Commit 973d755c authored by Dimitris Lampridis's avatar Dimitris Lampridis

hdl: introduce hello world test software for top testbench

Now have working lm32 and urv hello world sim.
parent f5dbdb5e
*.bit
*.bin
*.ngc
*~
#*
*.ini
*.log
work
*.vstf
*.wlf
*.version
*.cfg
*.bk
*#
*.bak
run.tcl
.emacs*
.#*
transcript
*.par
*.pcf
*.pad
*.ngr
*.ncd
*.gise
*.ptwx
*.twx
*.unroutes
*.ut
*.xpi
*.bgn
*.bld
*.cmd_log
*.drc
*.lso
*.ngd
*.prj
*.stx
*.syr
*.twr
*.xst
*_bitgen.xwbt
*_envsettings.html
*_map.map
*_map.mrp
*_map.ngm
*_map.xrpt
*_ngdbuild.xrpt
*_pad.csv
*_pad.txt
*_par.xrpt
*.html
*.xml
*_usage.xml
*_xst.xrpt
xlnx_auto_0_xdb
iseconfig
_ngo
_xmsgs
*.o
*.pdf
*.aux
*.out
*.psr
*.xdl
*.orig
pa.fromNcd.tcl
pa.fromNetlist.tcl
planAhead_run_*
*.vcd
*.wlf
work/
*.elf
.Xil
xst/
*stacktrace*
rtl/*.h
scp.sh
disasm.S
*.mif
*.asy
*.xco
*.debug
......@@ -16,3 +16,6 @@
[submodule "hdl/ip_cores/gn4124-core"]
path = hdl/ip_cores/gn4124-core
url = git://ohwr.org/hdl-core-lib/gn4124-core.git
[submodule "hdl/ip_cores/urv-core"]
path = hdl/ip_cores/urv-core
url = git://ohwr.org/hdl-core-lib/urv-core.git
general-cores @ 23f71bcc
Subproject commit 8cd05d796abf0e494a367c15ce4fde1535751efe
Subproject commit 23f71bcc79d8cf6d5a076c961e64003502fb1d47
gn4124-core @ 9b9625bb
Subproject commit e3a0bf97e125020c83bff6e40199a717e7fda738
Subproject commit 9b9625bb4270114266cd357f199d649f3d799f04
urv-core @ f1fcd338
Subproject commit f1fcd338aefb276b89c502c7c52d6e7b26cebdfe
wr-cores @ 69cc4cc3
Subproject commit 573ac5a938e53c6bedaee13b75e1c0c6c6e311db
Subproject commit 69cc4cc3132530c836cd57ce1b282e8377fe7a07
files = [
"mt_cpu_cb.vhd",
"mt_cpu_csr_wbgen2_pkg.vhd",
"mt_cpu_csr_wb.vhd",
"mt_cpu_iram.vhd",
"mt_cpu_lr_wbgen2_pkg.vhd",
"mt_cpu_lr_wb.vhd",
"mt_lm32_wrapper.vhd",
"mt_private_pkg.vhd",
"mt_urv_wrapper.vhd",
"mt_trace_profiler.vhd",
"mt_tpu_csr_wb.vhd",
"mt_tpu_csr_wbgen2_pkg.vhd"
];
"mt_cpu_cb.vhd",
"mt_cpu_csr_wbgen2_pkg.vhd",
"mt_cpu_csr_wb.vhd",
"mt_cpu_iram.vhd",
"mt_cpu_lr_wbgen2_pkg.vhd",
"mt_cpu_lr_wb.vhd",
"mt_lm32_wrapper.vhd",
"mt_private_pkg.vhd",
"mt_urv_wrapper.vhd",
"mt_trace_profiler.vhd",
"mt_tpu_csr_wb.vhd",
"mt_tpu_csr_wbgen2_pkg.vhd",
]
files = [ "mt_mqueue_host.vhd",
"mt_mqueue_remote.vhd",
"mt_rmq_outgoing_slot.vhd",
"mt_rmq_incoming_slot.vhd",
"mt_mqueue_irq_unit.vhd",
"mt_mqueue_pkg.vhd",
"mt_mqueue_slot.vhd",
"mt_mqueue_remote.vhd",
"mt_mqueue_wishbone_slave.vhd",
"mt_ethernet_tx_framer.vhd",
"mt_rmq_rx_deframer.vhd",
"mt_rmq_rx_path.vhd",
"mt_rmq_tx_path.vhd",
"mt_stream_register.vhd",
"mt_udp_tx_framer.vhd",
"mt_rmq_packet_output.vhd",
"mt_wr_sink.vhd",
"mt_wr_source.vhd"];
files = [
"mt_mqueue_host.vhd",
"mt_mqueue_remote.vhd",
"mt_rmq_outgoing_slot.vhd",
"mt_rmq_incoming_slot.vhd",
"mt_mqueue_irq_unit.vhd",
"mt_mqueue_pkg.vhd",
"mt_mqueue_slot.vhd",
"mt_mqueue_remote.vhd",
"mt_mqueue_wishbone_slave.vhd",
"mt_ethernet_tx_framer.vhd",
"mt_rmq_rx_deframer.vhd",
"mt_rmq_rx_path.vhd",
"mt_rmq_tx_path.vhd",
"mt_stream_register.vhd",
"mt_udp_tx_framer.vhd",
"mt_rmq_packet_output.vhd",
"mt_wr_sink.vhd",
"mt_wr_source.vhd",
]
files = ["mt_shared_mem.vhd"]
\ No newline at end of file
files = [
"mt_shared_mem.vhd",
]
*
!.gitignore
!Manifest.py
action = "synthesis"
target = "xilinx"
fetchto = "../../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "spec_top"
syn_project = "spec_mt_demo.xise"
top_module = "spec_top"
syn_tool = "ise"
modules = {
"local" : [
"../../../top/spec/mt_demo",
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/wr-cores.git",
"git://ohwr.org/hdl-core-lib/urv-core.git",
"git://ohwr.org/hdl-core-lib/gn4124-core.git",
],
}
action = "synthesis"
target="xilinx"
fetchto = "../../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "spec_top"
syn_project = "spec_wr_node_demo.xise"
top_module = "spec_top"
syn_tool = "ise"
modules = { "local" : [ "../../../top/spec/wr_node_demo" ] }
*
!.gitignore
!Manifest.py
action = "synthesis"
target = "xilinx"
fetchto = "../../../ip_cores"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg900"
syn_top = "svec_top"
syn_project = "svec_mt_demo.xise"
top_module = "svec_top"
syn_tool = "ise"
modules = {
"local" : [
"../../../top/svec/mt_demo",
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/wr-cores.git",
"git://ohwr.org/hdl-core-lib/urv-core.git",
"git://ohwr.org/hdl-core-lib/vme64x-core.git",
],
}
action = "synthesis"
target="xilinx"
fetchto = "../../../ip_cores"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg900"
syn_top = "svec_top"
syn_project = "svec_wr_node_demo.xise"
top_module = "svec_top"
syn_tool = "ise"
modules = { "local" : [ "../../../top/svec/wr_node_demo" ] }
`include "wrn_cpu_csr_regs.vh"
`include "mt_cpu_csr_regs.vh"
typedef class NodeCPUDbgQueue;
......@@ -13,7 +13,6 @@ class NodeCPUControl;
protected uint32_t core_count ,app_id;
// NodeCPUDbgQueue dbgq [$];
NodeCPUDbgQueue dbgq [$];
function new ( CBusAccessor bus_, input uint32_t base_);
......@@ -28,8 +27,6 @@ class NodeCPUControl;
task readl ( uint32_t r, ref uint32_t v );
uint64_t tmp;
bus.read (base + r, tmp );
//$display("Read %x : %x", base+r, tmp);
v= tmp;
endtask // readl
......@@ -37,8 +34,8 @@ class NodeCPUControl;
int i;
readl(`ADDR_WRN_CPU_CSR_APP_ID, app_id);
readl(`ADDR_WRN_CPU_CSR_CORE_COUNT, core_count);
readl(`ADDR_MT_CPU_CSR_APP_ID, app_id);
readl(`ADDR_MT_CPU_CSR_CORE_COUNT, core_count);
core_count&='hf;
......@@ -54,8 +51,8 @@ class NodeCPUControl;
for(i=0;i<core_count;i++)
begin
uint32_t memsize;
writel(`ADDR_WRN_CPU_CSR_CORE_SEL, i);
readl(`ADDR_WRN_CPU_CSR_CORE_MEMSIZE, memsize);
writel(`ADDR_MT_CPU_CSR_CORE_SEL, i);
readl(`ADDR_MT_CPU_CSR_CORE_MEMSIZE, memsize);
$display("Core %d: %d kB private memory", i, memsize/1024);
end
......@@ -67,25 +64,25 @@ class NodeCPUControl;
task reset_core(int core, int reset);
uint32_t rstr;
readl(`ADDR_WRN_CPU_CSR_RESET, rstr);
readl(`ADDR_MT_CPU_CSR_RESET, rstr);
if(reset)
rstr |= (1<<core);
else
rstr &= ~(1<<core);
writel(`ADDR_WRN_CPU_CSR_RESET, rstr);
writel(`ADDR_MT_CPU_CSR_RESET, rstr);
endtask // enable_cpu
task debug_int_enable(int core, int enable);
uint32_t imsk;
readl(`ADDR_WRN_CPU_CSR_DBG_IMSK, imsk);
readl(`ADDR_MT_CPU_CSR_DBG_IMSK, imsk);
if(enable)
imsk |= (1<<core);
else
imsk &= ~(1<<core);
writel(`ADDR_WRN_CPU_CSR_DBG_IMSK, imsk);
writel(`ADDR_MT_CPU_CSR_DBG_IMSK, imsk);
endtask // debug_int_enable
......@@ -97,7 +94,7 @@ class NodeCPUControl;
reset_core(core, 1);
writel(`ADDR_WRN_CPU_CSR_CORE_SEL, core);
writel(`ADDR_MT_CPU_CSR_CORE_SEL, core);
......@@ -109,28 +106,23 @@ class NodeCPUControl;
$fscanf(f,"%s %08x %08x", cmd,addr,data);
if(cmd == "write")
begin
writel(`ADDR_WRN_CPU_CSR_UADDR, addr);
writel(`ADDR_WRN_CPU_CSR_UDATA, data);
writel(`ADDR_MT_CPU_CSR_UADDR, addr);
writel(`ADDR_MT_CPU_CSR_UDATA, data);
q.push_back(data);
n++;
end
end
/* -----\/----- EXCLUDED -----\/-----
for(i=0;i<n;i++)
begin
uint32_t rv;
writel(`ADDR_WRN_CPU_CSR_UADDR, i);
readl(`ADDR_WRN_CPU_CSR_UDATA, rv);
$display("readback: addr %x d %x", i, rv);
writel(`ADDR_MT_CPU_CSR_UADDR, i);
readl(`ADDR_MT_CPU_CSR_UDATA, rv);
if(rv != q[i])
$display("verification error\n");
$display("verification error at %x, got %x, expected %x\n",
i, rv, q[i]);
end
-----/\----- EXCLUDED -----/\----- */
endtask
......@@ -149,7 +141,7 @@ class NodeCPUControl;
endtask // update
task set_smem_op(int op);
writel(`ADDR_WRN_CPU_CSR_SMEM_OP, op);
writel(`ADDR_MT_CPU_CSR_SMEM_OP, op);
endtask // set_smem_op
......@@ -176,12 +168,12 @@ class NodeCPUDbgQueue;
task update();
uint32_t rval;
cctl.readl(`ADDR_WRN_CPU_CSR_DBG_POLL , rval);
cctl.readl(`ADDR_MT_CPU_CSR_DBG_POLL , rval);
if(! (rval & (1<<core_id)))
return;
cctl.writel(`ADDR_WRN_CPU_CSR_CORE_SEL, core_id);
cctl.readl(`ADDR_WRN_CPU_CSR_DBG_MSG, rval);
cctl.writel(`ADDR_MT_CPU_CSR_CORE_SEL, core_id);
cctl.readl(`ADDR_MT_CPU_CSR_DBG_MSG, rval);
if(rval == 0)
......
......@@ -79,9 +79,9 @@ class MQueueHost;
endfunction // poll
function mqueue_message_t recv (int slot);
mqueue_message_t tmp = slots_in[slot][$];
slots_in[slot].pop_back();
return tmp;
mqueue_message_t ret = slots_in[slot][$];
mqueue_message_t tmp = slots_in[slot].pop_back();
return ret;
endfunction
task send (int slot, uint32_t data[$]);
......@@ -222,7 +222,8 @@ class MQueueHost;
task update();
uint32_t in_stat, irq_mask;
int i;
mqueue_message_t tmp;
if(!initialized)
init();
......@@ -248,7 +249,7 @@ class MQueueHost;
begin
if ( slots_out[i].size() )
begin
slots_out[i].pop_back();
tmp = slots_out[i].pop_back();
end
end
......
`define ADDR_MT_CPU_CSR_APP_ID 6'h0
`define ADDR_MT_CPU_CSR_RESET 6'h4
`define ADDR_MT_CPU_CSR_ENABLE 6'h8
`define ADDR_MT_CPU_CSR_UADDR 6'hc
`define MT_CPU_CSR_UADDR_ADDR_OFFSET 0
`define MT_CPU_CSR_UADDR_ADDR 32'h000fffff
`define ADDR_MT_CPU_CSR_CORE_SEL 6'h10
`define ADDR_MT_CPU_CSR_CORE_COUNT 6'h14
`define ADDR_MT_CPU_CSR_CORE_MEMSIZE 6'h18
`define ADDR_MT_CPU_CSR_UDATA 6'h1c
`define ADDR_MT_CPU_CSR_DBG_JTAG 6'h20
`define MT_CPU_CSR_DBG_JTAG_JDATA_OFFSET 0
`define MT_CPU_CSR_DBG_JTAG_JDATA 32'h000000ff
`define MT_CPU_CSR_DBG_JTAG_JADDR_OFFSET 8
`define MT_CPU_CSR_DBG_JTAG_JADDR 32'h00000700
`define MT_CPU_CSR_DBG_JTAG_RSTN_OFFSET 16
`define MT_CPU_CSR_DBG_JTAG_RSTN 32'h00010000
`define MT_CPU_CSR_DBG_JTAG_TCK_OFFSET 17
`define MT_CPU_CSR_DBG_JTAG_TCK 32'h00020000
`define MT_CPU_CSR_DBG_JTAG_UPDATE_OFFSET 18
`define MT_CPU_CSR_DBG_JTAG_UPDATE 32'h00040000
`define ADDR_MT_CPU_CSR_DBG_MSG 6'h24
`define MT_CPU_CSR_DBG_MSG_DATA_OFFSET 0
`define MT_CPU_CSR_DBG_MSG_DATA 32'h000000ff
`define ADDR_MT_CPU_CSR_DBG_POLL 6'h28
`define MT_CPU_CSR_DBG_POLL_READY_OFFSET 0
`define MT_CPU_CSR_DBG_POLL_READY 32'h000000ff
`define ADDR_MT_CPU_CSR_DBG_IMSK 6'h2c
`define MT_CPU_CSR_DBG_IMSK_ENABLE_OFFSET 0
`define MT_CPU_CSR_DBG_IMSK_ENABLE 32'h000000ff
`define ADDR_MT_CPU_CSR_SMEM_OP 6'h30
`define ADDR_D3S_RSTR 7'h0
`define D3S_RSTR_PLL_RST_OFFSET 0
`define D3S_RSTR_PLL_RST 32'h00000001
`define ADDR_D3S_TCR 7'h4
`define D3S_TCR_WR_LOCK_EN_OFFSET 0
`define D3S_TCR_WR_LOCK_EN 32'h00000001
`define D3S_TCR_WR_LOCKED_OFFSET 1
`define D3S_TCR_WR_LOCKED 32'h00000002
`define D3S_TCR_WR_TIME_VALID_OFFSET 2
`define D3S_TCR_WR_TIME_VALID 32'h00000004
`define D3S_TCR_WR_LINK_OFFSET 3
`define D3S_TCR_WR_LINK 32'h00000008
`define ADDR_D3S_WR_FREQ 7'h8
`define D3S_WR_FREQ_METER_OFFSET 0
`define D3S_WR_FREQ_METER 32'hffffffff
`define ADDR_D3S_GPIOR 7'hc
`define D3S_GPIOR_SI57X_SCL_OFFSET 0
`define D3S_GPIOR_SI57X_SCL 32'h00000001
`define D3S_GPIOR_SI57X_SDA_OFFSET 1
`define D3S_GPIOR_SI57X_SDA 32'h00000002
`define D3S_GPIOR_SPI_CS_ADC_OFFSET 2
`define D3S_GPIOR_SPI_CS_ADC 32'h00000004
`define D3S_GPIOR_SPI_SCK_OFFSET 3
`define D3S_GPIOR_SPI_SCK 32'h00000008
`define D3S_GPIOR_SPI_MOSI_OFFSET 4
`define D3S_GPIOR_SPI_MOSI 32'h00000010
`define D3S_GPIOR_SPI_MISO_OFFSET 5
`define D3S_GPIOR_SPI_MISO 32'h00000020
`define D3S_GPIOR_SERDES_PLL_LOCKED_OFFSET 6
`define D3S_GPIOR_SERDES_PLL_LOCKED 32'h00000040
`define ADDR_D3S_SSR 7'h10
`define ADDR_D3S_CR 7'h14
`define D3S_CR_ENABLE_OFFSET 0
`define D3S_CR_ENABLE 32'h00000001
`define ADDR_D3S_RL_ERR_MIN 7'h18
`define ADDR_D3S_RL_ERR_MAX 7'h1c
`define ADDR_D3S_RL_LENGTH_MAX 7'h20
`define ADDR_D3S_TRANSIENT_THRESHOLD_PHASE 7'h24
`define ADDR_D3S_TRANSIENT_THRESHOLD_COUNT 7'h28
`define ADDR_D3S_CNT_FIXED 7'h2c
`define ADDR_D3S_CNT_TRANSIENT 7'h30
`define ADDR_D3S_CNT_RL 7'h34
`define ADDR_D3S_CNT_TSTAMP 7'h38
`define ADDR_D3S_ADC_R0 7'h3c
`define D3S_ADC_R0_PAYLOAD_OFFSET 0
`define D3S_ADC_R0_PAYLOAD 32'hffffffff
`define ADDR_D3S_ADC_CSR 7'h40
`define D3S_ADC_CSR_FULL_OFFSET 16
`define D3S_ADC_CSR_FULL 32'h00010000
`define D3S_ADC_CSR_EMPTY_OFFSET 17
`define D3S_ADC_CSR_EMPTY 32'h00020000
`define D3S_ADC_CSR_CLEAR_BUS_OFFSET 18
`define D3S_ADC_CSR_CLEAR_BUS 32'h00040000
`define D3S_ADC_CSR_USEDW_OFFSET 0
`define D3S_ADC_CSR_USEDW 32'h00003fff
`define ADDR_D3SS_RSTR 6'h0
`define D3SS_RSTR_PLL_RST_OFFSET 0
`define D3SS_RSTR_PLL_RST 32'h00000001
`define ADDR_D3SS_TCR 6'h4
`define D3SS_TCR_WR_LOCK_EN_OFFSET 0
`define D3SS_TCR_WR_LOCK_EN 32'h00000001
`define D3SS_TCR_WR_LOCKED_OFFSET 1
`define D3SS_TCR_WR_LOCKED 32'h00000002
`define D3SS_TCR_WR_TIME_VALID_OFFSET 2
`define D3SS_TCR_WR_TIME_VALID 32'h00000004
`define D3SS_TCR_WR_LINK_OFFSET 3
`define D3SS_TCR_WR_LINK 32'h00000008
`define ADDR_D3SS_GPIOR 6'h8
`define D3SS_GPIOR_PLL_SYS_CS_N_OFFSET 0
`define D3SS_GPIOR_PLL_SYS_CS_N 32'h00000001
`define D3SS_GPIOR_PLL_SYS_RESET_N_OFFSET 1
`define D3SS_GPIOR_PLL_SYS_RESET_N 32'h00000002
`define D3SS_GPIOR_PLL_SCLK_OFFSET 2
`define D3SS_GPIOR_PLL_SCLK 32'h00000004
`define D3SS_GPIOR_PLL_SDIO_OFFSET 3
`define D3SS_GPIOR_PLL_SDIO 32'h00000008
`define D3SS_GPIOR_PLL_SDIO_DIR_OFFSET 4
`define D3SS_GPIOR_PLL_SDIO_DIR 32'h00000010
`define D3SS_GPIOR_PLL_VCXO_RESET_N_OFFSET 5
`define D3SS_GPIOR_PLL_VCXO_RESET_N 32'h00000020
`define D3SS_GPIOR_PLL_VCXO_CS_N_OFFSET 6
`define D3SS_GPIOR_PLL_VCXO_CS_N 32'h00000040
`define D3SS_GPIOR_PLL_VCXO_SDO_OFFSET 7
`define D3SS_GPIOR_PLL_VCXO_SDO 32'h00000080
`define D3SS_GPIOR_ADF_CE_OFFSET 8
`define D3SS_GPIOR_ADF_CE 32'h00000100
`define D3SS_GPIOR_ADF_CLK_OFFSET 9
`define D3SS_GPIOR_ADF_CLK 32'h00000200
`define D3SS_GPIOR_ADF_LE_OFFSET 10
`define D3SS_GPIOR_ADF_LE 32'h00000400
`define D3SS_GPIOR_ADF_DATA_OFFSET 11
`define D3SS_GPIOR_ADF_DATA 32'h00000800
`define D3SS_GPIOR_SERDES_PLL_LOCKED_OFFSET 12
`define D3SS_GPIOR_SERDES_PLL_LOCKED 32'h00001000
`define ADDR_D3SS_CR 6'hc
`define D3SS_CR_ENABLE_OFFSET 0
`define D3SS_CR_ENABLE 32'h00000001
`define ADDR_D3SS_REC_DELAY_COARSE 6'h10
`define ADDR_D3SS_FREV_TS_SEC 6'h14
`define ADDR_D3SS_FREV_TS_NS 6'h18
`define ADDR_D3SS_FREV_CR 6'h1c
`define D3SS_FREV_CR_VALID_OFFSET 0
`define D3SS_FREV_CR_VALID 32'h00000001
`define D3SS_FREV_CR_READY_OFFSET 1
`define D3SS_FREV_CR_READY 32'h00000002
`define ADDR_D3SS_PHFIFO_R0 6'h20
`define D3SS_PHFIFO_R0_PAYLOAD_OFFSET 0
`define D3SS_PHFIFO_R0_PAYLOAD 32'hffffffff
`define ADDR_D3SS_PHFIFO_CSR 6'h24
`define D3SS_PHFIFO_CSR_FULL_OFFSET 16
`define D3SS_PHFIFO_CSR_FULL 32'h00010000
`define D3SS_PHFIFO_CSR_EMPTY_OFFSET 17
`define D3SS_PHFIFO_CSR_EMPTY 32'h00020000
`define D3SS_PHFIFO_CSR_CLEAR_BUS_OFFSET 18
`define D3SS_PHFIFO_CSR_CLEAR_BUS 32'h00040000
`define D3SS_PHFIFO_CSR_USEDW_OFFSET 0
`define D3SS_PHFIFO_CSR_USEDW 32'h00003fff
`define ADDR_WRN_CPU_CSR_APP_ID 6'h0
`define ADDR_WRN_CPU_CSR_RESET 6'h4
`define ADDR_WRN_CPU_CSR_ENABLE 6'h8
`define ADDR_WRN_CPU_CSR_UADDR 6'hc
`define WRN_CPU_CSR_UADDR_ADDR_OFFSET 0
`define WRN_CPU_CSR_UADDR_ADDR 32'h000fffff
`define ADDR_WRN_CPU_CSR_CORE_SEL 6'h10
`define ADDR_WRN_CPU_CSR_CORE_COUNT 6'h14
`define ADDR_WRN_CPU_CSR_CORE_MEMSIZE 6'h18
`define ADDR_WRN_CPU_CSR_UDATA 6'h1c
`define ADDR_WRN_CPU_CSR_DBG_JTAG 6'h20
`define WRN_CPU_CSR_DBG_JTAG_JDATA_OFFSET 0
`define WRN_CPU_CSR_DBG_JTAG_JDATA 32'h000000ff
`define WRN_CPU_CSR_DBG_JTAG_JADDR_OFFSET 8
`define WRN_CPU_CSR_DBG_JTAG_JADDR 32'h00000700
`define WRN_CPU_CSR_DBG_JTAG_RSTN_OFFSET 16
`define WRN_CPU_CSR_DBG_JTAG_RSTN 32'h00010000
`define WRN_CPU_CSR_DBG_JTAG_TCK_OFFSET 17
`define WRN_CPU_CSR_DBG_JTAG_TCK 32'h00020000
`define WRN_CPU_CSR_DBG_JTAG_UPDATE_OFFSET 18
`define WRN_CPU_CSR_DBG_JTAG_UPDATE 32'h00040000
`define ADDR_WRN_CPU_CSR_DBG_MSG 6'h24
`define WRN_CPU_CSR_DBG_MSG_DATA_OFFSET 0
`define WRN_CPU_CSR_DBG_MSG_DATA 32'h000000ff
`define ADDR_WRN_CPU_CSR_DBG_POLL 6'h28
`define WRN_CPU_CSR_DBG_POLL_READY_OFFSET 0
`define WRN_CPU_CSR_DBG_POLL_READY 32'h000000ff
`define ADDR_WRN_CPU_CSR_DBG_IMSK 6'h2c
`define WRN_CPU_CSR_DBG_IMSK_ENABLE_OFFSET 0
`define WRN_CPU_CSR_DBG_IMSK_ENABLE 32'h000000ff
`define ADDR_WRN_CPU_CSR_SMEM_OP 6'h30
/*
* This work is part of the White Rabbit project
*
* Copyright (C) 2011 CERN (www.cern.ch)
* Author: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
*
* Released according to the GNU GPL, version 2 or any later version.
*/
#include <stdio.h>
#include <stdlib.h>
int main(int argc, char *argv[])
{
if (argc < 2)
return -1;
FILE *f = fopen(argv[1], "rb");
if (!f)
return -1;
unsigned char x[4];
int i = 0;
fseek(f, 0, SEEK_END);
int n = (ftell(f) + 3) / 4;
rewind(f);
printf("Argc: %d\n", argc);
if(argc > 2)
n = atoi(argv[2]);
while (!feof(f)) {
fread(x, 1, 4, f);
printf("write %x %02X%02X%02X%02X\n", i++, x[0], x[1], x[2],
x[3]);
}
for (; i < n;) {
printf("write %x %02X%02X%02X%02X\n", i++, 0, 0, 0, 0);
}
fclose(f);
return 0;
}
......@@ -8,11 +8,11 @@ OBJCOPY = $(CROSS_COMPILE)objcopy
SIZE = $(CROSS_COMPILE)size
CFLAGS = -DWRNODE_RT -g -O3 -I. -I../common -I../../include -I../include/ -mmultiply-enabled -mbarrel-shift-enabled -ffunction-sections -fdata-sections -Wl,--gc-sections
OBJS += ../common/lm32/wrn-crt0.o ../common/rt-common.o ../common/printf.o ../common/vsprintf-xint.o
LDSCRIPT = ../common/lm32/wrnode.ld
OBJS += ../common/lm32/crt0.o ../common/rt-common.o ../common/printf.o ../common/vsprintf-xint.o
LDSCRIPT = ../common/lm32/mt.ld
LDFLAGS= -ffunction-sections -fdata-sections -Wl,--gc-sections
$(OUTPUT): $(LDSCRIPT) $(OBJS)
$(OUTPUT): $(LDSCRIPT) $(OBJS) ../common/genraminit
${CC} -o $(OUTPUT).elf -nostartfiles $(OBJS) -T $(LDSCRIPT) -lgcc -lc $(LDFLAGS)
${OBJCOPY} --remove-section .smem -O binary $(OUTPUT).elf $(OUTPUT).bin
${OBJDUMP} -S $(OUTPUT).elf > disasm.S
......@@ -21,6 +21,6 @@ $(OUTPUT): $(LDSCRIPT) $(OBJS)
clean:
rm -f $(OBJS) $(OUTPUT).bin
install:
cp $(OUTPUT).bin /acc/local/share/firmware/list
\ No newline at end of file
cp $(OUTPUT).bin /acc/local/share/firmware/list
......@@ -113,7 +113,7 @@ jump_table_return:
lw t5,120(a0)
lw t6,124(a0)
lw a0,40(a0)
eret
mret
.weak undefined_handler
undefined_handler:
......
......@@ -7,25 +7,25 @@ OBJDUMP = $(CROSS_COMPILE)objdump
OBJCOPY = $(CROSS_COMPILE)objcopy
SIZE = $(CROSS_COMPILE)size
CFLAGS = -DWRNODE_RT -g -O2 -m32 -I. -I../common -I../../include -I../include/ -march=RV32IM
CFLAGS = -DWRNODE_RT -g -O2 -I. -I../common -I../../include -I../include/ -march=rv32im -mabi=ilp32
OBJS += ../common/urv/crt0.o ../common/urv/irq.o ../common/urv/emulate.o ../common/rt-common.o ../common/printf.o ../common/vsprintf-xint.o
LDSCRIPT = ../common/urv/mt.ld
$(OUTPUT): $(LDSCRIPT) $(OBJS)
${CC} -m32 -flto -g -o $(OUTPUT).elf -nostartfiles $(OBJS) -T $(LDSCRIPT) -lgcc -lc
${CC} $(CFLAGS) -o $(OUTPUT).elf -nostartfiles $(OBJS) -T $(LDSCRIPT) -lgcc -lc
${OBJCOPY} --remove-section .smem -O binary $(OUTPUT).elf $(OUTPUT).bin
${OBJDUMP} -S $(OUTPUT).elf > disasm.S
../common/genraminit $(OUTPUT).bin > $(OUTPUT).ram
$(SIZE) $(OUTPUT).elf
../common/urv/emulate.o: ../common/urv/emulate.c
${CC} -O2 -m32 -march=RV32I -m32 -c $^ -o $@ -I.
${CC} $(CFLAGS) -march=rv32i -c $^ -o $@ -I.
%.o: %.S
${CC} -march=RV32I -m32 -c $^ -o $@
${CC} $(CFLAGS) -c $^ -o $@
clean:
rm -f $(OBJS) $(OUTPUT).bin
install:
cp $(OUTPUT).bin /acc/local/share/firmware/list
\ No newline at end of file
cp $(OUTPUT).bin /acc/local/share/firmware/list
CPU=urv
CPU ?= urv
OBJS = hello.o
OUTPUT = hello
include ../common/$(CPU)/mt.mk
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work/
Makefile
modelsim.ini
transcript
*.wlf
......@@ -8,12 +8,13 @@ sim_top = "main"
action = "simulation"
target = "xilinx"
syn_device = "xc6slx150t"
vcom_opt = "-mixedsvvh"
vcom_opt = "-93 -mixedsvvh"
include_dirs = [
"../include",
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/",
"../../ip_cores/general-cores/sim/",
"../../ip_cores/urv-core/rtl/",
]
files = [
......@@ -23,8 +24,12 @@ files = [
modules = {
"local" : [
"../../rtl",
"../../ip_cores/etherbone-core",
"../../ip_cores/general-cores",
"../../ip_cores/wr-cores",
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/wr-cores.git",
"git://ohwr.org/hdl-core-lib/urv-core.git",
],
}
fetchto = "../../ip_cores"
import wishbone_pkg::*;
import wr_node_pkg::*;
`include "vhd_wishbone_master.svh"
`include "cpu_csr_driver.svh"
`include "mqueue_host.svh"
class CWRNode;
function new ( CBusAccessor acc_, input uint32_t base_);
endfunction // new
endclass // CWRNode
`timescale 1ns/1ps
module main;
......@@ -24,132 +15,67 @@ module main;
always #4ns clk_cpu <= ~clk_cpu;
always@(posedge clk_cpu)
clk_sys <= ~clk_sys;
initial begin
repeat(20) @(posedge clk_sys);
rst_n = 1;
end
wire host_irq;
wire host_irq;
IVHDWishboneMaster Host ( clk_sys, rst_n );
wr_node_core # (
.g_double_core_clock(1'b0)
)DUT (
.clk_i (clk_sys),
.clk_cpu_i(clk_cpu),
.rst_n_i (rst_n),
.host_slave_i (Host.master.out),
.host_slave_o (Host.master.in),
.host_irq_o(host_irq)
);
mock_turtle_core #
(
.g_double_core_clock(1'b0),
//.g_cpu_arch("LM32")
.g_cpu_arch("URV")
)
DUT (
.clk_i (clk_sys),
.clk_cpu_i(clk_cpu),
.rst_n_i (rst_n),
.host_slave_i (Host.master.out),
.host_slave_o (Host.master.in),
.host_irq_o(host_irq)
);
initial begin
NodeCPUControl cpu_csr;
MQueueHost hmq;
uint64_t rv;
CBusAccessor host_acc;
#10us;
host_acc = Host.get_accessor();
cpu_csr = new ( Host.get_accessor(), 'hc000 );
hmq = new ( Host.get_accessor(), 0 );
// enable all IRQs
host_acc.write(`MQUEUE_GCR_IRQ_MASK, 'hffff);
cpu_csr.init();
cpu_csr.load_firmware (0, "../../sw/debug-test/debug-test.ram");
//cpu_csr.load_firmware (0, "../sw/hw-tests/hello/hello.ram.lm32");
cpu_csr.load_firmware (0, "../sw/hw-tests/hello/hello.ram.urv");
cpu_csr.reset_core(0, 0);
/* -----\/----- EXCLUDED -----\/-----
cpu_csr.load_firmware (1, "../../sw/debug-test/debug-test.ram");
cpu_csr.reset_core(1, 0);
-----/\----- EXCLUDED -----/\----- */
$display("CPU0 started\n");
/* -----\/----- EXCLUDED -----\/-----
forever begin
cpu_csr.update();
@(posedge clk_sys);
end
-----/\----- EXCLUDED -----/\----- */
/* -----\/----- EXCLUDED -----\/-----
host_acc.read('h08, rv);
$display("GCR_IRQ_MASK %x", rv);
host_acc.read('h04, rv);
$display("GCR_STATUS %x", rv);
hmq.send(0, '{1,2,3} );
#20us;
$display("GCR_STATUS %x", rv);
forever begin
hmq.update();
#1us;
end
-----/\----- EXCLUDED -----/\----- */
/* -----\/----- EXCLUDED -----\/-----
cpu_csr.set_smem_op(`SMEM_OP_DIRECT);
host_acc.write('h10000, 'hcafebabe);
host_acc.write('h10004, 'hdeadbeef);
host_acc.read('h10000, rv);
$display("smem-read: %x", rv);
host_acc.read('h10004, rv);
$display("smem-read: %x", rv);
cpu_csr.set_smem_op(`SMEM_OP_ADD);
$display("Atomic add...\n");
host_acc.write('h10000, 'h1);
host_acc.write('h10004, 'h2);
host_acc.read('h10000, rv);
$display("smem-read: %x", rv);
host_acc.read('h10004, rv);
$display("smem-read: %x", rv);
-----/\----- EXCLUDED -----/\----- */
$error("Loop");
forever begin
cpu_csr.update();
while(host_irq)
hmq.update();
#1us;
hmq.update();
#1us;
@(posedge clk_sys);
end
end // initial begin
endmodule
......@@ -5,4 +5,4 @@ set NumericStdNoWarnings 1
do wave.do
radix -hexadecimal
run 200us
\ No newline at end of file
run 1000us
\ No newline at end of file
files = [ "synthesis_descriptor.vhd", "spec_top.vhd", "spec_top.ucf" ]
fetchto = "../../ip_cores"
files = [
"synthesis_descriptor.vhd",
"spec_top.vhd",
"spec_top.ucf",
]
modules = {
"local" : [ "../../../rtl",
"../mt_template",
"../../../ip_cores/gn4124-core" ],
}
"local" : [
"../mt_template",
],
}
......@@ -222,7 +222,7 @@ net "leds_n_o[3]" IOSTANDARD=LVCMOS18;
# GN4124
NET "l_rst_n" TIG;
NET "U_Node_Template/gen_with_gennum.U_GN4124_Core/rst_*" TIG;
NET "U_MT_Template/gen_with_gennum.U_GN4124_Core/rst_*" TIG;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/01/20
#INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
#INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
......@@ -232,7 +232,7 @@ NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
NET "U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk" TNM_NET = U_Node_Template/U_GN4124_Core/cmp_clk_in/P_clk;
TIMESPEC TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_P_clk = PERIOD "U_Node_Template/U_GN4124_Core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
NET "U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback" TNM_NET = U_Node_Template/U_GN4124_Core/cmp_clk_in/feedback;
TIMESPEC TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_feedback = PERIOD "U_Node_Template/U_GN4124_Core/cmp_clk_in/feedback" 5 ns HIGH 50%;
NET "U_MT_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk" TNM_NET = U_MT_Template/U_GN4124_Core/cmp_clk_in/P_clk;
TIMESPEC TS_U_MT_Template_U_GN4124_Core_cmp_clk_in_P_clk = PERIOD "U_MT_Template/U_GN4124_Core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
NET "U_MT_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback" TNM_NET = U_MT_Template/U_GN4124_Core/cmp_clk_in/feedback;
TIMESPEC TS_U_MT_Template_U_GN4124_Core_cmp_clk_in_feedback = PERIOD "U_MT_Template/U_GN4124_Core/cmp_clk_in/feedback" 5 ns HIGH 50%;
files = [ "spec_mt_pkg.vhd",
"spec_mt_template.vhd",
"spec_reset_gen.vhd" ];
files = [
"spec_mt_pkg.vhd",
"spec_mt_template.vhd",
"spec_reset_gen.vhd"
]
modules = { "local" : [ "../../../rtl" ] };
modules = {
"local" : [
"../../../rtl",
],
}
files = [ "synthesis_descriptor.vhd", "svec_top.vhd", "svec_top.ucf" ]
fetchto = "../../ip_cores"
files = [
"synthesis_descriptor.vhd",
"svec_top.vhd",
"svec_top.ucf",
]
modules = {
"local" : [ "../../../rtl",
"../mt_template",
"../../../ip_cores/vme64x-core" ],
}
"local" : [
"../mt_template",
],
}
files = [ "svec_mt_pkg.vhd",
"svec_mt_template.vhd",
"bicolor_led_ctrl.vhd",
"bicolor_led_ctrl_pkg.vhd" ];
files = [
"svec_mt_pkg.vhd",
"svec_mt_template.vhd",
"bicolor_led_ctrl.vhd",
"bicolor_led_ctrl_pkg.vhd",
]
modules = {
"local" : [
"../../../rtl",
],
}
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2014-04-01
-- Last update: 2017-04-24
-- Last update: 2018-03-08
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -43,15 +43,15 @@ library work;
use work.wishbone_pkg.all;
use work.mock_turtle_pkg.all;
use work.mt_mqueue_pkg.all;
use work.xvme64x_core_pkg.all;
use work.vme64x_pkg.all;
package svec_mt_pkg is
constant c_unused_wisbone_slave_out : t_wishbone_slave_out :=
('1', '0', '0', '0', '0', x"deadbeef");
constant c_unused_fmc0_record : t_sdb_record := f_sdb_embed_device(cc_dummy_sdb_device, x"00010000");
constant c_unused_fmc1_record : t_sdb_record := f_sdb_embed_device(cc_dummy_sdb_device, x"00018000");
constant c_unused_fmc0_record : t_sdb_record := f_sdb_embed_device(cc_dummy_sdb_device, x"00001000");
constant c_unused_fmc1_record : t_sdb_record := f_sdb_embed_device(cc_dummy_sdb_device, x"00004000");
component svec_mt_template is
......
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2014-04-01
-- Last update: 2017-04-26
-- Last update: 2018-03-08
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -49,7 +49,7 @@ use ieee.numeric_std.all;
use work.svec_mt_pkg.all;
use work.wishbone_pkg.all;
use work.wr_fabric_pkg.all;
use work.xvme64x_core_pkg.all;
use work.vme64x_pkg.all;
use work.mock_turtle_pkg.all;
use work.gencores_pkg.all;
use work.wrcore_pkg.all;
......@@ -688,7 +688,7 @@ begin
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_softpll_enable_debugger => false,
g_dpram_initf => "wrc.bram")
g_dpram_initf => "../../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram")
port map (
clk_sys_i => clk_sys,
clk_dmtd_i => clk_dmtd,
......@@ -1048,12 +1048,10 @@ begin
fp_gpio1_a2b_o <= mt_gpio_out(24);
fp_gpio2_a2b_o <= mt_gpio_out(25);
fp_gpio34_a2b_o <= mt_gpio_out(26);
fp_gpio1_a2b_o <= wrn_gpio_out(24);
mt_gpio_in(0) <= fp_gpio1_b;
mt_gpio_in(1) <= fp_gpio2_b;
mt_gpio_in(2) <= fp_gpio3_b;
mt_gpio_in(3) <= fp_gpio4_b;
fp_gpio2_a2b_o <= wrn_gpio_out(25);
fp_gpio1_b <= 'Z' when mt_gpio_out(24) = '0' else mt_gpio_out(0);
fp_gpio2_b <= 'Z' when mt_gpio_out(25) = '0' else mt_gpio_out(1);
fp_gpio3_b <= 'Z' when mt_gpio_out(26) = '0' else mt_gpio_out(2);
......
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