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Commit 2cc7927e authored by Dimitris Lampridis's avatar Dimitris Lampridis
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doc: group together all HDL simulations

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doc/demos/fmc-spec-carrier.rst
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......@@ -76,27 +76,6 @@ inputs are copies of the same signals. The mapping of these 8 signals is the fol
All mentioned peripherals (WB crossbar, VIC, WB GPIO) are available as part of `OHWR
general-cores`_. The SPEC demo also uses the Gennum `GN4124 core`_ to provide the host interface.
Simulation
----------
.. note:: read :ref:`hdl:sim` chapter in order to run a simulation.
The spec_mt_demo testbench uses the top-level module as the Device Under Test (DUT).
It loads and executes a simple "Hello World" in the first CPU.
The aim of this testbench is to simply verify that the SPEC Demo design is working.
The expected output from the simulation is::
App ID: 0xd331d331
Core count: 2
UART MSG from core 0: Hello World!
UART MSG from core 0:
.. note::
The spec_mt_demo testbench expects an already compiled software binary under
*demos/hello_world/firmware/fw-01*. Please compile the software prior to running the simulation.
Software
=========
......
doc/demos/fmc-svec-carrier.rst
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......@@ -81,29 +81,6 @@ signals. The mapping of these 24 signals is the following:
All mentioned peripherals (WB crossbar, VIC, WB GPIO) are available as part of `OHWR
general-cores`_. This demo also uses the `VME64x core`_ to provide the host interface.
Simulation
----------
.. note:: read :ref:`hdl:sim` chapter in order to run a simulation.
The spec_mt_demo testbench uses the top-level module as the Device Under Test
(DUT). It loads and executes a simple "Hello World" in the first CPU.
The aim of this testbench is to simply verify that the SVEC demo design is
working.
The expected output from the simulation is::
App ID: 0xd330d330
Core count: 2
UART MSG from core 0: Hello World!
UART MSG from core 0:
.. note::
The svec_mt_demo testbench expects an already compiled software binary under
*demos/hello_world/firmware/fw-01*. Please compile the software prior to
running the simulation.
Software
=========
......
doc/hdl/index.rst
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......@@ -547,6 +547,48 @@ The expected output from the simulation is::
The mt_eth_ep testbench expects an already compiled software binary under
*tests/firmware/rmq-udp-send*. Please compile the software prior to running the simulation.
spec_mt_demo
------------
The spec_mt_demo testbench uses the top-level module of the :ref:`demo:spec` as the Device Under
Test (DUT). It loads and executes a simple "hello world" demo program on the first CPU.
The purpose of this testbench is mainly to verify that the :ref:`demo:spec` HDL design is
working. To this end, the testbench simply instantiates the top-level and waits for the
firmware to print the "hello world" message on the serial console.
The expected output from the simulation is::
App ID: 0xd331d331
Core count: 2
UART MSG from core 0: Hello World!
UART MSG from core 0:
.. note::
The spec_mt_demo testbench expects an already compiled software binary under
*demos/hello_world*. Please compile the software prior to running the simulation.
svec_mt_demo
------------
The svec_mt_demo testbench uses the top-level module of the :ref:`demo:svec` as the Device Under
Test (DUT). It loads and executes a simple "hello world" demo program on the first CPU.
The purpose of this testbench is mainly to verify that the :ref:`demo:svec` HDL design is
working. To this end, the testbench simply instantiates the top-level and waits for the
firmware to print the "hello world" message on the serial console.
The expected output from the simulation is::
App ID: 0xd330d330
Core count: 2
UART MSG from core 0: Hello World!
UART MSG from core 0:
.. note::
The svec_mt_demo testbench expects an already compiled software binary under
*demos/hello_world*. Please compile the software prior to running the simulation.
.. _OHWR general-cores: https://www.ohwr.org/project/general-cores/wiki
.. _White Rabbit PTP Core: https://www.ohwr.org/project/wr-cores/wiki/Wrpc_core/wiki
.. _Hdlmake: https://www.ohwr.org/project/hdl-make/wiki
......
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