Commit 04fa428e authored by Dimitris Lampridis's avatar Dimitris Lampridis

hdl: update VME64x core to v2 for SVEC demo

parent 3575b2a5
vme64x-core @ 258f8f68
Subproject commit aa37242a6ef7a317360fe730cf349d1cdf02ac9a
Subproject commit 258f8f68fddf0223d7e377d1c75b8fa109410ca9
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2014-04-01
-- Last update: 2015-07-23
-- Last update: 2018-03-08
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -43,7 +43,7 @@ library work;
use work.wishbone_pkg.all;
use work.wr_node_pkg.all;
use work.wrn_mqueue_pkg.all;
use work.xvme64x_core_pkg.all;
use work.vme64x_pkg.all;
package svec_node_pkg is
......
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2014-04-01
-- Last update: 2015-08-26
-- Last update: 2018-03-08
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -49,7 +49,7 @@ use ieee.numeric_std.all;
use work.svec_node_pkg.all;
use work.wishbone_pkg.all;
use work.wr_fabric_pkg.all;
use work.xvme64x_core_pkg.all;
use work.vme64x_pkg.all;
use work.wr_node_pkg.all;
use work.etherbone_pkg.all;
use work.gencores_pkg.all;
......@@ -284,6 +284,9 @@ architecture rtl of svec_node_template is
signal VME_ADDR_b_out : std_logic_vector(31 downto 1);
signal VME_LWORD_n_b_out, VME_DATA_DIR_int, VME_ADDR_DIR_int : std_logic;
signal VME_BERR_n : std_logic;
signal VME_IRQ_n : std_logic_vector(6 downto 0);
signal dac_hpll_load_p1 : std_logic;
signal dac_dpll_load_p1 : std_logic;
signal dac_hpll_data : std_logic_vector(15 downto 0);
......@@ -583,38 +586,45 @@ begin
U_VME_Core : xvme64x_core
generic map (
g_adem_a24 => x"fff80000")
g_CLOCK_PERIOD => 16,
g_DECODE_AM => TRUE,
g_USER_CSR_EXT => FALSE,
g_WB_GRANULARITY => BYTE,
g_MANUFACTURER_ID => c_CERN_ID,
g_BOARD_ID => c_SVEC_ID,
g_REVISION_ID => c_SVEC_REVISION_ID,
g_PROGRAM_ID => c_SVEC_PROGRAM_ID)
port map (
clk_i => clk_sys,
rst_n_i => powerup_rst_n,
VME_AS_n_i => VME_AS_n_i,
VME_RST_n_i => powerup_rst_n,
VME_WRITE_n_i => VME_WRITE_n_i,
VME_AM_i => VME_AM_i,
VME_DS_n_i => VME_DS_n_i,
VME_GA_i => VME_GA_i,
VME_BERR_o => VME_BERR_o,
VME_DTACK_n_o => VME_DTACK_n_o,
VME_RETRY_n_o => VME_RETRY_n_o,
VME_RETRY_OE_o => VME_RETRY_OE_o,
VME_LWORD_n_b_i => VME_LWORD_n_b,
VME_LWORD_n_b_o => VME_LWORD_n_b_out,
VME_ADDR_b_i => VME_ADDR_b,
VME_DATA_b_o => VME_DATA_b_out,
VME_ADDR_b_o => VME_ADDR_b_out,
VME_DATA_b_i => VME_DATA_b,
VME_IRQ_n_o => VME_IRQ_n_o,
VME_IACK_n_i => VME_IACK_n_i,
VME_IACKIN_n_i => VME_IACKIN_n_i,
VME_IACKOUT_n_o => VME_IACKOUT_n_o,
VME_DTACK_OE_o => VME_DTACK_OE_o,
VME_DATA_DIR_o => VME_DATA_DIR_int,
VME_DATA_OE_N_o => VME_DATA_OE_N_o,
VME_ADDR_DIR_o => VME_ADDR_DIR_int,
VME_ADDR_OE_N_o => VME_ADDR_OE_N_o,
master_o => cnx_slave_in(c_MASTER_VME),
master_i => cnx_slave_out(c_MASTER_VME),
irq_i => vic_master_irq);
vme_i.as_n => VME_AS_n_i,
vme_i.rst_n => powerup_rst_n,
vme_i.write_n => VME_WRITE_n_i,
vme_i.am => VME_AM_i,
vme_i.ds_n => VME_DS_n_i,
vme_i.ga => VME_GA_i,
vme_i.lword_n => VME_LWORD_n_b,
vme_i.addr => VME_ADDR_b,
vme_i.data => VME_DATA_b,
vme_i.iack_n => VME_IACK_n_i,
vme_i.iackin_n => VME_IACKIN_n_i,
vme_o.berr_n => VME_BERR_n,
vme_o.dtack_n => VME_DTACK_n_o,
vme_o.retry_n => VME_RETRY_n_o,
vme_o.retry_oe => VME_RETRY_OE_o,
vme_o.lword_n => VME_LWORD_n_b_out,
vme_o.data => VME_DATA_b_out,
vme_o.addr => VME_ADDR_b_out,
vme_o.irq_n => VME_IRQ_n,
vme_o.iackout_n => VME_IACKOUT_n_o,
vme_o.dtack_oe => VME_DTACK_OE_o,
vme_o.data_dir => VME_DATA_DIR_int,
vme_o.data_oe_n => VME_DATA_OE_N_o,
vme_o.addr_dir => VME_ADDR_DIR_int,
vme_o.addr_oe_n => VME_ADDR_OE_N_o,
wb_o => cnx_slave_in(c_MASTER_VME),
wb_i => cnx_slave_out(c_MASTER_VME),
int_i => vic_master_irq);
VME_DATA_b <= VME_DATA_b_out when VME_DATA_DIR_int = '1' else (others => 'Z');
VME_ADDR_b <= VME_ADDR_b_out when VME_ADDR_DIR_int = '1' else (others => 'Z');
......@@ -623,6 +633,10 @@ begin
VME_ADDR_DIR_o <= VME_ADDR_DIR_int;
VME_DATA_DIR_o <= VME_DATA_DIR_int;
-- BERR and IRQ vme signals are inverted by the drivers. See SVEC schematics.
VME_BERR_o <= not VME_BERR_n;
VME_IRQ_n_o <= not VME_IRQ_n;
gen_with_wr : if( g_with_white_rabbit ) generate
-- Tristates for SFP EEPROM
......
......@@ -16,8 +16,8 @@ NET "vme_iack_n_i" LOC = N1;
NET "vme_ga_i[5]" LOC = M6;
NET "vme_dtack_oe_o" LOC = T1;
NET "vme_dtack_n_o" LOC = R5;
NET "vme_ds_n_i[1]" LOC = Y7;
NET "vme_ds_n_i[0]" LOC = Y6;
NET "vme_ds_n_i[1]" LOC = Y6;
NET "vme_ds_n_i[0]" LOC = Y7;
NET "vme_data_oe_n_o" LOC = P1;
NET "vme_data_dir_o" LOC = P2;
NET "vme_berr_o" LOC = R3;
......
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