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Mock Turtle
Commit 03248832 authored by Federico Vaga's avatar Federico Vaga
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sw:py minor fixes and improvements for future tests

parents 97889b72 9550372a
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Showing with 1798 additions and 514 deletions
general-cores @ b47b0b1b
Subproject commit ea7614397a6d650dc56ec4411c46f138f5980cf4
Subproject commit b47b0b1b9b883658edebea986cf347311d158447
urv-core @ 134759b2
Subproject commit 075d7b1c664269a51a284c525d5bdcf3588aa4ee
Subproject commit 134759b20e8fa5241d3a3424393c6fbdfb66c6df
hdl/rtl/Manifest.py
View file @ 03248832
......@@ -2,6 +2,7 @@ files = [
"mock_turtle_core.vhd",
"mock_turtle_pkg.vhd",
"mt_wb_remapper.vhd",
"mt_config_rom.vhd",
]
modules = {
......
hdl/rtl/cpu/Manifest.py
View file @ 03248832
......@@ -2,6 +2,7 @@ files = [
"mt_cpu_cb.vhd",
"mt_cpu_csr_wbgen2_pkg.vhd",
"mt_cpu_csr_wb.vhd",
"mt_per_cpu_csr_pkg.vhd",
"mt_cpu_iram.vhd",
"mt_cpu_lr_wbgen2_pkg.vhd",
"mt_cpu_lr_wb.vhd",
......
hdl/rtl/cpu/mt_cpu_cb.vhd
View file @ 03248832
......@@ -6,32 +6,32 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2014-04-01
-- Last update: 2018-03-14
-- Last update: 2018-03-16
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-- Description:
--
-- WR Node CPU Core block top level. Connects an LM32, dedicated peripheral,
-- WR Node CPU Core block top level. Connects CPU, dedicated peripheral,
-- program/data memory and control registers.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2014 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
......@@ -44,19 +44,20 @@ use work.wishbone_pkg.all;
use work.gencores_pkg.all;
use work.genram_pkg.all;
use work.mt_cpu_csr_wbgen2_pkg.all;
use work.mt_cpu_lr_wbgen2_pkg.all;
use work.mt_per_cpu_csr_pkg.all;
use work.mock_turtle_pkg.all;
use work.mt_private_pkg.all;
entity mt_cpu_cb is
generic (
g_cpu_id : integer;
g_iram_size : integer;
g_system_clock_freq : integer;
g_with_white_rabbit : boolean);
g_with_white_rabbit : boolean
);
port (
......@@ -74,8 +75,8 @@ entity mt_cpu_cb is
dp_master_i : in t_wishbone_master_in := cc_dummy_master_in;
dp_master_o : out t_wishbone_master_out;
cpu_csr_i : in t_mt_cpu_csr_out_registers;
cpu_csr_o : out t_mt_cpu_csr_in_registers := c_mt_cpu_csr_in_registers_init_value;
cpu_csr_i : in t_mt_per_cpu_csr_out;
cpu_csr_o : out t_mt_per_cpu_csr_in;
rmq_ready_i : in std_logic_vector(15 downto 0);
hmq_ready_i : in std_logic_vector(15 downto 0);
......@@ -115,22 +116,6 @@ architecture rtl of mt_cpu_cb is
regs_o : out t_mt_cpu_lr_out_registers);
end component;
component mt_urv_wrapper is
generic (
g_iram_size : integer;
g_cpu_id : integer);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
irq_i : in std_logic_vector(31 downto 0) := x"00000000";
dwb_o : out t_wishbone_master_out;
dwb_i : in t_wishbone_master_in;
pc_o : out std_logic_vector(c_mt_pc_bits-1 downto 0);
pc_valid_o : out std_logic;
cpu_csr_i : in t_mt_cpu_csr_out_registers;
cpu_csr_o : out t_mt_cpu_csr_in_registers);
end component mt_urv_wrapper;
constant c_local_wishbone_masters : integer := 3;
signal cnx_master_in : t_wishbone_master_in_array(c_local_wishbone_masters-1 downto 0);
......@@ -139,7 +124,7 @@ architecture rtl of mt_cpu_cb is
constant c_slave_lr : integer := 0;
constant c_slave_dp : integer := 1;
constant c_slave_si : integer := 2;
constant c_cnx_address : t_wishbone_address_array(2 downto 0) := (
c_slave_lr => x"00100000", -- local regs
c_slave_dp => x"00200000", -- dedicated peripheral port
......@@ -281,7 +266,7 @@ begin -- rtl
local_regs_in.stat_wr_time_ok_i <= '0';
local_regs_in.stat_wr_aux_clock_ok_i <= x"00";
end generate gen_without_wr_1;
p_delay_counter : process(clk_sys_i)
......@@ -297,13 +282,13 @@ begin -- rtl
end if;
local_regs_in.delay_cnt_i <= delay_cnt;
end if;
end if;
end process;
p_gpio : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
......@@ -325,8 +310,7 @@ begin -- rtl
end if;
end process;
U_TheCoreCPU : mt_urv_wrapper
U_TheCoreCPU : entity work.mt_urv_wrapper
generic map (
g_iram_size => g_iram_size,
g_cpu_id => g_cpu_id)
......@@ -427,5 +411,5 @@ begin -- rtl
local_regs_in.stat_core_id_i <= std_logic_vector(to_unsigned(g_cpu_id, 4));
end rtl;
hdl/rtl/cpu/mt_cpu_csr.wb
View file @ 03248832
......@@ -10,27 +10,27 @@
-- Created : 2014-04-01
-- Last update: 2014-11-26
-------------------------------------------------------------------------------
-- Description:
-- Description:
--
-- CPU Control/Status Registers block layout (wbgen2)
-------------------------------------------------------------------------------
--
-- Copyright (c) 2014 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
......@@ -43,10 +43,10 @@ peripheral {
reg {
name = "Application ID Register";
prefix = "APP_ID";
field {
name = "User application ID";
type = SLV;
size = 32;
access_bus = READ_ONLY;
......@@ -87,7 +87,7 @@ peripheral {
field {
name = "Address";
prefix = "ADDR";
prefix = "ADDR";
size = 20;
type = SLV;
access_bus = READ_WRITE;
......@@ -106,7 +106,7 @@ peripheral {
access_dev = READ_ONLY;
};
};
reg {
name = "Core Count Register";
prefix = "CORE_COUNT";
......@@ -209,6 +209,104 @@ access_dev = READ_ONLY;
};
};
};
reg {
name = "Debug CPU Status Register";
prefix = "DBG_CPU_STATUS";
field {
name = "Per CPU debug mode bit";
type = SLV;
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Debug CPU Force Register";
prefix = "DBG_CPU_FORCE";
field {
name = "CPU debug force";
size = 8;
type = SLV;
reset_value = 0xff;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Debug CPU instruction ready Register";
prefix = "DBG_CPU_INSN_READY";
field {
name = "CPU insn ready";
size = 8;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Debug CPU[0] Instruction Register";
prefix = "DBG_CPU0_INSN";
field {
name = "Instruction to be executed";
size = 32;
type = PASS_THROUGH;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "Debug CPU[1] Instruction Register";
prefix = "DBG_CPU1_INSN";
field {
name = "Instruction to be executed";
size = 32;
type = PASS_THROUGH;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
-- ...
reg {
name = "Debug MBX[0] Data Register";
prefix = "DBG_MBX0";
field {
name = "CPU0 mailbox data";
size = 32;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "Debug MBX[1] Data Register";
prefix = "DBG_MBX1";
field {
name = "CPU1 mailbox data";
size = 32;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
};
hdl/rtl/cpu/mt_cpu_csr_wb.vhd
View file @ 03248832
This diff is collapsed.
hdl/rtl/cpu/mt_cpu_csr_wbgen2_pkg.vhd
View file @ 03248832
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : mt_cpu_csr_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from mt_cpu_csr.wb
-- Created : Wed Mar 14 14:00:34 2018
-- Created : Mon Mar 19 10:25:02 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mt_cpu_csr.wb
......@@ -26,6 +26,10 @@ package mt_cpu_csr_wbgen2_pkg is
udata_i : std_logic_vector(31 downto 0);
dbg_msg_data_i : std_logic_vector(7 downto 0);
dbg_poll_ready_i : std_logic_vector(7 downto 0);
dbg_cpu_status_i : std_logic_vector(7 downto 0);
dbg_cpu_insn_ready_i : std_logic_vector(7 downto 0);
dbg_mbx0_i : std_logic_vector(31 downto 0);
dbg_mbx1_i : std_logic_vector(31 downto 0);
end record;
constant c_mt_cpu_csr_in_registers_init_value: t_mt_cpu_csr_in_registers := (
......@@ -34,7 +38,11 @@ package mt_cpu_csr_wbgen2_pkg is
core_memsize_i => (others => '0'),
udata_i => (others => '0'),
dbg_msg_data_i => (others => '0'),
dbg_poll_ready_i => (others => '0')
dbg_poll_ready_i => (others => '0'),
dbg_cpu_status_i => (others => '0'),
dbg_cpu_insn_ready_i => (others => '0'),
dbg_mbx0_i => (others => '0'),
dbg_mbx1_i => (others => '0')
);
-- Output registers (WB slave -> user design)
......@@ -48,6 +56,15 @@ package mt_cpu_csr_wbgen2_pkg is
udata_load_o : std_logic;
dbg_imsk_enable_o : std_logic_vector(7 downto 0);
smem_op_o : std_logic_vector(2 downto 0);
dbg_cpu_force_o : std_logic_vector(7 downto 0);
dbg_cpu0_insn_o : std_logic_vector(31 downto 0);
dbg_cpu0_insn_wr_o : std_logic;
dbg_cpu1_insn_o : std_logic_vector(31 downto 0);
dbg_cpu1_insn_wr_o : std_logic;
dbg_mbx0_o : std_logic_vector(31 downto 0);
dbg_mbx0_load_o : std_logic;
dbg_mbx1_o : std_logic_vector(31 downto 0);
dbg_mbx1_load_o : std_logic;
end record;
constant c_mt_cpu_csr_out_registers_init_value: t_mt_cpu_csr_out_registers := (
......@@ -58,7 +75,16 @@ package mt_cpu_csr_wbgen2_pkg is
udata_o => (others => '0'),
udata_load_o => '0',
dbg_imsk_enable_o => (others => '0'),
smem_op_o => (others => '0')
smem_op_o => (others => '0'),
dbg_cpu_force_o => (others => '0'),
dbg_cpu0_insn_o => (others => '0'),
dbg_cpu0_insn_wr_o => '0',
dbg_cpu1_insn_o => (others => '0'),
dbg_cpu1_insn_wr_o => '0',
dbg_mbx0_o => (others => '0'),
dbg_mbx0_load_o => '0',
dbg_mbx1_o => (others => '0'),
dbg_mbx1_load_o => '0'
);
function "or" (left, right: t_mt_cpu_csr_in_registers) return t_mt_cpu_csr_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
......@@ -78,10 +104,10 @@ function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if x(i) = '1' then
tmp(i):= '1';
else
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
......@@ -95,6 +121,10 @@ tmp.core_memsize_i := f_x_to_zero(left.core_memsize_i) or f_x_to_zero(right.core
tmp.udata_i := f_x_to_zero(left.udata_i) or f_x_to_zero(right.udata_i);
tmp.dbg_msg_data_i := f_x_to_zero(left.dbg_msg_data_i) or f_x_to_zero(right.dbg_msg_data_i);
tmp.dbg_poll_ready_i := f_x_to_zero(left.dbg_poll_ready_i) or f_x_to_zero(right.dbg_poll_ready_i);
tmp.dbg_cpu_status_i := f_x_to_zero(left.dbg_cpu_status_i) or f_x_to_zero(right.dbg_cpu_status_i);
tmp.dbg_cpu_insn_ready_i := f_x_to_zero(left.dbg_cpu_insn_ready_i) or f_x_to_zero(right.dbg_cpu_insn_ready_i);
tmp.dbg_mbx0_i := f_x_to_zero(left.dbg_mbx0_i) or f_x_to_zero(right.dbg_mbx0_i);
tmp.dbg_mbx1_i := f_x_to_zero(left.dbg_mbx1_i) or f_x_to_zero(right.dbg_mbx1_i);
return tmp;
end function;
end package body;
hdl/rtl/cpu/mt_cpu_lr_wb.vhd
View file @ 03248832
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : mt_cpu_lr_wb.vhd
-- Author : auto-generated by wbgen2 from mt_cpu_lr.wb
-- Created : Mon Feb 26 11:11:22 2018
-- Created : Mon Mar 19 10:25:02 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mt_cpu_lr.wb
......@@ -41,12 +41,22 @@ architecture syn of mt_cpu_lr_wb_slave is
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(3 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
......
hdl/rtl/cpu/mt_cpu_lr_wbgen2_pkg.vhd
View file @ 03248832
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : mt_cpu_lr_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from mt_cpu_lr.wb
-- Created : Mon Feb 26 11:11:22 2018
-- Created : Mon Mar 19 10:25:02 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mt_cpu_lr.wb
......
hdl/rtl/cpu/mt_per_cpu_csr_pkg.vhd 0 → 100644
View file @ 03248832
-------------------------------------------------------------------------------
-- Title : Mock Turtle Core
-- Project : Mock Turtle
-------------------------------------------------------------------------------
-- Company : CERN BE-CO-HT
-------------------------------------------------------------------------------
-- Description:
--
-- Per CPU CSR ports, not to be confused with the wbgen generated file that
-- describe the whole CSR interface.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2018 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package mt_per_cpu_csr_pkg is
-- Per CPU CSR inputs (from urv to mt)
type t_mt_per_cpu_csr_in is record
udata_i : std_logic_vector(31 downto 0);
dbg_cpu_status_i : std_logic;
dbg_insn_ready_i : std_logic;
dbg_mbx_i : std_logic_vector(31 downto 0);
end record;
-- Per CPU CSR outputs (from mt to urv)
type t_mt_per_cpu_csr_out is record
reset_o : std_logic;
enable_o : std_logic;
uaddr_addr_o : std_logic_vector(19 downto 0);
core_sel_o : std_logic;
udata_o : std_logic_vector(31 downto 0);
udata_load_o : std_logic;
dbg_cpu_force_o : std_logic;
dbg_insn_o : std_logic_vector(31 downto 0);
dbg_insn_wr_o : std_logic;
dbg_mbx_o : std_logic_vector(31 downto 0);
dbg_mbx_wr_o : std_logic;
end record;
end package;
hdl/rtl/cpu/mt_tpu_csr_wb.vhd
View file @ 03248832
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : mt_tpu_csr_wb.vhd
-- Author : auto-generated by wbgen2 from mt_tpu_csr.wb
-- Created : Mon Feb 26 11:11:23 2018
-- Created : Mon Mar 19 10:25:02 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mt_tpu_csr.wb
......@@ -45,12 +45,22 @@ signal tpu_buf_addr_int : std_logic_vector(15 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(2 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
......
hdl/rtl/cpu/mt_tpu_csr_wbgen2_pkg.vhd
View file @ 03248832
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : mt_tpu_csr_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from mt_tpu_csr.wb
-- Created : Mon Feb 26 11:11:23 2018
-- Created : Mon Mar 19 10:25:02 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mt_tpu_csr.wb
......
hdl/rtl/cpu/mt_urv_wrapper.vhd
View file @ 03248832
......@@ -6,11 +6,11 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2014-04-01
-- Last update: 2018-03-14
-- Last update: 2018-03-19
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-- Description:
--
-- A small wrapper for the URV encompassing the internal RAM and
-- access to the RAM through CPU CSR register block.
......@@ -18,20 +18,20 @@
--
-- Copyright (c) 2014-2015 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
......@@ -42,7 +42,7 @@ use ieee.numeric_std.all;
use work.genram_pkg.all;
use work.wishbone_pkg.all;
use work.mt_cpu_csr_wbgen2_pkg.all;
use work.mt_per_cpu_csr_pkg.all;
use work.mt_private_pkg.all;
entity mt_urv_wrapper is
......@@ -60,63 +60,13 @@ entity mt_urv_wrapper is
pc_o: out std_logic_vector(c_mt_pc_bits-1 downto 0);
pc_valid_o : out std_logic;
cpu_csr_i : in t_mt_cpu_csr_out_registers;
cpu_csr_o : out t_mt_cpu_csr_in_registers
cpu_csr_i : in t_mt_per_cpu_csr_out;
cpu_csr_o : out t_mt_per_cpu_csr_in
);
end mt_urv_wrapper;
architecture wrapper of mt_urv_wrapper is
component urv_cpu is
port(
clk_i : in std_logic;
rst_i : in std_logic;
irq_i : in std_logic;
im_addr_o : out std_logic_vector(31 downto 0);
im_data_i : in std_logic_vector(31 downto 0);
im_valid_i : in std_logic;
dm_addr_o : out std_logic_vector(31 downto 0);
dm_data_s_o : out std_logic_vector(31 downto 0);
dm_data_l_i : in std_logic_vector(31 downto 0);
dm_data_select_o : out std_logic_vector(3 downto 0);
dm_ready_i : in std_logic;
dm_store_o : out std_logic;
dm_load_o : out std_logic;
dm_load_done_i : in std_logic;
dm_store_done_i : in std_logic
-- trace_pc_o : out std_logic_vector(31 downto 0);
-- trace_pc_valid_o : out std_logic
);
end component;
component urv_iram
generic (
g_size : integer;
g_init_file : string;
g_simulation : boolean
);
port (
clk_i : in std_logic;
ena_i : in std_logic;
wea_i : in std_logic;
aa_i : in std_logic_vector(31 downto 0);
bwea_i : in std_logic_vector(3 downto 0);
da_i : in std_logic_vector(31 downto 0);
qa_o : out std_logic_vector(31 downto 0);
enb_i : in std_logic;
web_i : in std_logic;
ab_i : in std_logic_vector(31 downto 0);
bweb_i : in std_logic_vector(3 downto 0);
db_i : in std_logic_vector(31 downto 0);
qb_o : out std_logic_vector(31 downto 0)
);
end component;
function f_x_to_zero (x : std_logic_vector) return std_logic_vector is
variable tmp : std_logic_vector(x'length-1 downto 0);
begin
......@@ -137,19 +87,6 @@ architecture wrapper of mt_urv_wrapper is
begin
return x(7 downto 0) & x(15 downto 8) & x(23 downto 16) & x(31 downto 24);
end f_swap_endian_32;
-- reserved for simulation purposes. firmware name
-- will be passed through a generic
impure function f_pick_init_file return string is
begin
if g_cpu_id = 0 then
-- return "rt-tdc.ram";
return "none";
else
return "none";
end if;
end function;
signal cpu_rst : std_logic;
signal cpu_rst_n : std_logic;
......@@ -176,6 +113,9 @@ architecture wrapper of mt_urv_wrapper is
signal dm_wb_write, dm_select_wb : std_logic;
signal dm_data_write : std_logic;
constant c_insn_nop : std_logic_vector(31 downto 0) := x"0000_0013";
signal dbg_insn : std_logic_vector(31 downto 0);
signal trace_pc_valid : std_logic;
signal trace_pc : std_logic_vector(31 downto 0);
......@@ -187,12 +127,11 @@ begin
dwb_o <= dwb_out;
pc_o <= (others => '0');
pc_valid_o <= '0';
cpu_rst_n <= not cpu_rst;
U_cpu_core : urv_cpu
U_cpu_core : entity work.urv_cpu
port map (
clk_i => clk_sys_i,
rst_i => cpu_rst,
......@@ -208,18 +147,29 @@ begin
dm_store_o => dm_store,
dm_load_o => dm_load,
dm_load_done_i => dm_load_done,
dm_store_done_i => dm_store_done
dm_store_done_i => dm_store_done,
dbg_force_i => cpu_csr_i.dbg_cpu_force_o,
dbg_enabled_o => cpu_csr_o.dbg_cpu_status_i,
dbg_insn_i => dbg_insn,
dbg_insn_set_i => cpu_csr_i.dbg_insn_wr_o,
dbg_insn_ready_o => cpu_csr_o.dbg_insn_ready_i,
dbg_mbx_data_i => cpu_csr_i.dbg_mbx_o,
dbg_mbx_write_i => cpu_csr_i.dbg_mbx_wr_o,
dbg_mbx_data_o => cpu_csr_o.dbg_mbx_i
-- trace_pc_o => trace_pc,
-- trace_pc_valid_o => trace_pc_valid
);
);
dm_data_write <= not dm_is_wishbone and dm_store;
U_iram : urv_iram
U_iram : entity work.urv_iram
generic map (
g_size => g_iram_size,
g_init_file => "",
g_simulation => false)
g_simulation => 0)
port map (
clk_i => clk_sys_i,
......@@ -258,15 +208,15 @@ begin
ha_im_addr(31 downto 22) <= (others => '0');
cpu_csr_o.udata_i <= f_swap_endian_32(im_data);
else
else
cpu_csr_o.udata_i <= (others => '0');
end if;
end if;
end if;
end process;
dm_is_wishbone <= '1' when dm_addr(31 downto 20) /= x"000" else '0'; -- 1st MByte of the mem is
-- the IRAM
......@@ -276,12 +226,17 @@ begin
if rising_edge(clk_sys_i) then
if(rst_n_i = '0' or cpu_rst = '1') then
dwb_out.cyc <= '0';
dwb_out.stb <= '0';
dwb_out.adr <= (others => '0');
dwb_out.sel <= x"0";
dwb_out.we <= '0';
dwb_out.dat <= (others => '0');
dm_cycle_in_progress <= '0';
dm_load_done <= '0';
dm_store_done <= '0';
dm_select_wb <= '0';
else
if(dm_cycle_in_progress = '0') then -- access to internal memory
if(dm_is_wishbone = '0') then
if(dm_store = '1') then
......@@ -308,7 +263,6 @@ begin
dwb_out.dat <= dm_data_s;
dwb_out.sel <= dm_data_select;
dm_load_done <= '0';
dm_store_done <= '0';
dm_cycle_in_progress <= '1';
......@@ -343,12 +297,27 @@ begin
end if;
end if;
end process;
dm_data_write <= not dm_is_wishbone and dm_store;
dm_data_l <= dm_wb_rdata when dm_select_wb = '1' else dm_mem_rdata;
im_addr_muxed <= ha_im_addr when cpu_rst = '1' else im_addr;
dm_ready <= '1';
p_dbg_insn: process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
dbg_insn <= c_insn_nop;
else
if cpu_csr_i.dbg_insn_wr_o = '1' then
dbg_insn <= cpu_csr_i.dbg_insn_o;
else
dbg_insn <= c_insn_nop;
end if;
end if;
end if;
end process p_dbg_insn;
process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
......@@ -362,15 +331,6 @@ begin
end if;
end process;
core_sel_match <= '1' when unsigned(cpu_csr_i.core_sel_o) = g_cpu_id else '0';
cpu_rst <= not rst_n_i or cpu_csr_i.reset_o(g_cpu_id);
-- Assign unused cpu_csr_o outputs to reduce warnings. These values are ignored
-- at higher levels
cpu_csr_o.app_id_i <= (others => '0');
cpu_csr_o.core_count_i <= (others => '0');
cpu_csr_o.core_memsize_i <= (others => '0');
cpu_csr_o.dbg_msg_data_i <= (others => '0');
cpu_csr_o.dbg_poll_ready_i <= (others => '0');
core_sel_match <= cpu_csr_i.core_sel_o;
cpu_rst <= not rst_n_i or cpu_csr_i.reset_o;
end wrapper;
hdl/rtl/mock_turtle_core.vhd
View file @ 03248832
This diff is collapsed.
hdl/rtl/mqueue/mt_rmq_incoming_slot.vhd
View file @ 03248832
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2014-04-01
-- Last update: 2017-05-15
-- Last update: 2018-03-16
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -127,29 +127,6 @@ architecture rtl of mt_rmq_incoming_slot is
constant c_addr_dst_type2 : integer := 10;
constant c_addr_dst_type3 : integer := 11;
component chipscope_ila
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(31 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0));
end component;
component chipscope_icon
port (
CONTROL0 : inout std_logic_vector (35 downto 0));
end component;
signal CONTROL : std_logic_vector(35 downto 0);
signal CLK : std_logic;
signal TRIG0 : std_logic_vector(31 downto 0);
signal TRIG1 : std_logic_vector(31 downto 0);
signal TRIG2 : std_logic_vector(31 downto 0);
signal TRIG3 : std_logic_vector(31 downto 0);
signal config : t_rmq_incoming_slot_config;
signal match_type0, match_type1, match_type2, match_type3, match_dst_mac, match_dst_ip, match_udp, match_ethertype, match_dst_port, match_raw, match : std_logic;
......@@ -545,38 +522,5 @@ begin -- rtl
stat_o.full <= full;
stat_o.empty <= empty;
stat_o.count <= std_logic_vector(occupied);
gen_cc : if (g_id = 0) generate
chipscope_ila_1 : chipscope_ila
port map (
CONTROL => CONTROL,
CLK => clk_i,
TRIG0 => TRIG0,
TRIG1 => TRIG1,
TRIG2 => TRIG2,
TRIG3 => TRIG3);
trig0(0) <= snk_i.valid;
trig0(1) <= snk_i.last;
trig0(2) <= empty;
trig0(3) <= full;
trig0(4) <= outb_i.sel;
trig0(6) <= outb_i.we;
trig0(5) <= mem_we;
trig0(15 downto 12) <= std_logic_vector(to_unsigned(t_wr_state'pos(wr_state), 4));
trig0(11 downto 8) <= std_logic_vector(to_unsigned(t_rd_state'pos(rd_state), 4));
trig0(31 downto 16) <= snk_i.data(15 downto 0);
trig1(9 downto 0) <= outb_i.adr;
trig2 <= outb_out.dat;
chipscope_icon_1 : chipscope_icon
port map (
CONTROL0 => CONTROL);
end generate gen_cc;
end rtl;
hdl/rtl/mqueue/mt_rmq_tx_path.vhd
View file @ 03248832
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2014-04-01
-- Last update: 2018-02-26
-- Last update: 2018-03-16
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -76,28 +76,6 @@ architecture rtl of mt_rmq_tx_path is
signal fwd_pipe : t_mt_stream_source_out_array(0 to 2);
signal rev_pipe : t_mt_stream_source_in_array(0 to 2);
component chipscope_ila
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(31 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0));
end component;
component chipscope_icon
port (
CONTROL0 : inout std_logic_vector (35 downto 0));
end component;
signal CONTROL : std_logic_vector(35 downto 0);
signal CLK : std_logic;
signal TRIG0 : std_logic_vector(31 downto 0);
signal TRIG1 : std_logic_vector(31 downto 0);
signal TRIG2 : std_logic_vector(31 downto 0);
signal TRIG3 : std_logic_vector(31 downto 0);
signal p_payload_len : std_logic_vector(15 downto 0);
component mt_rmq_tx_packer is
......@@ -178,26 +156,6 @@ p_payload_len <= std_logic_vector(unsigned(p_payload_words_i) sll 1);
p_dst_mac_i => p_dst_mac_i,
p_ethertype_i => p_ethertype_i);
chipscope_ila_1 : chipscope_ila
port map (
CONTROL => CONTROL,
CLK => clk_i,
TRIG0 => TRIG0,
TRIG1 => TRIG1,
TRIG2 => TRIG2,
TRIG3 => TRIG3);
chipscope_icon_1 : chipscope_icon
port map (
CONTROL0 => CONTROL);
trig0(0) <= fwd_pipe(2).valid;
trig0(1) <= fwd_pipe(2).last;
trig0(17 downto 2) <= fwd_pipe(2).data(15 downto 0);
trig0(19 downto 18) <= fwd_pipe(2).tag(1 downto 0);
trig0(20) <= rev_pipe(2).ready;
src_o <= fwd_pipe(2);
rev_pipe(2) <= src_i;
......
hdl/rtl/mt_config_rom.vhd
View file @ 03248832
--------------------------------------------------------------------------------
-- CERN BE-CO-HT
-- Mock Turtle
-- https://gitlab.cern.ch/coht/mockturtle
--------------------------------------------------------------------------------
--
-- unit name: mt_config_rom
--
-- description: A ROM to hold the various configuration values of the current
-- MockTurtle implementation.
--
--------------------------------------------------------------------------------
-- Copyright (c) 2018 CERN
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wr_node_pkg.all;
use work.wrn_mqueue_pkg.all;
use work.mock_turtle_pkg.all;
use work.mt_mqueue_pkg.all;
use work.wishbone_pkg.all;
entity mt_config_rom is
generic(
-- Message Queue and CPU configuration
g_config : t_wr_node_config := c_default_node_config;
-- When true, the CPUs can run with 2x the system clock. User design must
-- supply the clk_cpu_i signal which is in phase with the clk_i signal.
g_double_core_clock : boolean := false;
-- When true, the Remote Message Queue is implemented.
g_with_rmq : boolean := true;
-- Frequency of clk_sys_i, in Hz
g_system_clock_freq : integer := 62500000;
-- Enables/disables WR support
g_with_white_rabbit : boolean := false;
-- Choice of the CPU core used: LM32 or URV
g_cpu_arch : string := "LM32"
);
g_config : t_mock_turtle_config := c_default_mock_turtle_config;
-- When true, the Remote Message Queue is implemented.
g_with_rmq : boolean := TRUE;
-- Frequency of clk_sys_i, in Hz
g_system_clock_freq : integer := 62500000;
-- Enables/disables WR support
g_with_white_rabbit : boolean := FALSE);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
slave1_i : in t_wishbone_slave_in;
slave2_i : in t_wishbone_slave_in;
clk_i : in std_logic;
rst_n_i : in std_logic;
slave1_i : in t_wishbone_slave_in;
slave1_o : out t_wishbone_slave_out;
slave2_o : out t_wishbone_slave_out
);
slave2_i : in t_wishbone_slave_in;
slave2_o : out t_wishbone_slave_out);
end entity;
architecture rtl of mt_config_rom is
constant c_rom_size : integer := 256;
constant c_rom_size : integer := 256;
type t_rom_array is array(0 to c_rom_size-1) of std_logic_vector(31 downto 0);
constant c_mt_revision : integer := 20161208;
......@@ -63,7 +82,7 @@ architecture rtl of mt_config_rom is
procedure f_make_mq_config (
cfg : out t_rom_array;
offset : integer;
mq : t_wrn_mqueue_config
mq : t_mt_mqueue_config
) is
begin
cfg(offset) := f_int_to_slv(mq.in_slot_count);
......@@ -76,32 +95,30 @@ architecture rtl of mt_config_rom is
cfg(offset + 32 + 2 * i + 2) := f_int_to_slv(mq.out_slot_config(i).width);
cfg(offset + 32 + 2 * i + 2 + 1) := f_int_to_slv(mq.out_slot_config(i).entries);
end loop;
end f_make_mq_config;
impure function f_initialize_rom return t_rom_array is
function f_initialize_rom return t_rom_array is
variable cfg : t_rom_array;
begin
cfg(0) := f_char_to_slv('T') & f_char_to_slv('R') & f_char_to_slv('T') & f_char_to_slv('L');
cfg(1) := f_int_to_slv(c_mt_revision);
if g_cpu_arch = "LM32" then
cfg(2) := x"00000001";
else
cfg(2) := x"00000002";
end if;
--init to zero
cfg := (others => (others => '0'));
cfg(0) := f_char_to_slv('T') & f_char_to_slv('R') & f_char_to_slv('T') & f_char_to_slv('L');
cfg(1) := f_int_to_slv(c_mt_revision);
cfg(3) := f_int_to_slv(g_system_clock_freq);
cfg(4)(0) := f_bool_to_sl(g_with_white_rabbit);
cfg(4)(1) := f_bool_to_sl(g_with_rmq);
cfg(4)(2) := f_bool_to_sl(g_double_core_clock);
cfg(5) := g_config.app_id;
cfg(6) := f_int_to_slv(g_config.cpu_count);
cfg(7) := f_int_to_slv(g_config.shared_mem_size);
for i in 0 to 7 loop
if (i < g_config.cpu_count) then
cfg(i) := f_int_to_slv(g_config.cpu_memsizes(i));
cfg(8+i) := f_int_to_slv(g_config.cpu_memsizes(i));
else
cfg(i) := (others => '0');
cfg(8+i) := (others => '0');
end if;
end loop;
......@@ -110,11 +127,40 @@ architecture rtl of mt_config_rom is
f_make_mq_config(cfg, 64 + 64 + 2, g_config.rmq_config);
return cfg;
end f_initialize_rom;
constant c_rom_data : t_rom_array := f_initialize_rom;
signal wb1_ack, wb2_ack : std_logic := '0';
begin
p_ack : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb1_ack <= '0';
wb2_ack <= '0';
else
wb1_ack <= slave1_i.cyc and slave1_i.stb;
wb2_ack <= slave2_i.cyc and slave2_i.stb;
end if;
end if;
end process p_ack;
slave1_o.ack <= wb1_ack;
slave1_o.dat <= c_rom_data(to_integer(unsigned(slave1_i.adr(9 downto 2))));
slave1_o.stall <= '0';
slave1_o.err <= '0';
slave1_o.rty <= '0';
slave1_o.int <= '0';
slave2_o.ack <= wb2_ack;
slave2_o.dat <= c_rom_data(to_integer(unsigned(slave2_i.adr(9 downto 2))));
slave2_o.stall <= '0';
slave2_o.err <= '0';
slave2_o.rty <= '0';
slave2_o.int <= '0';
end rtl;
hdl/testbench/debug/Manifest.py 0 → 100644
View file @ 03248832
# HDLMake 'develop' branch required.
#
# Due to bugs in release v3.0 of hdlmake it is necessary to use the "develop"
# branch of hdlmake, commit db4e1ab.
sim_tool = "modelsim"
sim_top = "main"
action = "simulation"
target = "xilinx"
syn_device = "xc6slx150t"
vcom_opt = "-93 -mixedsvvh"
include_dirs = [
"../include",
"../../ip_cores/general-cores/sim/",
"../../ip_cores/urv-core/rtl/",
]
files = [
"main.sv",
]
modules = {
"local" : [
"../../rtl",
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/wr-cores.git",
"git://ohwr.org/hdl-core-lib/urv-core.git",
],
}
fetchto = "../../ip_cores"
hdl/testbench/debug/main.sv 0 → 100644
View file @ 03248832
import wishbone_pkg::*;
`include "vhd_wishbone_master.svh"
`include "mt_mqueue_host_driver.svh"
`include "mock_turtle_driver.svh"
`timescale 1ns/1ps
module main;
reg rst_n = 0;
reg clk_sys = 0;
reg clk_cpu = 0;
always #4ns clk_cpu <= ~clk_cpu;
always@(posedge clk_cpu)
clk_sys <= ~clk_sys;
initial begin
repeat(20) @(posedge clk_sys);
rst_n = 1;
end
wire host_irq;
IVHDWishboneMaster Host ( clk_sys, rst_n );
mock_turtle_core #
(
.g_double_core_clock(1'b0),
//.g_cpu_arch("LM32")
.g_cpu_arch("URV")
)
DUT (
.clk_i (clk_sys),
.rst_n_i (rst_n),
.host_slave_i (Host.master.out),
.host_slave_o (Host.master.in),
.host_irq_o(host_irq)
);
initial begin
MQueueHost hmq;
MTCPUControl cpu_csr;
uint64_t rv;
CBusAccessor host_acc;
uint32_t v;
#10us;
host_acc = Host.get_accessor();
cpu_csr = new ( Host.get_accessor(), 'hc000 );
hmq = new ( Host.get_accessor(), 0 );
// enable all IRQs
host_acc.write(`MQUEUE_GCR_IRQ_MASK, 'hffff);
cpu_csr.init();
// enable debug message interrupts for CPU0
cpu_csr.debug_int_enable(0, 1);
// clear reset
cpu_csr.writel('h4, 0);
// clear force
cpu_csr.writel('h34, 0);
cpu_csr.readl('h30, v);
$display("CPU status: %x", v);
cpu_csr.writel('h3c, 'h001005b7); // la t1, 0x10001c
cpu_csr.writel('h3c, 'h01c5e593);
cpu_csr.writel('h3c, 'h06800513); // li t0, 'h'
cpu_csr.writel('h3c, 'h00a58023); // sb t0, 0(t1)
cpu_csr.writel('h3c, 'h7d459073); // csrrw zero, 0x7d4, t1
cpu_csr.writel('h3c, 'h06300513); // li t0, 0x63 (bra 0)
cpu_csr.writel('h3c, 'h00502023); // sw t0, 0(zero)
while (1) begin
cpu_csr.readl('h38, v);
if ((v & 1) == 1'b1)
break;
end
//cpu_csr.load_firmware (0, "../sw/hw-tests/hello/hello.ram.lm32");
//cpu_csr.load_firmware (0, "../sw/hw-tests/hello/hello.ram.urv");
//cpu_csr.reset_core(0, 0);
$display("CPU0 started\n");
cpu_csr.readl('h44, v);
$display("mbx data: %x", v);
cpu_csr.writel('h44, 32'h12345678);
cpu_csr.readl('h44, v);
$display("mbx data: %x", v);
cpu_csr.writel('h3c, 'h00100073); // ebreak
forever begin
cpu_csr.update();
while(host_irq)
hmq.update();
#1us;
@(posedge clk_sys);
end
end // initial begin
endmodule
hdl/testbench/debug/run.do 0 → 100644
View file @ 03248832
vsim -L unisim work.main -novopt
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
do wave.do
radix -hexadecimal
run 1000us
\ No newline at end of file
hdl/testbench/debug/wave.do 0 → 100644
View file @ 03248832
This diff is collapsed.
hdl/testbench/include/mock_turtle_driver.svh
View file @ 03248832
//------------------------------------------------------------------------------
// CERN BE-CO-HT
// Mock Turtle
// https://gitlab.cern.ch/coht/mockturtle
//------------------------------------------------------------------------------
//
// unit name: MockTurtleDriver
//
// description: A SystemVerilog Class to provide an abstraction of the complete
// MockTurtle core.
//
//------------------------------------------------------------------------------
// Copyright (c) 2018 CERN
//------------------------------------------------------------------------------
// GNU LESSER GENERAL PUBLIC LICENSE
//------------------------------------------------------------------------------
// This source file is free software; you can redistribute it and/or modify it
// under the terms of the GNU Lesser General Public License as published by the
// Free Software Foundation; either version 2.1 of the License, or (at your
// option) any later version. This source is distributed in the hope that it
// will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
// of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU Lesser General Public License for more details. You should have
// received a copy of the GNU Lesser General Public License along with this
// source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
//------------------------------------------------------------------------------
`ifndef __MOCK_TURTLE_DRIVER_INCLUDED
`define __MOCK_TURTLE_DRIVER_INCLUDED
`include "simdrv_defs.svh"
`include "mt_cpu_csr_driver.svh"
`include "mt_mqueue_host_driver.svh"
`include "mt_config_rom_driver.svh"
class MockTurtleDriver;
protected CBusAccessor m_acc;
protected uint64_t m_base;
protected MTCPUControl m_cpu_csr;
protected MTCPUControl m_csr;
protected MQueueHost m_hmq;
protected MTConfigRom m_rom;
function automatic MTCPUControl CPUs();
return m_cpu_csr;
endfunction // CPUs
function automatic MQueueHost HMQ();
return m_hmq;
endfunction // CPUs
function new ( CBusAccessor acc, uint64_t base );
m_acc = acc;
m_base = base;
endfunction // new
task automatic init();
m_cpu_csr = new ( m_acc, m_base + 'hc000 );
task init();
m_csr = new ( m_acc, m_base + 'hc000 );
m_hmq = new ( m_acc, m_base + 'h0000 );
m_cpu_csr.init();
m_rom = new (m_acc, m_base + 'he000, 256 );
m_csr.init();
m_hmq.init();
m_rom.init();
endtask // init
task load_firmware ( int core, string filename );
m_csr.load_firmware ( core, filename );
endtask // load_firmware
task reset_core ( int core, int reset );
m_csr.reset_core ( core, reset );
endtask // reset_core
task cfg_rom_display();
m_rom.pretty_print();
endtask // cfg_rom_display
// polls HMQ and Debug UART
task automatic update();
m_cpu_csr.update();
task update();
m_csr.update();
m_hmq.update();
endtask // update
......
hdl/testbench/include/mt_config_rom_driver.svh 0 → 100644
View file @ 03248832
//------------------------------------------------------------------------------
// CERN BE-CO-HT
// Mock Turtle
// https://gitlab.cern.ch/coht/mockturtle
//------------------------------------------------------------------------------
//
// unit name: MTConfigRom
//
// description: A ROM to hold the various configuration values of the current
// MockTurtle implementation.
//
//------------------------------------------------------------------------------
// Copyright (c) 2018 CERN
//------------------------------------------------------------------------------
// GNU LESSER GENERAL PUBLIC LICENSE
//------------------------------------------------------------------------------
// This source file is free software; you can redistribute it and/or modify it
// under the terms of the GNU Lesser General Public License as published by the
// Free Software Foundation; either version 2.1 of the License, or (at your
// option) any later version. This source is distributed in the hope that it
// will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
// of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU Lesser General Public License for more details. You should have
// received a copy of the GNU Lesser General Public License along with this
// source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
//------------------------------------------------------------------------------
`ifndef __MOCK_TURTLE_CONFIG_ROM_INCLUDED
`define __MOCK_TURTLE_CONFIG_ROM_INCLUDED
`include "simdrv_defs.svh"
class MTConfigRom;
protected CBusAccessor m_acc;
protected uint64_t m_base;
protected uint32_t m_size;
protected uint32_t m_data [];
function new ( CBusAccessor acc, uint64_t base, uint64_t size );
m_acc = acc;
m_base = base;
m_size = size;
m_data = new[m_size];
endfunction // new
task _readl ( uint32_t r, ref uint32_t v );
uint64_t tmp;
m_acc.read ( m_base + r, tmp );
v= tmp;
endtask // _readl
task init ( );
int i;
for ( i = 0; i < m_size; i+=4 )
begin
_readl ( i, m_data[i] );
end
endtask // init
function uint32_t read ( uint32_t pos );
return m_data[4 * pos];
endfunction // read
task pretty_print ( );
$display ( "Configuration ROM contents:" );
$display ( " Magic Value: %s", read(0) );
$display ( " MT revision: %0d", read(1) );
endtask // pretty_print
endclass // MockTurtleConfigRom
`endif // `ifndef __MOCK_TURTLE_CONFIG_ROM_DRIVER_INCLUDED
hdl/testbench/include/mt_cpu_csr_driver.svh
View file @ 03248832
`include "mt_cpu_csr_regs.vh"
`include "regs/mt_cpu_csr_regs.vh"
typedef class MTCPUDbgQueue;
......
hdl/testbench/svec_mt_demo-verification/main.sv
View file @ 03248832
......@@ -72,7 +72,6 @@ module main;
automatic CWishboneAccessor acc;
automatic MockTurtleDriver drv;
automatic MTCPUControl csr;
@(posedge DUT.rst_n_sys);
@(posedge DUT.clk_sys);
......@@ -81,11 +80,13 @@ module main;
acc.set_mode (PIPELINED);
drv = new(acc, 'h20000);
drv.init();
csr = drv.CPUs();
csr.load_firmware(0, "../sw/hello/hello.ram.urv");
csr.reset_core(0, 0);
drv.cfg_rom_display();
drv.load_firmware(0, "../sw/hello/hello.ram.urv");
drv.reset_core(0, 0);
forever begin
drv.update();
......
hdl/top/svec_mt_demo/svec_mt_demo.vhd
View file @ 03248832
......@@ -173,6 +173,7 @@ architecture arch of svec_mt_demo is
signal cpu0_gpio_oen, cpu1_gpio_oen : std_logic_vector(23 downto 0);
signal cpu0_gpio_out, cpu1_gpio_out : std_logic_vector(23 downto 0);
signal cpu_gpio_oen : std_logic_vector(23 downto 0);
signal cpu_gpio_out, cpu_gpio_in : std_logic_vector(23 downto 0);
signal VME_DATA_b_out : std_logic_vector(31 downto 0);
......@@ -308,7 +309,7 @@ begin -- architecture arch
-- synthesis translate_off
cnx_slave_in(c_MASTER_VME) <= sim_wb_i;
sim_wb_o <= cnx_slave_out(c_MASTER_VME);
-- synthesis translate_on
-- synthesis translate_on
end generate gen_without_vme64_core;
U_Intercon : xwb_sdb_crossbar
......@@ -388,21 +389,18 @@ begin -- architecture arch
gpio_oen_o => cpu1_gpio_oen);
cpu_gpio_out <= cpu0_gpio_out or cpu1_gpio_out;
cpu_gpio_oen <= cpu0_gpio_oen or cpu1_gpio_oen;
-- FP GPIO directions
fp_gpio1_a2b_o <= cpu0_gpio_oen(0) or cpu1_gpio_oen(0);
fp_gpio2_a2b_o <= cpu0_gpio_oen(1) or cpu1_gpio_oen(1);
fp_gpio34_a2b_o <= cpu0_gpio_oen(2) or cpu1_gpio_oen(2);
fp_gpio1_a2b_o <= cpu_gpio_oen(0);
fp_gpio2_a2b_o <= cpu_gpio_oen(1);
fp_gpio34_a2b_o <= cpu_gpio_oen(2);
-- FP GPIO bidir in/out (3 and 4 share the same direction line)
fp_gpio1_b <= (cpu0_gpio_out(0) or cpu1_gpio_out(0))
when (cpu0_gpio_oen(0) = '1' or cpu1_gpio_oen(0) = '1') else 'Z';
fp_gpio2_b <= (cpu0_gpio_out(1) or cpu1_gpio_out(1))
when (cpu0_gpio_oen(1) = '1' or cpu1_gpio_oen(1) = '1') else 'Z';
fp_gpio3_b <= (cpu0_gpio_out(2) or cpu1_gpio_out(2))
when (cpu0_gpio_oen(2) = '1' or cpu1_gpio_oen(2) = '1') else 'Z';
fp_gpio4_b <= (cpu0_gpio_out(3) or cpu1_gpio_out(3))
when (cpu0_gpio_oen(2) = '1' or cpu1_gpio_oen(2) = '1') else 'Z';
fp_gpio1_b <= cpu_gpio_out(0) when cpu_gpio_oen(0) = '1' else 'Z';
fp_gpio2_b <= cpu_gpio_out(1) when cpu_gpio_oen(1) = '1' else 'Z';
fp_gpio3_b <= cpu_gpio_out(2) when cpu_gpio_oen(2) = '1' else 'Z';
fp_gpio4_b <= cpu_gpio_out(3) when cpu_gpio_oen(2) = '1' else 'Z';
-- gpio inputs (same for both CPUs)
cpu_gpio_in(0) <= fp_gpio1_b;
......@@ -410,7 +408,7 @@ begin -- architecture arch
cpu_gpio_in(2) <= fp_gpio3_b;
cpu_gpio_in(3) <= fp_gpio4_b;
cpu_gpio_in(23 downto 8) <= cpu_gpio_out(23 downto 8);
cpu_gpio_in(23 downto 4) <= cpu_gpio_out(23 downto 4);
U_LED_Controller : gc_bicolor_led_ctrl
generic map(
......
software/tools/mockturtle-debug.py 0 → 100644
View file @ 03248832
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