A more modular approach to HDLMake on OpenEmbedded

parent 822f6fd3
......@@ -9,34 +9,35 @@ PV = "0.1"
# Patch the top Manifest.py to adapt the old WR-NIC repo to the new HDLMake format.
SRC_URI = "git://ohwr.org/white-rabbit/wr-nic.git \
file://top-manifest.patch"
SRCREV = "3bf04881479303ae41ce3fd2f4df90cd22ea8991"
S = "${WORKDIR}/git"
HDLMAKE_TOP_FOLDER = "${S}/syn/specdio"
FILES_${PN} += "/lib/firmware/fmc"
# Update and init Git submodules to clone some dependent HDL libraries
do_fetch_extra(){
git submodule update --init
}
addtask fetch_extra after do_unpack before do_patch
# Use HDLMake to analyze the project and generate the Makefile
do_configure() {
cd ${HDLMAKE_TOP_FOLDER}
hdlmake
}
FILES_${PN} += "/lib/firmware/fmc"
# Get into the HDL synthesis folder and run HDLMake to analyze the design and generate the Makefile.
# Once the design is cloned, we can run make to build the FPGA bitstream.
# Synthesize the FPGA bitstream
do_compile() {
cd ${S}/syn/specdio/
hdlmake
cd ${HDLMAKE_TOP_FOLDER}
make
}
# Install the bitstream binary in the folder where the associated kernel module will search for it.
# Deploy the bitstream into the appropriated target folder
do_install() {
install -d ${D}/lib/firmware/fmc
install -m 0755 ${S}/syn/specdio/wr_nic_dio_top.bin ${D}/lib/firmware/fmc/wr_nic_dio.bin
install -d ${D}/lib/firmware/fmc
install -m 0755 ${S}/syn/specdio/wr_nic_dio_top.bin ${D}/lib/firmware/fmc/wr_nic_dio.bin
}
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