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MasterFIP - Testing
Commit fe9ccb82 authored by Marek Gumiński's avatar Marek Gumiński
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Renamed top module. 

Cleaned some scripts.
parent cd910088
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Showing with 13 additions and 28 deletions
gateware/syn/spec/spec_masterfip_mt.xise
View file @ fe9ccb82
......@@ -142,9 +142,9 @@
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore Version Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|spec_masterfip_pts2|rtl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../top/spec/spec_masterfip_pts2.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/spec_masterfip_pts2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|spec_masterfip_pts|rtl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../top/spec/spec_masterfip_pts.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/spec_masterfip_pts" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -1755,22 +1755,15 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="../../top/spec/spec_masterfip_pts.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="394"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../top/spec/spec_masterfip_pts.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../top/spec/carrier_csr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="396"/>
<association xil_pn:name="Implementation" xil_pn:seqID="175"/>
</file>
<file xil_pn:name="../../top/spec/spec_masterfip_pts2.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../top/spec/spec_masterfip_pts.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="433"/>
<association xil_pn:name="Implementation" xil_pn:seqID="180"/>
</file>
<file xil_pn:name="../../top/spec/spec_masterfip_pts2.ucf" xil_pn:type="FILE_UCF">
<file xil_pn:name="../../top/spec/spec_top_fmc_masterfip.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../rtl/masterfip_pts.vhd" xil_pn:type="FILE_VHDL">
......@@ -1791,8 +1784,7 @@
<bindings>
<binding xil_pn:location="/spec_masterfip_mt" xil_pn:name="../../ip_cores/gw-masterfip/top/spec/spec_masterfip_mt.ucf"/>
<binding xil_pn:location="/spec_masterfip_pts" xil_pn:name="../../top/spec/spec_masterfip_pts.ucf"/>
<binding xil_pn:location="/spec_masterfip_pts2" xil_pn:name="../../top/spec/spec_masterfip_pts2.ucf"/>
<binding xil_pn:location="/spec_masterfip_pts2" xil_pn:name="../../top/spec/spec_top_fmc_masterfip.ucf"/>
</bindings>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
......
gateware/top/spec/spec_masterfip_pts2.vhd → gateware/top/spec/spec_masterfip_pts.vhd
View file @ fe9ccb82
......@@ -7,10 +7,10 @@
---------------------------------------------------------------------------------------------------
-- |
-- spec_masterfip_pts2 |
-- spec_masterfip_pts |
-- |
---------------------------------------------------------------------------------------------------
-- File spec_masterfip_pts2.vhd |
-- File spec_masterfip_pts.vhd |
-- |
-- Description Top level of the masterFIP design with Mock Turtle on a SPEC carrier. |
-- |
......@@ -45,7 +45,7 @@
-- | | |___| | | |
-- | |_________________________________________| | |
-- |______________________________________________________________________| |
-- Figure 1: spec_masterfip_pts2 architecture |
-- Figure 1: spec_masterfip_pts architecture |
-- |
-- |
-- FMC MASTERFIP CORE: |
......@@ -154,7 +154,7 @@ use work.masterFIP_pkg.all; -- for the fmc_masterfip_core definition
use work.masterfip_wbgen2_pkg.all; -- for the masterfip_wbgen2_csr records
entity spec_masterfip_pts2 is
entity spec_masterfip_pts is
generic (g_simulation : boolean := false);
port
(-- Carrier signals
......@@ -252,13 +252,13 @@ entity spec_masterfip_pts2 is
adc_1v8_shdn_n_o : out std_logic;
adc_m5v_shdn_n_o : out std_logic;
adc_5v_en_n_o : out std_logic);
end spec_masterfip_pts2;
end spec_masterfip_pts;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of spec_masterfip_pts2 is
architecture rtl of spec_masterfip_pts is
---------------------------------------------------------------------------------------------------
-- MOCK TURTLE CONSTANTS --
......
pts/fmcmasterfip.sh
View file @ fe9ccb82
......@@ -84,8 +84,6 @@ sleep 1
insmod "${top}/${projectpath}/software/fmc-bus/kernel/fmc.ko"
insmod "${top}/${projectpath}/software/spec-sw/kernel/spec.ko" "fw_name=../../${top}/${projectpath}/gateware/spec-init.bin-2012-12-14"
# insmod "${top}/${projectpath}/software/zio/zio.ko"
# insmod "${top}/${projectpath}/software/fmc-adc-100m14b4cha-sw/kernel/fmc-adc-100m14b.ko" "gateware=../../${top}/${projectpath}/gateware/syn/spec/spec_top_fmc_masterfip.bin"
modprobe usbserial
insmod "${top}/${projectpath}/software/cp210x/cp210x.ko"
......@@ -131,10 +129,6 @@ nb_test_limit=2
nb_test=1
# leftovers from previous tests
rm -f "/tmp/mfdata_*"
#######################################################################
############################## Testing ###############################
#######################################################################
......
python/fmcmasterfip.py
View file @ fe9ccb82
......@@ -230,7 +230,6 @@ class fmcmasterfip:
util.info_msg("Speed : 0x%08X"%(self.fipcore.read_regname('speed')) )
def get_bus_freq(self):
print self.fipcore.read_regname('speed')
return self.freq_options[ self.fipcore.read_regname('speed') ]
......
python/utilities.py
View file @ fe9ccb82
......@@ -13,7 +13,7 @@ INFO = True
WARRNING = True
CRITICAL = True
FIRMWARE_PATH ='gateware/syn/spec/spec_masterfip_pts2.bin'
FIRMWARE_PATH ='gateware/syn/spec/spec_masterfip_pts.bin'
TOPDIRNAME ="fmcmasterfip"
test03_outputpath ='/tmp/'
......
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