Commit f256bd68 authored by Matthieu Cattin's avatar Matthieu Cattin

Add masterFIP proto access class and simple test with nanoFIP.

parents
#! /usr/bin/env python
# coding: utf8
# Copyright CERN, 2014
# Author: Matthieu Cattin (CERN)
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org
# Last modifications: 6/11/2014
# Import standard modules
import os
import sys
# Add common modules and libraries location to path
cdir = os.path.dirname(os.path.realpath(__file__))
sys.path.append(os.path.join(cdir,'../pts/'))
sys.path.append(os.path.join(cdir,'../pts/gnurabbit/python/'))
sys.path.append(os.path.join(cdir,'../pts/common/'))
# Import specific modules
from sdb import *
from csr import *
from gn4124 import *
# Import register maps
from fmc_masterfip_proto_regs import *
# Class to access MasterFip prototype core (simple register map to send receive variables)
class FmcMasterFipProtoOperationError(Exception):
def __init__(self, msg):
self.msg = msg
def __str__(self):
return ("FmcMasterFipProto: %s" %(self.msg))
class CFmcMasterFipProto:
REGS_ADDR = 0x11000
def __init__(self, bus, offset=0x40000):
self.bus = bus
self.mezz_offset = offset
try:
self.regs = CCSR(self.bus, self.mezz_offset + self.REGS_ADDR, FMC_MASTERFIP_PROTO_REGS)
except (CSRDeviceOperationError) as e:
raise FmcMasterFipProtoOperationError(e)
def set_core_config(self, ident_addr, cons_addr, nb_bourr):
self.regs.set_reg(IDENT_ID_DAT_SUB, ident_addr)
self.regs.set_reg(CONS_ID_DAT_SUB, cons_addr)
self.regs.set_field(CONFIG, NUM_OF_BOURR, nb_bourr)
def print_core_config(self):
self.regs.print_reg_map()
def continuous_loop_enable(self):
self.regs.set_field(CONFIG, CONT_LOOP, 1)
def continuous_loop_disable(self):
self.regs.set_field(CONFIG, CONT_LOOP, 0)
def start_loop(self):
self.regs.set_field(CTRL, ACTIV_LOOP, 1)
def stop_loop(self):
self.regs.set_field(CTRL, ACTIV_LOOP, 0)
# send 16-bit consumed RP_DAT
def send_cons_rp_dat(self, data):
self.regs.set_reg(CONSU_RP_DAT_BYTE0, (data & 0xFF))
self.regs.set_reg(CONSU_RP_DAT_BYTE1, ((data >> 8) & 0xFF))
def print_ident_rp_dat(self):
for i,addr in enumerate(range(0x10, 0x38, 0x4)):
print "Identification: byte %d: 0x%02X"%(i, self.regs.rd_reg(addr))
#! /usr/bin/env python
# coding: utf8
# Copyright CERN, 2014
# Author: Matthieu Cattin (CERN)
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org
# Last modifications: 6/11/2014
# fmc masterfip prototype registers
FMC_MASTERFIP_PROTO_REGS=['Fmc Masterfip Prototype registers', {
'IDENT_ID_DAT_VAR':[0x00, 'Indentification ID_DAT variable', {}],
'IDENT_ID_DAT_SUB':[0x04, 'Indentification ID_DAT subaddress', {}],
'CONSU_ID_DAT_VAR':[0x08, 'Consumed ID_DAT variable', {}],
'CONSU_ID_DAT_SUB':[0x0C, 'Consumed ID_DAT subaddress', {}],
'IDENT_RP_DAT_BYTE0':[0x10, 'Indentification RP_DAT byte 0', {}],
'IDENT_RP_DAT_BYTE1':[0x14, 'Indentification RP_DAT byte 1', {}],
'IDENT_RP_DAT_BYTE2':[0x18, 'Indentification RP_DAT byte 2', {}],
'IDENT_RP_DAT_BYTE3':[0x1C, 'Indentification RP_DAT byte 3', {}],
'IDENT_RP_DAT_BYTE4':[0x20, 'Indentification RP_DAT byte 4', {}],
'IDENT_RP_DAT_BYTE5':[0x24, 'Indentification RP_DAT byte 5', {}],
'IDENT_RP_DAT_BYTE6':[0x28, 'Indentification RP_DAT byte 6', {}],
'IDENT_RP_DAT_BYTE7':[0x2C, 'Indentification RP_DAT byte 7', {}],
'IDENT_RP_DAT_BYTE8':[0x30, 'Indentification RP_DAT byte 8', {}],
'IDENT_RP_DAT_BYTE0':[0x34, 'Indentification RP_DAT byte 9', {}],
'CONSU_RP_DAT_BYTE0':[0x38, 'Consumed RP_DAT byte 0', {}],
'CONSU_RP_DAT_BYTE1':[0x3C, 'Consumed RP_DAT byte 1', {}],
'CONFIG':[0x50, 'Configuration register', {
'NUM_OF_BOURR':[0, 'Number of bourrage', 0xFF],
'RESERVED':[8, 'Reserved', 0x3FFFFF],
'CONT_LOOP':[31, 'Continuous loop', 0x1]}],
'CTRL':[0x54, 'Control register', {
'ACTIV_LOOP':[0, 'Activate loop', 0x1],
'RESERVED':[3, 'Reserved', 0x7FFFFFFF]}]
}]
#! /usr/bin/env python
# coding: utf8
# Copyright CERN, 2014
# Author: Matthieu Cattin <matthieu.cattin@cern.ch>
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org
# Last modifications: 11/5/2014
# Import system modules
import sys
import time
import os
# Import specific modules
from fmc_masterfip_proto import *
# Import common modules
from ptsexcept import *
import rr
"""
"""
MASTERFIP_PROTO_PCIE_ADDR = '1a39:0004/1a39:0004@000B:0000'
MASTERFIP_PROTO_BITSTREAM = '../gatewares/spec_masterfip_proto.bin'
MASTERFIP_PROTO_BITSTREAM = os.path.join(default_directory, MASTERFIP_PROTO_BITSTREAM)
IDENT_VAR_ADDR = 0x3
CONSUM_VAR_ADDR = 0x3
NB_BOURRAGE = 0x4B
def main (default_directory='.'):
start_test_time = time.time()
print "================================================================================"
print "Test start\n"
# SPEC object declaration
print "Loading hardware access library and opening device.\n"
spec = rr.Gennum()
# Bind SPEC object to masterFip card
#for name, value in spec.parse_addr(MASTERFIP_PROTO_PCIE_ADDR).iteritems():
# print "%9s:0x%04X"%(name, value)
#spec.bind(MASTERFIP_PROTO_PCIE_ADDR)
# Load MasterFip Proto gateware
print "Loading gateware: %s\n" % MASTERFIP_PROTO_BITSTREAM
if(os.path.isfile(MASTERFIP_PROTO_BITSTREAM)):
spec.load_gateware(MASTERFIP_PROTO_BITSTREAM)
time.sleep(2)
else:
raise PtsCritical("Gateware file \"%s\" is missing, test stopped." % MASTERFIP_PROTO_BITSTREAM)
"""
# Carrier object declaration (SPEC board specific part)
try:
carrier = CFmcAdc100mSpec(spec)
except FmcAdc100mSpecOperationError as e:
raise PtsCritical("Carrier init failed, test stopped: %s" % e)
"""
# Mezzanine object declaration (FmcAdc100m14b4cha board specific part)
try:
fmc = CFmcMasterFipProto(spec)
except FmcMasterFipProtoOperationError as e:
raise PtsCritical("Mezzanine init failed, test stopped: %s" % e)
# Perform simple test (controls LEDs on nanoFIP test board)
try:
fmc.set_core_config(IDENT_VAR_ADDR, CONS_VAR_ADDR, NB_BOURRAGE)
#time.sleep(1)
fmc.print_core_config()
fmc.continuous_loop_enable()
print "\n\n ----> Start loop\n"
fmc.start_loop()
#time.sleep(1)
i = 0
while(1):
print "\nIteration %d\n"%i
data = 1
for d in range(8):
fmc.send_cons_rp_dat(data)
data = (data << 1) + 1
time.sleep(0.5)
data = 1
for d in range(8):
fmc.send_cons_rp_dat(data << 8)
data = (data << 1) + 1
time.sleep(0.5)
for d in range(2):
fmc.send_cons_rp_dat(0x0000)
time.sleep(0.3)
fmc.send_cons_rp_dat(0xFFFF)
time.sleep(0.3)
for d in range(2):
fmc.send_cons_rp_dat(0x0200)
time.sleep(0.3)
fmc.send_cons_rp_dat(0x0000)
time.sleep(0.3)
fmc.print_ident)rd_dat()
i++
except FmcMasterFipProtoOperationError as e:
raise PtsError("Test failed: %s" % e)
print ""
print "==> End of test"
print "================================================================================"
end_test_time = time.time()
print "Elapsed time: %.2f seconds\n" % (end_test_time-start_test_time)
if __name__ == '__main__' :
main()
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment