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MasterFIP - Testing
Commit cd910088 authored by Marek Gumiński's avatar Marek Gumiński
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removed unused sources

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#----------------------------------------
# BANK 0 P2V5: Clock
#----------------------------------------
NET "clk_125m_pllref_n_i" LOC = F10;
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_p_i" LOC = G9;
NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
#----------------------------------------
# BANK 1 P1V8: PCIe interface
#----------------------------------------
NET "l_rst_n_i" LOC = N20;
NET "l_rst_n_i" IOSTANDARD = "LVCMOS18";
NET "L2P_CLKN_o" LOC = K22;
NET "L2P_CLKN_o" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_CLKP_o" LOC = K21;
NET "L2P_CLKP_o" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_DFRAME_o" LOC = U22;
NET "L2P_DFRAME_o" IOSTANDARD = "SSTL18_I";
NET "L2P_EDB_o" LOC = U20;
NET "L2P_EDB_o" IOSTANDARD = "SSTL18_I";
NET "L2P_RDY_i" LOC = U19;
NET "L2P_RDY_i" IOSTANDARD = "SSTL18_I";
NET "L2P_VALID_o" LOC = T18;
NET "L2P_VALID_o" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY_i[0]" LOC = R20;
NET "L_WR_RDY_i[0]" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY_i[1]" LOC = T22;
NET "L_WR_RDY_i[1]" IOSTANDARD = "SSTL18_I";
NET "P2L_CLKN_i" LOC = M19;
NET "P2L_CLKN_i" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_CLKP_i" LOC = M20;
NET "P2L_CLKP_i" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_DFRAME_i" LOC = J22;
NET "P2L_DFRAME_i" IOSTANDARD = "SSTL18_I";
NET "P2L_RDY_o" LOC = J16;
NET "P2L_RDY_o" IOSTANDARD = "SSTL18_I";
NET "P2L_VALID_i" LOC = L19;
NET "P2L_VALID_i" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY_i[0]" LOC = N16;
NET "P_RD_D_RDY_i[0]" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY_i[1]" LOC = P19;
NET "P_RD_D_RDY_i[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY_o[0]" LOC = L15;
NET "P_WR_RDY_o[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY_o[1]" LOC = K16;
NET "P_WR_RDY_o[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ_i[0]" LOC = M22;
NET "P_WR_REQ_i[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ_i[1]" LOC = M21;
NET "P_WR_REQ_i[1]" IOSTANDARD = "SSTL18_I";
NET "RX_ERROR_o" LOC = J17;
NET "RX_ERROR_o" IOSTANDARD = "SSTL18_I";
NET "TX_ERROR_i" LOC = M17;
NET "TX_ERROR_i" IOSTANDARD = "SSTL18_I";
NET "VC_RDY_i[0]" LOC = B21;
NET "VC_RDY_i[0]" IOSTANDARD = "SSTL18_I";
NET "VC_RDY_i[1]" LOC = B22;
NET "VC_RDY_i[1]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[0]" LOC = P16;
NET "L2P_DATA_o[0]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[1]" LOC = P21;
NET "L2P_DATA_o[1]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[2]" LOC = P18;
NET "L2P_DATA_o[2]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[3]" LOC = T20;
NET "L2P_DATA_o[3]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[4]" LOC = V21;
NET "L2P_DATA_o[4]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[5]" LOC = V19;
NET "L2P_DATA_o[5]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[6]" LOC = W22;
NET "L2P_DATA_o[6]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[7]" LOC = Y22;
NET "L2P_DATA_o[7]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[8]" LOC = P22;
NET "L2P_DATA_o[8]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[9]" LOC = R22;
NET "L2P_DATA_o[9]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[10]" LOC = T21;
NET "L2P_DATA_o[10]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[11]" LOC = T19;
NET "L2P_DATA_o[11]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[12]" LOC = V22;
NET "L2P_DATA_o[12]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[13]" LOC = V20;
NET "L2P_DATA_o[13]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[14]" LOC = W20;
NET "L2P_DATA_o[14]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[15]" LOC = Y21;
NET "L2P_DATA_o[15]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[0]" LOC = K20;
NET "P2L_DATA_i[0]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[1]" LOC = H22;
NET "P2L_DATA_i[1]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[2]" LOC = H21;
NET "P2L_DATA_i[2]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[3]" LOC = L17;
NET "P2L_DATA_i[3]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[4]" LOC = K17;
NET "P2L_DATA_i[4]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[5]" LOC = G22;
NET "P2L_DATA_i[5]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[6]" LOC = G20;
NET "P2L_DATA_i[6]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[7]" LOC = K18;
NET "P2L_DATA_i[7]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[8]" LOC = K19;
NET "P2L_DATA_i[8]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[9]" LOC = H20;
NET "P2L_DATA_i[9]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[10]" LOC = J19;
NET "P2L_DATA_i[10]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[11]" LOC = E22;
NET "P2L_DATA_i[11]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[12]" LOC = E20;
NET "P2L_DATA_i[12]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[13]" LOC = F22;
NET "P2L_DATA_i[13]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[14]" LOC = F21;
NET "P2L_DATA_i[14]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[15]" LOC = H19;
NET "P2L_DATA_i[15]" IOSTANDARD = "SSTL18_I";
#----------------------------------------
# BANK 0 P2V5: SPEC LEDs
#----------------------------------------
NET "GPIO_b[1]" LOC = U16;
NET "GPIO_b[1]" IOSTANDARD = "LVCMOS25";
NET "GPIO_b[0]" LOC = AB19;
NET "GPIO_b[0]" IOSTANDARD = "LVCMOS25";
NET "LED_RED_O" LOC = D5;
NET "LED_RED_O" IOSTANDARD = "LVCMOS25";
NET "LED_GREEN_O" LOC = E5;
NET "LED_GREEN_O" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# BANK 0 P2V5: SPEC DAC
#----------------------------------------
NET "dac_cs_n_o[0]" LOC = A3;
NET "dac_cs_n_o[0]" IOSTANDARD = "LVCMOS25";
NET "dac_cs_n_o[1]" LOC = B3;
NET "dac_cs_n_o[1]" IOSTANDARD = "LVCMOS25";
NET "dac_sclk_o" LOC = A4;
NET "dac_sclk_o" IOSTANDARD = "LVCMOS25";
NET "dac_din_o" LOC = C4;
NET "dac_din_o" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# PCB version number (coded with resistors)
#----------------------------------------
NET "pcb_ver_i[0]" LOC = P5;
NET "pcb_ver_i[0]" IOSTANDARD = LVCMOS15;
NET "pcb_ver_i[1]" LOC = P4;
NET "pcb_ver_i[1]" IOSTANDARD = LVCMOS15;
NET "pcb_ver_i[2]" LOC = AA2;
NET "pcb_ver_i[2]" IOSTANDARD = LVCMOS15;
NET "pcb_ver_i[3]" LOC = AA1;
NET "pcb_ver_i[3]" IOSTANDARD = LVCMOS15;
#----------------------------------------
# Bank 2 P2V5: FMC
#----------------------------------------
NET "fmc_prsnt_m2c_n_i" LOC = AB14;
NET "fmc_prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
NET "fmc_onewire_b" LOC = "C18";
NET "fmc_onewire_b" IOSTANDARD = "LVCMOS25";
NET "fmc_scl_io" LOC = F7;
NET "fmc_sda_io" LOC = F8;
NET "fmc_scl_io" IOSTANDARD = LVCMOS25;
NET "fmc_sda_io" IOSTANDARD = LVCMOS25;
NET "fd_rstn_o" LOC = "Y18";
NET "fd_rstn_o" IOSTANDARD = "LVCMOS25";
NET "fd_txd_o" LOC = "T14";
NET "fd_txd_o" IOSTANDARD = "LVCMOS25";
NET "fd_txck_o" LOC = "W17";
NET "fd_txck_o" IOSTANDARD = "LVCMOS25";
NET "fd_txer_i" LOC = "T11";
NET "fd_txer_i" IOSTANDARD = "LVCMOS25";
NET "fd_rxcdn_i" LOC = "T15";
NET "fd_rxcdn_i" IOSTANDARD = "LVCMOS25";
NET "fd_rxd_i" LOC = "U15";
NET "fd_rxd_i" IOSTANDARD = "LVCMOS25";
NET "fd_wdgn_i" LOC = "R11";
NET "fd_wdgn_i" IOSTANDARD = "LVCMOS25";
NET "fd_txena_o" LOC = "R13";
NET "fd_txena_o" IOSTANDARD = "LVCMOS25";
NET "speed_b0_i" LOC = Y5;
NET "speed_b0_i" IOSTANDARD = "LVCMOS25";
NET "speed_b1_i" LOC = AB5;
NET "speed_b1_i" IOSTANDARD = "LVCMOS25";
NET "ext_sync_term_en_o" LOC = AB13;
NET "ext_sync_term_en_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_i" LOC = T8;
NET "ext_sync_i" IOSTANDARD = "LVCMOS25";
NET "ext_sync_oe_n_o" LOC = W6;
NET "ext_sync_oe_n_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_dir_o" LOC = Y6;
NET "ext_sync_dir_o" IOSTANDARD = "LVCMOS25";
NET "adc_1v8_shdn_n_o" LOC = V17;
NET "adc_1v8_shdn_n_o" IOSTANDARD = "LVCMOS25";
NET "adc_m5v_shdn_n_o" LOC = W18;
NET "adc_m5v_shdn_n_o" IOSTANDARD = "LVCMOS25";
NET "adc_5v_en_n_o" LOC = R8;
NET "adc_5v_en_n_o" IOSTANDARD = "LVCMOS25";
NET "led_tx_err_n_o" LOC = C19;
NET "led_tx_err_n_o" IOSTANDARD = "LVCMOS25";
NET "led_tx_act_n_o" LOC = A19;
NET "led_tx_act_n_o" IOSTANDARD = "LVCMOS25";
NET "led_rx_err_n_o" LOC = B20;
NET "led_rx_err_n_o" IOSTANDARD = "LVCMOS25";
NET "led_rx_act_n_o" LOC = A20;
NET "led_rx_act_n_o" IOSTANDARD = "LVCMOS25";
NET "led_sync_act_n_o" LOC = W10;
NET "led_sync_act_n_o" IOSTANDARD = "LVCMOS25";
NET "led_sync_err_n_o" LOC = Y10;
NET "led_sync_err_n_o" IOSTANDARD = "LVCMOS25";
NET "tp1_o" LOC = AA16;
NET "tp1_o" IOSTANDARD = "LVCMOS25";
NET "tp2_o" LOC = AB16;
NET "tp2_o" IOSTANDARD = "LVCMOS25";
NET "tp3_o" LOC = Y17;
NET "tp3_o" IOSTANDARD = "LVCMOS25";
NET "tp4_o" LOC = AB17;
NET "tp4_o" IOSTANDARD = "LVCMOS25";
# <ucfgen_end>
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2015/07/27
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk" TNM_NET = U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk;
TIMESPEC TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_P_clk = PERIOD "U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback" TNM_NET = U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback;
TIMESPEC TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_feedback = PERIOD "U_Node_Template/U_GN4124_Core/cmp_clk_in/feedback" 5 ns HIGH 50%;
NET "l_rst_n_i" TIG;
NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/rst_*" TIG;
\ No newline at end of file
gateware/top/spec/spec_masterfip_pts.vhd deleted 100644 → 0
View file @ e18ab308
--_________________________________________________________________________________________________
-- |
-- |SPEC masterFIP| |
-- |
-- CERN, BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- spec_masterfip_pts |
-- |
---------------------------------------------------------------------------------------------------
-- File spec_masterfip_pts.vhd |
-- |
-- Description Top level of the masterFIP design with Mock Turtle on a SPEC carrier. |
-- |
-- Figure 1 shows the architecture and main components of the design. |
-- ______________________________________________________________________ |
-- | | |
-- | _________________________________________ | |
-- | | MOCK TURTLE | | |
-- _ | | _____ | | |
-- | | | | ___ | | | | |
-- |F| | . .| . . . . . . . . . . . >| | | | | | |
-- |I| | _____ . | | | | | | | |
-- |E| | | | . | . . . . . . . .>| | | | | | |
-- |L| <--| | | . | . HMQs | | | | | | |
-- |D| | | F | . | . | | | | | | |
-- |R| | | M | . | ______ | | | | | | |
-- |I| -->| | C | . | DP | | | | | | | | |
-- |V| | | | . .|. .>| CPU0 | _____ | X | | G | | | |
-- |E| | | M | ____ . | |______| | | | b | | N | | | <-PCIe->|
-- |_| | | A | | | . | | SH. | | a | | 4 | | | host |
-- | | S |....|Xbar|... | ______ | MEM | | r | | 1 | | | |
-- ext pulse --> | | T | |____| . | | | |_____| | | | 2 | | | |
-- | | E | . | DP | CPU1 | | | | 4 | | | |
-- | | R | . .|. .>|______| | | | | | | |
-- FMC 1wire <-->| | F | | . | | | | | | |
-- | | I | | . HMQs | | | | | | |
-- | | P | | . . . . . . . . >|___| | | | | |
-- FMC LEDs <--| | | | |_____| | | |
-- | |_____| | _^_ | | |
-- | | | | | | |
-- | | |VIC| | | |
-- | | |___| | | |
-- | |_________________________________________| | |
-- |______________________________________________________________________| |
-- Figure 1: spec_masterfip_pts architecture |
-- |
-- |
-- FMC MASTERFIP CORE: |
-- On one side the FMC MASTERFIP CORE is the interface to the FMC hardware (i.e. |
-- FielDrive chip, external pulse LEMO, 1-wire DS18B20 chip, LEDs) on the other side |
-- it provides a wbgen2 WISHBONE where a set of control and status registers have |
-- been defined to interface with the MOCK TURTLE. |
-- The core ignores the notion of the WorldFIP frame type (ID_DAT/RT_DAT/..etc), |
-- or the macrocycle sequence and macrocycle timing; the sw running on the Mock |
-- Turtle CPUs is responsible for managing these aspects and for providing to this |
-- core all the payload bytes (coming from the host) that have to be serializedand, |
-- together with a serialization startup trigger, or for enabling the deserializer |
-- and then providing to the host the deserialized bytes. |
-- Figure 2 shows the structure of a WorldFIP frame. The core is internally |
-- generating (in the case of serialization) or validating (in the case of |
-- deserialization) only the FSS, CRC and FES bytes; the rest of the bytes are |
-- retrieved from or provided to the MOCK TURTLE. The core also encodes/decodes all |
-- the bytes to/from the Manchester2 code (as specified by the WorldFIP protocol) and|
-- controls/monitors all the FielDrive signals. |
-- _____________________________________________________________________________ |
-- |_____FSS_____|__Ctrl__|_____________Payload_____________|_____CRC____|__FES__| |
-- |
-- Figure 2: WorldFIP frame structure |
-- |
-- MOCK TURTLE: |
-- Instead of having a big FSM in HDL that would be executing the WorldFIP |
-- macrocycle, we have software running on an embedded CPU, in order to add |
-- flexibility and ease the implementation of the design. Mock Turtle is the |
-- generic core that offers multi-CPU processing and all the infrastructure around. |
-- The interface between the CPUs and the PCIe host is though HostMessageQueues(HMQ).|
-- The interface between the CPUs with the FMC MASTERFIP CORE is a set of wbgen2- |
-- generated registers. |
-- In this design MT is configured with 2 CPUs: |
-- - CPU0 is the heart of the design; it is "playing" the WorldFIP macrocycle. |
-- For example,it initiates the delivery of a WorldFIP question frame, by providing|
-- the frame bytes to the FMC MASTERFIP CORE, and then awaits for the reception of |
-- the response frame.It retrieves these consumed data from the FMC MASTERFIP CORE,|
-- packs them in the corresponding HMQ (according to the frame type) and can notify|
-- the host through an IRQ. |
-- - CPU1 is mainly polling the host to retrieve new payload bytes for production. |
-- When new data is received from the host through a dedicated HMQ, CPU1 puts them |
-- into the Shared Memory for CPU0 to retrieve them and provide them to the |
-- FMC MASTERFIP CORE for serialization. |
-- CPU1 does not need access to the FMC MASTERFIP CORE; however access is possible |
-- for debugging purposes. |
-- |
-- XBAR: |
-- The crossbar between the FMC MASTERFIP CORE and MOCK TURTLE is used so that |
-- CPU0, CPU1 and to the PCIe host can access directly the wbgen2-defined regs |
-- in the FMC MASTERFIP CORE. |
-- Note that to give access to the FMC MASTERFIP CORE to both CPU0 and CPU1, we |
-- could have used the Shared Port of MT, instead of using the Dedicated Ports (DP) |
-- and this crossbar; this though would have also affected (potentially slowed down) |
-- the accesses to the MT Shared Memory. |
-- Note also that as mentioned above CPU1 is only accessing the FMC MASTERFIP CORE |
-- for debugging purposes; the same goes also for the PCIe host. |
-- |
-- CLK, RST: |
-- There is only one clock domain of 100 MHz, in the whole design. The clock is |
-- generated inside the MOCK TURTLE, from the 125 MHz SPEC PLL IC6 output clock |
-- (clk_125m_pllref_p_i,clk_125m_pllref_n_i) and it is used by both MOCK TURTLE CPUs,|
-- by the FMC MASTERFIP CORE and the XBAR. A PCIe reset signal, synchronous to |
-- the 100 MHz clock is also provided by MOCK TURTLE. |
-- |
-- MEMORY MAP AS SEEN FROM PCIe: |
-- 0x00000000 (size: 4 bytes) : SDB signature |
-- 0x00002000 (size: 64 bytes) : VIC |
-- 0x00010000 (size: 644 bytes) : Host access to the FMC MASTERFIP CORE |
-- 0x00020000 (size: 128 kB) : MOCK TURTLE |
-- |-- 0x00020000 : HMQ Global Control Registers |
-- |-- 0x00024000 : HMQ incoming slots (Host->CPUs) |
-- |-- 0x00028000 : HMQ outgoing slots (CPUs->Host) |
-- |-- 0x0002c000 : CPU Control/Status Registers |
-- |-- 0x00030000 : Shared Memory (64 KB) |
-- |
-- Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Eva Calvo Giraldo (Eva.Calvo.Giraldo@cern.ch) |
-- Tomasz Wlostowski (Tomasz.Wlostowski@cern.ch) |
-- |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, please download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all; -- std_logic definitions
use IEEE.numeric_std.all; -- conversion functions
library work;
use work.wishbone_pkg.all; -- for the wb_crossbar
use work.spec_node_pkg.all; -- for the spec_node_template definition
use work.wr_node_pkg.all; -- for the spec_node_template configuration
use work.wrn_mqueue_pkg.all; -- for the HMQ
use work.masterFIP_pkg.all; -- for the fmc_masterfip_core definition
use work.masterfip_wbgen2_pkg.all; -- for the masterfip_wbgen2_csr records
entity spec_masterfip_pts is
generic (g_simulation : boolean := false);
port
(-- Carrier signals
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Clock
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference,
clk_125m_pllref_n_i : in std_logic; -- used in MT to generate 100 MHz
-- GENNUM interface
l_rst_n_i : in std_logic; -- reset from GENNUM (RSTOUT18_N)
gpio_b : inout std_logic_vector(1 downto 0); -- general purpose interface
-- -- PCIe to Local [Inbound Data] - RX
p2l_rdy_o : out std_logic; -- rx buffer full flag
p2l_clkn_i : in std_logic; -- receiver source synch clock-
p2l_clkp_i : in std_logic; -- receiver source synch clock+
p2l_data_i : in std_logic_vector(15 downto 0);-- parallel receive data
p2l_dframe_i : in std_logic; -- receive frame
p2l_valid_i : in std_logic; -- receive data valid
-- -- Inbound Buffer Request/Status
p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe write request
p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe write ready
rx_error_o : out std_logic; -- receive error
-- -- Local to Parallel [Outbound Data] - TX
l2p_data_o : out std_logic_vector(15 downto 0);-- parallel transmit data
l2p_dframe_o : out std_logic; -- transmit data frame
l2p_valid_o : out std_logic; -- transmit data valid
l2p_clkn_o : out std_logic; -- transmitter source synch clock-
l2p_clkp_o : out std_logic; -- transmitter source synch clock+
l2p_edb_o : out std_logic; -- packet termination and discard
-- -- Outbound Buffer Status
l2p_rdy_i : in std_logic; -- tx buffer full flag
l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local read resp data ready
tx_error_i : in std_logic; -- transmit error
vc_rdy_i : in std_logic_vector(1 downto 0); -- channel ready
-- DAC I2C (driven by MT for max stability on the 100 MHz clk)
dac_cs_n_o : out std_logic_vector(1 downto 0); -- 0: select SPEC 25MHz OSC5 VCXO
dac_sclk_o : out std_logic; -- 1: select SPEC 20MHz OSC1 VCXO
dac_din_o : out std_logic;
-- SPEC LEDs
led_green_o : out std_logic; -- blinking with clk_100m_sys
led_red_o : out std_logic; -- active during a PCIe rst, l_rst_n_i
-- PCB version
pcb_ver_i : in std_logic_vector(3 downto 0);
-- FMC signals
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- FMC presence
fmc_prsnt_m2c_n_i : in std_logic; -- FMC presence (used by MT)
-- fmc i2c interface
fmc_scl_io : inout std_logic;
fmc_sda_io : inout std_logic;
-- FMC 1-wire
fmc_onewire_b : inout std_logic; -- temper and unique id
-- WorldFIP bus speed -- 31K25bps: speed_b1=0, speed_b0=0
speed_b0_i : in std_logic; -- 1Mbps : speed_b1=0, speed_b0=1
speed_b1_i : in std_logic; -- 2M5bps : speed_b1=1, speed_b0=0
-- 5Mbps : speed_b1=1, speed_b0=1
-- WorldFIP FielDrive
fd_rstn_o : out std_logic; -- reset
fd_rxcdn_i : in std_logic; -- rx carrier detect
fd_rxd_i : in std_logic; -- rx data
fd_txer_i : in std_logic; -- tx error
fd_wdgn_i : in std_logic; -- tx watchdog
fd_txck_o : out std_logic; -- tx clk
fd_txd_o : out std_logic; -- tx data
fd_txena_o : out std_logic; -- tx enable
-- External synchronisation pulse (input signal and transceiver control)
ext_sync_term_en_o : out std_logic; -- enable 50 Ohm termin of the pulse
ext_sync_dir_o : out std_logic := '0'; -- direction fixed B -> A
ext_sync_oe_n_o : out std_logic := '0'; -- output fixed to enabled
ext_sync_i : in std_logic; -- sync pulse
-- FMC Front panel LEDs: controlled by the MT firmware, updated every macrocycle
led_rx_act_n_o : out std_logic;
led_rx_err_n_o : out std_logic;
led_tx_act_n_o : out std_logic;
led_tx_err_n_o : out std_logic;
led_sync_act_n_o : out std_logic; -- stays OFF when ext_sync is not used
led_sync_err_n_o : out std_logic; -- stays OFF when ext_sync is not used
-- Test points
tp1_o : out std_logic; -- connected to fd_rxd
tp2_o : out std_logic; -- connected to fd_txd
tp3_o : out std_logic; -- connected to MT led&dbg reg bit 8
tp4_o : out std_logic; -- connected to MT led&dbg reg bit 9
-- To be removed on hw V3
adc_1v8_shdn_n_o : out std_logic;
adc_m5v_shdn_n_o : out std_logic;
adc_5v_en_n_o : out std_logic);
end spec_masterfip_pts;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of spec_masterfip_pts is
---------------------------------------------------------------------------------------------------
-- MOCK TURTLE CONSTANTS --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- HMQ: It total 10 HMQs have been defined. Each HMQ has 4 entries of 128 x 32 bits, each.
-- 8 "out HMQs" from the MT -> towards the host
-- - 0: HMQ from CPU0 with the WorldFIP payloads from periodic consumed variables
-- - 1: HMQ from CPU0 with the WorldFIP payloads from aperiodic consumed variables
-- (only for the case of identif variable, scheduled as periodic variable, by radMon app)
-- - 2: HMQ from CPU0 with the WorldFIP payloads from aperiodic consumed messages
-- - 3: HMQ from CPU0 with the WorldFIP payloads from periodic consumed diagnostic variables
-- (only for the case of the FIPdiag variable 0x067F)
-- - 4: HMQ from CPU0 with the WorldFIP payloads from aperiodic consumed diagnostic variables
-- (aperiodic presence and identification)
-- - 5: HMQ for debugging data from CPU0 and CPU1 towards the host
-- - 6: HMQ for the responses of CPU0 to the commands of the host, see below "in HMQ0"
-- (e.g.: acknowledgement of the configuration???)
-- - 7: HMQ for the responses of CPU1 to the commands of the host, see below "in HMQ1",
-- (e.g.: content of the report variable)
-- 2 "in HMQs" from the host -> towards MT
-- - 0: HMQ towards CPU0 with commands for the bus config, used only at startup (e.g.: HW_RESET,
-- PROGRAM_BA, BA_START, BA_RUNNING)
-- - 1: HMQ towards CPU1 with the payloads for produced WorldFIP frames (variables and messages;
-- CPU1 then puts this data into the Shared Memory for CPU0 to access and put them in the bus)
-- as well as requests for report data, requests for the scheduling of aperiodic traffic
-- (presence/ identification) etc (CPU1 again passes these requests into the Shared Memory).
constant C_HMQ_CONFIG : t_wrn_mqueue_config :=
(out_slot_count => 8, -- MT -> towards the host
out_slot_config =>
(0 => (width => 128, entries => 4),
1 => (width => 128, entries => 4),
2 => (width => 128, entries => 4),
3 => (width => 128, entries => 4),
4 => (width => 128, entries => 4),
5 => (width => 128, entries => 4),
6 => (width => 128, entries => 4),
7 => (width => 128, entries => 4),
others => (0, 0)),
in_slot_count => 2, -- host -> towards MT
in_slot_config =>
(0 => (width => 128, entries => 4),
1 => (width => 128, entries => 4),
others => (0, 0)));
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- RMQs not used!
constant C_RMQ_CONFIG : t_wrn_mqueue_config :=
(out_slot_count => 0,
out_slot_config => (others => (0, 0)),
in_slot_count => 0,
in_slot_config => (others => (0, 0)));
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
constant C_NODE_CONFIG : t_wr_node_config :=
(app_id => x"0f1dc03e",
cpu_count => 2,
cpu_memsizes => (98304, 8192, 0, 0, 0, 0, 0, 0), -- in bytes; for CPU0 the size should be enough
-- for the storage of the RT sw running on CPU0
-- and for the macrocycle configuration
hmq_config => C_HMQ_CONFIG,
rmq_config => C_RMQ_CONFIG,
shared_mem_size => 65536); -- in bytes
constant c_wb_spec_csr_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000001F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000603",
version => x"00000001",
date => x"20121116",
name => "WB-SPEC-CSR ")));
constant c_MASTERFIP_SDB_DEVICE : t_sdb_device :=(
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"0000000000000FFF",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000AAA", -- ...
version => x"00000001",
date => x"20151006",
name => "WB-MASTERFIP.CSR ")));
constant c_MASTERFIP_PTS_SDB_DEVICE : t_sdb_device :=(
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000001F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000AAA", -- ...
version => x"00000001",
date => x"20151006",
name => "WB-MASTERFIP.CSR ")));
-- SPEC carrier CSR constants
constant c_CARRIER_TYPE : std_logic_vector(15 downto 0) := X"0001";
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- crossbar constants
constant c_SDB_ADDRESS : t_wishbone_address := x"0000_0000";
constant c_fmc_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0000_ffff", x"0000_0000");
constant c_fmc_bridge_record_sdb : t_sdb_record := f_sdb_embed_bridge( c_fmc_bridge_sdb, x"0001_0000");
constant c_NUM_WB_SLAVES : integer := 4;
constant c_WB_SLAVE_STATUS_CSR : integer := 0;
constant c_WB_SLAVE_FMC_I2C : integer := 1;
constant c_WB_SLAVE_MF_PTS_CSR : integer := 2;
constant c_WB_SLAVE_MF_CORE : integer := 3;
constant c_NUM_WB_MASTERS : integer := 3;
constant c_WB_MASTER_TURTLE0 : integer := 0;
constant c_WB_MASTER_TURTLE1 : integer := 1;
constant c_WB_MASTER_FMCPERIPH : integer := 2;
-- constant wbmain_addr_mf_core_c : t_wishbone_address := x"0001_0000";
-- constant wbmain_mask_mf_core_c : t_wishbone_address := x"ffff_f000";
-- constant wbmain_addr_mf_pts_c : t_wishbone_address := x"0001_1000";
-- constant wbmain_mask_mf_pts_c : t_wishbone_address := x"ffff_f000";
-- constant wbmain_addr_status_c : t_wishbone_address := x"0001_2000";
-- constant wbmain_mask_status_c : t_wishbone_address := x"ffff_f000";
-- constant wbmain_addr_fmci2c_c : t_wishbone_address := x"0001_3000";
-- constant wbmain_mask_fmci2c_c : t_wishbone_address := x"ffff_f000";
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES - 1 downto 0) :=
(
c_WB_SLAVE_STATUS_CSR => f_sdb_embed_device(c_wb_spec_csr_sdb, x"0000_4000"),
c_WB_SLAVE_FMC_I2C => f_sdb_embed_device(c_xwb_i2c_master_sdb, x"0000_5000"),
c_WB_SLAVE_MF_PTS_CSR => f_sdb_embed_device(c_MASTERFIP_PTS_SDB_DEVICE, x"0000_6000"),
c_WB_SLAVE_MF_CORE => f_sdb_embed_device(c_MASTERFIP_SDB_DEVICE, x"0000_7000")
);
-- constant wbmain_addr_c : t_wishbone_address_array( c_NUM_WB_SLAVES-1 downto 0 ) := (
-- c_WB_SLAVE_MF_CORE => wbmain_addr_mf_core_c,
-- c_WB_SLAVE_MF_PTS_CSR => wbmain_addr_mf_pts_c,
-- c_WB_SLAVE_STATUS_CSR => wbmain_addr_status_c,
-- c_WB_SLAVE_FMC_I2C => wbmain_addr_fmci2c_c
-- );
-- constant wbmain_mask_c : t_wishbone_address_array( c_NUM_WB_SLAVES-1 downto 0 ) := (
-- c_WB_SLAVE_MF_CORE => wbmain_mask_mf_core_c,
-- c_WB_SLAVE_MF_PTS_CSR => wbmain_mask_mf_pts_c,
-- c_WB_SLAVE_STATUS_CSR => wbmain_mask_status_c,
-- c_WB_SLAVE_FMC_I2C => wbmain_mask_fmci2c_c
-- );
signal wbmain_slaves_ms : t_wishbone_master_out_array(0 to c_NUM_WB_SLAVES-1);
signal wbmain_slaves_sm : t_wishbone_master_in_array(0 to c_NUM_WB_SLAVES-1);
signal wbmain_masters_ms : t_wishbone_master_out_array(0 to c_NUM_WB_MASTERS-1);
signal wbmain_masters_sm : t_wishbone_master_in_array(0 to c_NUM_WB_MASTERS-1);
---------------------------------------------------------------------------------------------------
-- Signals --
---------------------------------------------------------------------------------------------------
-- clk, reset
signal clk_100m_sys : std_logic;
signal rst_n_sys : std_logic;
-- Mock Turtle
-- SPEC LEDs
signal led_divider : unsigned(22 downto 0);
signal leds : std_logic_vector(31 downto 0);
signal spec_led : std_logic_vector(7 downto 0);
signal fd_txd : std_logic;
-- Mezzanine system I2C for EEPROM
signal sys_scl_in : std_logic;
signal sys_scl_out : std_logic;
signal sys_scl_oe_n : std_logic;
signal sys_sda_in : std_logic;
signal sys_sda_out : std_logic;
signal sys_sda_oe_n : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- FIXED SIGNALS --
---------------------------------------------------------------------------------------------------
ext_sync_dir_o <= '0'; -- Direction fixed to: B -> A
ext_sync_oe_n_o <= '0'; -- Output fixed to: enabled
-- To be removed on hw V3
-- Note: For the hw v1 signals ext_sync_tst_n_o, adc_prim_conn_n_o and adc_sec_conn_n_o, in order
-- to disable them (that is set them to 'Z'), the ISE setting "Unused IOB pins" is set to
-- "floating", so there is no need to declare them.
adc_1v8_shdn_n_o <= '0'; -- OFF
adc_m5v_shdn_n_o <= '0'; -- OFF
adc_5v_en_n_o <= '1'; -- OFF
---------------------------------------------------------------------------------------------------
-- MOCK TURTLE CORE --
---------------------------------------------------------------------------------------------------
cmp_mock_turtle : spec_node_template
generic map
(g_simulation => g_simulation,
g_with_wr_phy => false, -- no White Rabbit support, dah
g_with_white_rabbit => false,
g_double_wrnode_core_clock => false,
g_system_clock_freq => 100000000, -- both CPUs at 100 MHz
g_wr_node_config => C_NODE_CONFIG,
g_fmc0_sdb => c_fmc_bridge_record_sdb
)
port map
(clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
rst_n_sys_o => rst_n_sys, -- PCIe rst, synced with clk_sys
clk_sys_o => clk_100m_sys, -- 100 MHz; one clk domain in the whole design
-- PCIe interface
l_rst_n => l_rst_n_i,
gpio => gpio_b,
p2l_rdy => p2l_rdy_o,
p2l_clkn => p2l_clkn_i,
p2l_clkp => p2l_clkp_i,
p2l_data => p2l_data_i,
p2l_dframe => p2l_dframe_i,
p2l_valid => p2l_valid_i,
p_wr_req => p_wr_req_i,
p_wr_rdy => p_wr_rdy_o,
rx_error => rx_error_o,
l2p_data => l2p_data_o,
l2p_dframe => l2p_dframe_o,
l2p_valid => l2p_valid_o,
l2p_clkn => l2p_clkn_o,
l2p_clkp => l2p_clkp_o,
l2p_edb => l2p_edb_o,
l2p_rdy => l2p_rdy_i,
l_wr_rdy => l_wr_rdy_i,
p_rd_d_rdy => p_rd_d_rdy_i,
tx_error => tx_error_i,
vc_rdy => vc_rdy_i,
-- DAC interface
dac_sclk_o => dac_sclk_o,
dac_din_o => dac_din_o,
dac_cs1_n_o => dac_cs_n_o(0),
dac_cs2_n_o => dac_cs_n_o(1),
-- FMC presence
fmc_prsnt_m2c_l_i => fmc_prsnt_m2c_n_i,
-- WISHBONE connection of the fmc_masterFIP_core to the MT CPUs
dp_master_o(0) => wbmain_masters_ms(c_WB_MASTER_TURTLE0), -- access from MT CPU0 at base address 0x100000
dp_master_o(1) => wbmain_masters_ms(c_WB_MASTER_TURTLE1),
dp_master_i(0) => wbmain_masters_sm(c_WB_MASTER_TURTLE0), -- access from MT CPU1 at base address 0x100000
dp_master_i(1) => wbmain_masters_sm(c_WB_MASTER_TURTLE1),
-- WISHBONE connection of the fmc_masterFIP_core to the host
fmc0_host_wb_o => wbmain_masters_ms(c_WB_MASTER_FMCPERIPH), -- access from PCIe host at base address 0x10000
fmc0_host_wb_i => wbmain_masters_sm(c_WB_MASTER_FMCPERIPH),
fmc0_host_irq_i => '0',
-- not used
clk_20m_vcxo_i => '0',
clk_125m_gtp_n_i => '0',
clk_125m_gtp_p_i => '1');
---------------------------------------------------------------------------------------------------
-- XBAR --
---------------------------------------------------------------------------------------------------
-- Crossbar to give access to the fmc_masterFIP_core to CPU0, CPU1 and directly to the PCIe host.
-- Note that to give access to the fmc_masterFIP_core to both CPU0 and CPU1, the SP of MT could
-- have been used instead of the DP and this crossbar; this though would have also affected
-- (potentially slowed down) the accesses to the MT Shared Memory.
-- Note that in the MT firmware the CPU1 is only accessing the masterfip_leds register for debugging
-- purposes. The PCIe host is accessing the core directly only for testing purposes.
cmp_wb_crossbar : xwb_sdb_crossbar
generic map
(g_num_masters => c_NUM_WB_MASTERS,
g_num_slaves => c_NUM_WB_SLAVES,
g_registered => true,
g_wraparound => true,
g_layout => c_INTERCONNECT_LAYOUT,
g_sdb_addr => c_SDB_ADDRESS)
port map
(clk_sys_i => clk_100m_sys,
rst_n_i => rst_n_sys,
slave_i => wbmain_masters_ms,
slave_o => wbmain_masters_sm,
master_o => wbmain_slaves_ms,
master_i => wbmain_slaves_sm);
---------------------------------------------------------------------------------------------------
-- FMC MASTERFIP CORE --
---------------------------------------------------------------------------------------------------
cmp_masterFIP_core : fmc_masterFIP_core
generic map
(g_span => 32,
g_width => 32,
values_for_simul => g_simulation
)
port map
(clk_i => clk_100m_sys,
rst_n_i => rst_n_sys,
-- FMC one-wire
onewire_b => fmc_onewire_b,
-- WorldFIP speed
speed_b0_i => speed_b0_i,
speed_b1_i => speed_b1_i,
-- FIELDRIVE
fd_rxcdn_a_i => fd_rxcdn_i,
fd_rxd_a_i => fd_rxd_i,
fd_txer_a_i => fd_txer_i,
fd_wdgn_a_i => fd_wdgn_i,
fd_rstn_o => fd_rstn_o,
fd_txck_o => fd_txck_o,
fd_txd_o => fd_txd,
fd_txena_o => fd_txena_o,
-- External Synch
ext_sync_term_en_o => ext_sync_term_en_o,
ext_sync_a_i => ext_sync_i,
ext_sync_dir_o => open, -- hard-wired to '0'
ext_sync_oe_n_o => open, -- hard-wired to '0'
-- LEDs
leds_o => leds,
-- WISHBONE interface with MT CPU0 and CPU1
wb_adr_i => wbmain_slaves_ms(c_WB_SLAVE_MF_CORE).adr,
wb_dat_i => wbmain_slaves_ms(c_WB_SLAVE_MF_CORE).dat,
wb_stb_i => wbmain_slaves_ms(c_WB_SLAVE_MF_CORE).stb,
wb_we_i => wbmain_slaves_ms(c_WB_SLAVE_MF_CORE).we,
wb_cyc_i => wbmain_slaves_ms(c_WB_SLAVE_MF_CORE).cyc,
wb_sel_i => wbmain_slaves_ms(c_WB_SLAVE_MF_CORE).sel,
wb_dat_o => wbmain_slaves_sm(c_WB_SLAVE_MF_CORE).dat,
wb_ack_o => wbmain_slaves_sm(c_WB_SLAVE_MF_CORE).ack,
wb_stall_o => wbmain_slaves_sm(c_WB_SLAVE_MF_CORE).stall);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- unused WISHBONE signals
wbmain_slaves_sm(c_WB_SLAVE_MF_CORE).err <= '0';
wbmain_slaves_sm(c_WB_SLAVE_MF_CORE).rty <= '0';
wbmain_slaves_sm(c_WB_SLAVE_MF_CORE).int <= '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
led_rx_act_n_o <= leds(0); -- probe on R4
led_rx_err_n_o <= leds(1); -- probe on R8
led_tx_act_n_o <= leds(2); -- probe on R4
led_tx_err_n_o <= leds(3); -- probe on R7
led_sync_act_n_o <= leds(4); -- probe on R1
led_sync_err_n_o <= leds(5); -- probe on R6
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
fd_txd_o <= fd_txd;
tp1_o <= fd_rxd_i;
tp2_o <= fd_txd;
tp3_o <= leds(8);
tp4_o <= leds(9);
---------------------------------------------------------------------------------------------------
-- SPEC front panel LEDs --
---------------------------------------------------------------------------------------------------
drive_led_clk_sys: process (clk_100m_sys)
begin
if rising_edge(clk_100m_sys) then
if(rst_n_sys = '0') then
spec_led <= "01111111";
led_divider <= (others => '0');
else
led_divider <= led_divider+ 1;
if(led_divider = 0) then
spec_led <= spec_led(6 downto 0) & spec_led(7);
end if;
end if;
end if;
end process;
led_green_o <= spec_led(7);
led_red_o <= not rst_n_sys;
------------------------------------------------------------------------------
-- Carrier CSR
-- Carrier type and PCB version
-- Bitstream (firmware) type and date
-- Release tag
-- VCXO DAC control (CLR_N)
------------------------------------------------------------------------------
cmp_carrier_csr : entity work.carrier_csr
port map(
rst_n_i => rst_n_sys,
clk_sys_i => clk_100m_sys,
wb_adr_i => wbmain_slaves_ms(c_WB_SLAVE_STATUS_CSR).adr(3 downto 2), -- wbmain_slaves_ms.adr is byte address
wb_dat_i => wbmain_slaves_ms(c_WB_SLAVE_STATUS_CSR).dat,
wb_dat_o => wbmain_slaves_sm(c_WB_SLAVE_STATUS_CSR).dat,
wb_cyc_i => wbmain_slaves_ms(c_WB_SLAVE_STATUS_CSR).cyc,
wb_sel_i => wbmain_slaves_ms(c_WB_SLAVE_STATUS_CSR).sel,
wb_stb_i => wbmain_slaves_ms(c_WB_SLAVE_STATUS_CSR).stb,
wb_we_i => wbmain_slaves_ms(c_WB_SLAVE_STATUS_CSR).we,
wb_ack_o => wbmain_slaves_sm(c_WB_SLAVE_STATUS_CSR).ack,
wb_stall_o => open,
carrier_csr_carrier_pcb_rev_i => pcb_ver_i,
carrier_csr_carrier_reserved_i => X"000",
carrier_csr_carrier_type_i => c_CARRIER_TYPE,
carrier_csr_stat_fmc_pres_i => fmc_prsnt_m2c_n_i,
carrier_csr_stat_p2l_pll_lck_i => '1',
carrier_csr_stat_sys_pll_lck_i => '1',
carrier_csr_stat_ddr3_cal_done_i => '1',
carrier_csr_ctrl_led_green_o => open,
carrier_csr_ctrl_led_red_o => open,
carrier_csr_ctrl_dac_clr_n_o => open,
carrier_csr_rst_fmc0_n_o => open,
carrier_csr_rst_fmc0_n_i => '0',
carrier_csr_rst_fmc0_n_load_o => open
);
-- Mezzanine system managment I2C master
-- Access to mezzanine EEPROM
------------------------------------------------------------------------------
cmp_fmc_sys_i2c : xwb_i2c_master
generic map(
g_interface_mode => CLASSIC,
g_address_granularity => BYTE
)
port map (
clk_sys_i => clk_100m_sys,
rst_n_i => rst_n_sys,
slave_i => wbmain_slaves_ms(c_WB_SLAVE_FMC_I2C),
slave_o => wbmain_slaves_sm(c_WB_SLAVE_FMC_I2C),
desc_o => open,
scl_pad_i(0) => sys_scl_in,
scl_pad_o(0) => sys_scl_out,
scl_padoen_o(0) => sys_scl_oe_n,
sda_pad_i(0) => sys_sda_in,
sda_pad_o(0) => sys_sda_out,
sda_padoen_o(0) => sys_sda_oe_n
);
-- Tri-state buffer for SDA and SCL
fmc_scl_io <= sys_scl_out when sys_scl_oe_n = '0' else 'Z';
sys_scl_in <= fmc_scl_io;
fmc_sda_io <= sys_sda_out when sys_sda_oe_n = '0' else 'Z';
sys_sda_in <= fmc_sda_io;
-- Tri-state buffer for SDA and SCL
end rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
--------------------------------------------------------------------------------------------------
\ No newline at end of file
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