Commit b8de055a authored by Marek Gumiński's avatar Marek Gumiński

Fixed watchdog part of test02.

Added firmware supporting watchdog test.
Last register update (just in case).

Allowed flattened stucture in FPGA design in order to help routing.

Included binary was build with previous commit.
parent 30c3283c
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_csr.vhd
-- Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/ip_cores/gw-masterfip/rtl/wbgen/masterfip_csr.wb
-- Created : Mon Apr 24 10:20:14 2017
-- Created : Mon Apr 24 13:49:01 2017
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/ip_cores/gw-masterfip/rtl/wbgen/masterfip_csr.wb
......
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.vhd
-- Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.wb
-- Created : Mon Apr 24 10:20:17 2017
-- Created : Mon Apr 24 13:49:04 2017
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.wb
......
......@@ -28,7 +28,7 @@
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -306,7 +306,7 @@
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Modelsim-SE Mixed" xil_pn:valueState="default"/>
......@@ -400,7 +400,7 @@
</file>
<file xil_pn:name="../../ip_cores/nanofip-gateware/src/wf_rx_osc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="149"/>
<association xil_pn:name="Implementation" xil_pn:seqID="142"/>
<association xil_pn:name="Implementation" xil_pn:seqID="143"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/cpu/wrn_cpu_iram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
......@@ -432,7 +432,7 @@
</file>
<file xil_pn:name="../../ip_cores/nanofip-gateware/src/wf_tx_serializer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="147"/>
<association xil_pn:name="Implementation" xil_pn:seqID="140"/>
<association xil_pn:name="Implementation" xil_pn:seqID="141"/>
</file>
<file xil_pn:name="../../ip_cores/gw-masterfip/rtl/wf_package.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="92"/>
......@@ -448,7 +448,7 @@
</file>
<file xil_pn:name="../../ip_cores/nanofip-gateware/src/wf_tx_osc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="148"/>
<association xil_pn:name="Implementation" xil_pn:seqID="141"/>
<association xil_pn:name="Implementation" xil_pn:seqID="142"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/mqueue/wrn_mqueue_irq_unit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
......@@ -588,7 +588,7 @@
</file>
<file xil_pn:name="../../ip_cores/nanofip-gateware/src/wf_rx_deserializer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="150"/>
<association xil_pn:name="Implementation" xil_pn:seqID="143"/>
<association xil_pn:name="Implementation" xil_pn:seqID="144"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
......@@ -700,7 +700,7 @@
</file>
<file xil_pn:name="../../ip_cores/nanofip-gateware/src/wf_rx_deglitcher.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="151"/>
<association xil_pn:name="Implementation" xil_pn:seqID="144"/>
<association xil_pn:name="Implementation" xil_pn:seqID="145"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/mqueue/wrn_mqueue_host.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="114"/>
......@@ -770,10 +770,6 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="91"/>
<association xil_pn:name="Implementation" xil_pn:seqID="91"/>
</file>
<file xil_pn:name="../../ip_cores/gw-masterfip/rtl/masterFIP_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="142"/>
<association xil_pn:name="Implementation" xil_pn:seqID="145"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
......@@ -864,7 +860,7 @@
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/wr_node_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="144"/>
<association xil_pn:name="Implementation" xil_pn:seqID="137"/>
<association xil_pn:name="Implementation" xil_pn:seqID="138"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
......@@ -1383,7 +1379,7 @@
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="145"/>
<association xil_pn:name="Implementation" xil_pn:seqID="138"/>
<association xil_pn:name="Implementation" xil_pn:seqID="139"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="184"/>
......@@ -1677,7 +1673,7 @@
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="146"/>
<association xil_pn:name="Implementation" xil_pn:seqID="139"/>
<association xil_pn:name="Implementation" xil_pn:seqID="140"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
......@@ -1767,6 +1763,10 @@
<file xil_pn:name="../../top/spec/spec_masterfip_pts.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../rtl/masterFIP_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="435"/>
<association xil_pn:name="Implementation" xil_pn:seqID="137"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/spec/ip_cores/fifo_32x512.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
......
......@@ -141,7 +141,7 @@ do
echo " "
# run tests
sudo ${top}/pts/ptsFip.py -b FmcMasterFip -s $serial -e $extra_serial "-t${top}/python -l $LOGDIR 00 01 02 04 05 06
sudo ${top}/pts/ptsFip.py -b FmcMasterFip -s $serial -e $extra_serial "-t${top}/python" -l $LOGDIR 00 01 02 04 05 06
# backup eeprom image
......
......@@ -214,7 +214,7 @@ class fmcmasterfip:
self.fipcore.write_regname('rst.core', 1)
time.sleep(1)
self.fippts.write_regname('rst.core', 1)
self.fippts.write_regname('rst', 1)
def rst_fd(self):
self.fipcore.write_regname('rst.fd', 1)
......
......@@ -2,7 +2,7 @@
#
# * File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/python/regs/carrier_addrtable.py
# * Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/carrier_csr.wb
# * Created : Mon Apr 24 10:20:14 2017
# * Created : Mon Apr 24 13:49:01 2017
#
# THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/carrier_csr.wb
# DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
......
......@@ -2,7 +2,7 @@
#
# * File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/python/regs/masterfip_csr.py
# * Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/ip_cores/gw-masterfip/rtl/wbgen/masterfip_csr.wb
# * Created : Mon Apr 24 10:20:15 2017
# * Created : Mon Apr 24 13:49:02 2017
#
# THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/ip_cores/gw-masterfip/rtl/wbgen/masterfip_csr.wb
# DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
......
......@@ -2,7 +2,7 @@
#
# * File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/python/regs/masterfip_pts_csr.py
# * Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.wb
# * Created : Mon Apr 24 10:20:17 2017
# * Created : Mon Apr 24 13:49:04 2017
#
# THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.wb
# DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
......
......@@ -178,7 +178,7 @@ def test_txerr( dut, box, maxtries = 50 ):
dut.fippts.write_regname('tx_corrupt',0)
########################################################################
util.section_msg("Checking if TX_ERR is not stack on active value")
util.info_msg("Checking if TX_ERR is not stack on active value")
for i in xrange(10):
# check pin value during bus idle
......@@ -219,7 +219,7 @@ def test_txerr( dut, box, maxtries = 50 ):
util.err_msg( "TX_ERR counter after transmission: %d" % det )
########################################################################
util.section_msg("Checking if TX_ERR IS going active during corrupted transmission (serial output is constant 1)")
util.info_msg("Checking if TX_ERR IS going active during corrupted transmission (serial output is constant 1)")
dut.rst_core()
util.info_msg("\nTX_ERR counter before transmission: %d" % dut.fippts.read_regname('fd_txerr_cnt') )
......@@ -258,7 +258,7 @@ def test_wdgn( dut ):
###################### test ##################################################
########################################################################
util.section_msg("Checking if WDG_N is not stack on active value")
util.info_msg("Checking if WDG_N is not stack on active value")
result = { }
for i in xrange(10):
......
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