Commit adccd96c authored by Marek Gumiński's avatar Marek Gumiński

Modified hdl in order to test synchronisation line without adc

parent 0e2e9c99
......@@ -210,6 +210,7 @@ architecture rtl of fmc_masterFIP_core_pts is
signal speed : std_logic_vector(1 downto 0);
-- ext pulse
signal ext_sync_p, ext_sync_oe : std_logic;
signal ext_sync_iodir : std_logic;
signal ext_sync_p_cnt_rst, ext_sync_p_cnt_host_rst : std_logic;
signal ext_sync_p_cnt : std_logic_vector(31 downto 0);
-- counters
......@@ -294,38 +295,7 @@ architecture rtl of fmc_masterFIP_core_pts is
-- architecture begin
--=================================================================================================
begin
--
-- -- enable all power
-- masterfip_1v8_shdn_n <= '1';
-- masterfip_m5v_shdn_n <= '1';
-- masterfip_5v_en_n <= '0';
-- -- oe_n must be low to enable inputs/outputs
-- -- when oe_n is higt, all other ports are High-Z
-- masterfip_ext_sync_oe_n <= '0';
---- DIR = high -> A data to B bus
---- DIR = low -> B data to A bus
---- in order to use ext_syc as INPUT, DIR pin must be LOW
-- masterfip_ext_sync_dir <= '0';
--
---- high-z - relay off
---- prim enables adc measurement of primary (device) side of transformer
---- sec enabled adc measurement of secondary (bus) side of transformer
-- masterfip_sec_conn_n <= 'Z';
-- masterfip_prim_conn_n <= 'Z';
--
---- pull up resistor pulls pmos transistor gate high
---- when masterfip_ext_sync_tst_n is set to high-z, transistor is off,
---- ext_sync works normal
---- when masterfip_ext_sync_tst_n is set to '0', transistor is on,
---- ext_sync is connected to vdd
-- masterfip_ext_sync_tst_n <= 'Z';
--
---- pull down resistor pulls nmos transistor gate low
---- when masterfip_ext_sync_term_en is set to high-z, transistor is off,
---- ext_sync is NOT terminated
---- when masterfip_ext_sync_term_en is set to '1', transistor is on,
---- ext_sync is TERMINATED with 50 Ohm
-- masterfip_ext_sync_term_en <= 'Z';
bus_term_en_n_o <= '1';
......@@ -370,6 +340,7 @@ begin
-- external sync pulse
mf_ext_sync_term_en_o => ext_sync_term_en_o,
mf_ext_sync_dir_o => ext_sync_dir,
mf_ext_sync_fpga_io_dir_o => ext_sync_iodir,
mf_ext_sync_oe_o => ext_sync_oe,
mf_ext_sync_tst_o => ext_sync_tst,
mf_ext_sync_output_value_o => ext_sync_out_val,
......@@ -573,7 +544,7 @@ begin
-- same here
adc_5v_en_n_o <= not adc_5v_en;
ext_sync_i <= ext_sync_out_val when ext_sync_dir = '1' else 'Z';
ext_sync_i <= ext_sync_out_val when ext_sync_iodir = '1' else 'Z';
ext_sync_dir_o <= ext_sync_dir;
---------------------------------------------------------------------------------------------------
-- resets --
......
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for FMC masterFIP core registers
---------------------------------------------------------------------------------------
-- File : /home/gumas/projects/cti/fmcmasterfip/gateware/rtl/fmc_masterfip_csr_pts.vhd
-- Author : auto-generated by wbgen2 from /home/gumas/projects/cti/fmcmasterfip/gateware/rtl/wbgen/fmc_masterfip_csr.wb
-- Created : Tue Jun 7 16:15:16 2016
-- File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/fmc_masterfip_csr_pts.vhd
-- Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/fmc_masterfip_csr.wb
-- Created : Tue Mar 7 12:59:02 2017
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/fmcmasterfip/gateware/rtl/wbgen/fmc_masterfip_csr.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/fmc_masterfip_csr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
......@@ -70,6 +70,8 @@ entity fmc_masterfip_csr_pts is
mf_ext_sync_output_value_o : out std_logic;
-- Port for BIT field: 'pulses counter reset' in reg: 'ext sync'
mf_ext_sync_p_cnt_rst_o : out std_logic;
-- Port for BIT field: 'FPGA IO direction' in reg: 'ext sync'
mf_ext_sync_fpga_io_dir_o : out std_logic;
-- Port for BIT field: 'ext_sync_raw_input' in reg: 'ext sync raw input'
mf_ext_sync_raw_input_i : in std_logic;
-- Port for std_logic_vector field: 'ext_sync_p_cnt' in reg: 'ext sync pulses cnt'
......@@ -427,6 +429,7 @@ signal mf_ext_sync_oe_int : std_logic ;
signal mf_ext_sync_tst_int : std_logic ;
signal mf_ext_sync_output_value_int : std_logic ;
signal mf_ext_sync_p_cnt_rst_int : std_logic ;
signal mf_ext_sync_fpga_io_dir_int : std_logic ;
signal mf_test_corrupt_int : std_logic ;
signal mf_macrocyc_lgth_int : std_logic_vector(30 downto 0);
signal mf_macrocyc_start_int : std_logic ;
......@@ -553,6 +556,7 @@ begin
mf_ext_sync_tst_int <= '0';
mf_ext_sync_output_value_int <= '0';
mf_ext_sync_p_cnt_rst_int <= '0';
mf_ext_sync_fpga_io_dir_int <= '0';
mf_test_corrupt_int <= '0';
mf_macrocyc_lgth_int <= "0000000000000000000000000000000";
mf_macrocyc_start_int <= '0';
......@@ -791,6 +795,7 @@ begin
mf_ext_sync_tst_int <= wrdata_reg(3);
mf_ext_sync_output_value_int <= wrdata_reg(4);
mf_ext_sync_p_cnt_rst_int <= wrdata_reg(8);
mf_ext_sync_fpga_io_dir_int <= wrdata_reg(9);
end if;
rddata_reg(0) <= mf_ext_sync_term_en_int;
rddata_reg(1) <= mf_ext_sync_dir_int;
......@@ -798,10 +803,10 @@ begin
rddata_reg(3) <= mf_ext_sync_tst_int;
rddata_reg(4) <= mf_ext_sync_output_value_int;
rddata_reg(8) <= mf_ext_sync_p_cnt_rst_int;
rddata_reg(9) <= mf_ext_sync_fpga_io_dir_int;
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
......@@ -2126,6 +2131,8 @@ begin
mf_ext_sync_output_value_o <= mf_ext_sync_output_value_int;
-- pulses counter reset
mf_ext_sync_p_cnt_rst_o <= mf_ext_sync_p_cnt_rst_int;
-- FPGA IO direction
mf_ext_sync_fpga_io_dir_o <= mf_ext_sync_fpga_io_dir_int;
-- ext_sync_raw_input
-- ext_sync_p_cnt
-- tx corrupt
......
......@@ -266,6 +266,16 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "FPGA IO direction";
prefix = "fpga_io_dir";
description = "Direction of FPGA IO";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
......
......@@ -247,6 +247,8 @@ NET "masterfip_c2m_adc_clk_n" LOC = U12;
NET "masterfip_ext_sync_term_en" LOC = AB13;
NET "masterfip_ext_sync_term_en" IOSTANDARD = LVCMOS25;
NET "masterfip_ext_sync" LOC = T8;
NET "masterfip_ext_sync" PULLDOWN;
NET "masterfip_ext_sync" IOSTANDARD = LVCMOS25;
NET "masterfip_ext_sync_tst_n" LOC = U8;
NET "masterfip_ext_sync_tst_n" IOSTANDARD = LVCMOS25;
......
......@@ -101,7 +101,7 @@ def test_termination( dut, box ):
util.info_msg("Enabling termination (pulldown)")
dut.fipcore.write_regname('ext_sync.term_en', 0)
dut.fipcore.write_regname('ext_sync.term_en', 1)
time.sleep(DEL)
......@@ -150,7 +150,7 @@ def test_oen( dut, box ):
if lowinput == 0:
util.info_msg("Read low input value")
else :
util.err_msg("Read high input value" )
util.info_msg("Read high input value" )
###############################################################################
......@@ -165,14 +165,14 @@ def test_oen( dut, box ):
if highinput == 0:
util.info_msg("Read low input value")
else :
util.err_msg("Read high input value" )
util.info_msg("Read high input value" )
box.trigger_input_low()
time.sleep(DEL)
###############################################################################
if lowinput = highinput :
if lowinput == highinput :
result['Output enable'] = 1
util.info_msg("Value read from disabled buffer didn't change no matter buffer input")
else :
......@@ -215,7 +215,7 @@ def test_dir( dut, box ):
if lowinput == 0:
util.info_msg("Read low input value")
else :
util.err_msg("Read high input value" )
util.info_msg("Read high input value" )
###############################################################################
......@@ -230,7 +230,7 @@ def test_dir( dut, box ):
if highinput == 0:
util.info_msg("Read low input value")
else :
util.err_msg("Read high input value" )
util.info_msg("Read high input value" )
box.trigger_input_low()
dut.fipcore.write_regname('ext_sync.dir', 0)
......@@ -238,7 +238,7 @@ def test_dir( dut, box ):
###############################################################################
if lowinput = highinput :
if lowinput == highinput :
result['Direction selection'] = 1
util.info_msg("Value read from buffer set to output didn't change no matter buffer input")
else :
......
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