Removed unused gateware submodules.
Added masterfip-gw submodule. Updated other submodules to work with masterfip-gw. Generated csr files for new masterfip_core. Updated ise project. Verified implementation of spec_masterfip_pts.
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ddr3-sp6-core @ 7496ea02
etherbone-core @ c1e676dc
fmc-adc-100m14b4cha-gw @ 94c7ce24
general-cores @ 1c2dd12b
gn4124-core @ e3a0bf97
nanofip-gateware @ 752512a8
wr-cores @ d0d4d09d
wr-node-core @ 96a78592
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python/regs/masterfip_csr.py
0 → 100644
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