Commit 4a5088eb authored by Marek Gumiński's avatar Marek Gumiński

Removed unused gateware submodules.

Added masterfip-gw submodule.
Updated other submodules to work with masterfip-gw.
Generated csr files for new masterfip_core.
Updated ise project.
Verified implementation of spec_masterfip_pts.
parent 2c46e85b
[submodule "gateware/ip_cores/general-cores"]
path = gateware/ip_cores/general-cores
url = git://ohwr.org/hdl-core-lib/general-cores.git
[submodule "gateware/ip_cores/fmc-adc-100m14b4cha-gw"]
path = gateware/ip_cores/fmc-adc-100m14b4cha-gw
url = git://ohwr.org/fmc-projects/fmc-adc-100m14b4cha/fmc-adc-100m14b4cha-gw.git
[submodule "gateware/ip_cores/gn4124-core"]
path = gateware/ip_cores/gn4124-core
url = git://ohwr.org/hdl-core-lib/gn4124-core.git
......@@ -13,9 +10,6 @@
[submodule "gateware/ip_cores/wr-node-core"]
path = gateware/ip_cores/wr-node-core
url = git://ohwr.org/white-rabbit/wr-node-core.git
[submodule "gateware/ip_cores/ddr3-sp6-core"]
path = gateware/ip_cores/ddr3-sp6-core
url = git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git
[submodule "software/spec-sw"]
path = software/spec-sw
url = git://ohwr.org/fmc-projects/spec/spec-sw.git
......@@ -28,3 +22,9 @@
[submodule "gateware/ip_cores/gw-masterfip"]
path = gateware/ip_cores/gw-masterfip
url = git://ohwr.org/cern-fip/masterfip/masterfip-gw.git
[submodule "gateware/ip_cores/etherbone-core"]
path = gateware/ip_cores/etherbone-core
url = git://ohwr.org/hdl-core-lib/etherbone-core.git
[submodule "gateware/ip_cores/nanofip-gateware"]
path = gateware/ip_cores/nanofip-gateware
url = git://ohwr.org/cern-fip/nanofip/nanofip-gateware.git
ddr3-sp6-core @ 7496ea02
Subproject commit 7496ea0237449047f452be15567546b5dff364f5
etherbone-core @ c1e676dc
Subproject commit c1e676dc9d35028910c50431d70328e522396c89
Subproject commit 94c7ce240aad469c5ea7e6a821ffe4697b94da46
general-cores @ 1c2dd12b
Subproject commit 2f134e412e762fd8970c673bf4ea77c3e162e9bb
Subproject commit 1c2dd12b1bceeab3b32b41c3522931c658ad15a7
gn4124-core @ e3a0bf97
Subproject commit ffea5479190c09938cbba9b7076953c5c41645f3
Subproject commit e3a0bf97e125020c83bff6e40199a717e7fda738
nanofip-gateware @ 752512a8
Subproject commit 752512a82a05ce5ac4c69ad19f68921762bdd512
wr-cores @ d0d4d09d
Subproject commit f3437dd82dd2267c63f3df341daac8972184cd9e
Subproject commit d0d4d09d5f0355dfc6c078171bc6856e580a7496
wr-node-core @ 96a78592
Subproject commit 13d98e48f9870bfa6a914c1eba698d7d90c1c6e8
Subproject commit 96a78592b4d20140bf13662476605ab7e96d7710
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/fmc_masterfip_csr_pts.vhd
-- Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/fmc_masterfip_csr.wb
-- Created : Tue Mar 7 12:59:02 2017
-- Created : Wed Mar 15 14:47:49 2017
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/fmc_masterfip_csr.wb
......
This source diff could not be displayed because it is too large. You can view the blob instead.
......@@ -81,6 +81,7 @@
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -132,9 +133,9 @@
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|spec_top_fmc_masterfip|rtl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../top/spec/spec_top_fmc_masterfip.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/spec_top_fmc_masterfip" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|spec_masterfip_pts|rtl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../top/spec/spec_masterfip_pts.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/spec_masterfip_pts" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -196,7 +197,7 @@
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="spec_top_fmc_masterfip" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="spec_masterfip_pts" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
......@@ -210,10 +211,10 @@
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="spec_top_fmc_masterfip_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="spec_top_fmc_masterfip_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="spec_top_fmc_masterfip_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="spec_top_fmc_masterfip_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="spec_masterfip_pts_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="spec_masterfip_pts_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="spec_masterfip_pts_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="spec_masterfip_pts_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -341,29 +342,17 @@
<libraries/>
<files>
<file xil_pn:name="../../ip_cores/fmc-adc-100m14b4cha-gw/hdl/ip_cores/multishot_dpram.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/fmc-adc-100m14b4cha-gw/hdl/ip_cores/adc_sync_fifo.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../top/spec/spec_top_fmc_masterfip.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/fmc-adc-100m14b4cha-gw/hdl/ip_cores/wb_ddr_fifo.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_infrastructure.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -371,95 +360,59 @@
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/fmc-adc-100m14b4cha-gw/hdl/adc/rtl/fmc_adc_100Ms_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="93"/>
</file>
<file xil_pn:name="../../ip_cores/masterfip-gw/rtl/masterfip_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="42"/>
</file>
<file xil_pn:name="../../ip_cores/fmc-adc-100m14b4cha-gw/hdl/adc/rtl/fmc_adc_mezzanine.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/fmc-adc-100m14b4cha-gw/hdl/adc/rtl/var_sat_s.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/fmc-adc-100m14b4cha-gw/hdl/ip_cores/monostable/monostable_rtl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="65"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="93"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/fmc-adc-100m14b4cha-gw/hdl/adc/rtl/fmc_adc_100Ms_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/fmc-adc-100m14b4cha-gw/hdl/ip_cores/timetag_core/rtl/timetag_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="64"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_word_packer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="80"/>
</file>
<file xil_pn:name="../../ip_cores/masterfip-gw/rtl/from_nanofip/wf_crc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="175"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="83"/>
</file>
<file xil_pn:name="../../ip_cores/fmc-adc-100m14b4cha-gw/hdl/ip_cores/timetag_core/rtl/timetag_core_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="63"/>
<association xil_pn:name="Implementation" xil_pn:seqID="178"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="68"/>
</file>
<file xil_pn:name="../../rtl/fmc_masterfip_adc_100Ms_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="74"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
<association xil_pn:name="Implementation" xil_pn:seqID="144"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="78"/>
</file>
<file xil_pn:name="../../ip_cores/fmc-adc-100m14b4cha-gw/hdl/adc/rtl/offset_gain_s.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="68"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="72"/>
<association xil_pn:name="Implementation" xil_pn:seqID="173"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
<association xil_pn:name="Implementation" xil_pn:seqID="146"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -470,54 +423,33 @@
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/ddr3_ctrl_spec_bank3_64b_32b.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="70"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/masterfip-gw/rtl/from_nanofip/wf_rx_deserializer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="57"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="71"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/masterfip-gw/rtl/free_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="410"/>
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<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="153"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd" xil_pn:type="FILE_VHDL">
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</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_raw_slave.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="433"/>
<association xil_pn:name="Implementation" xil_pn:seqID="74"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="161"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_xilinx_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="453"/>
<association xil_pn:name="Implementation" xil_pn:seqID="186"/>
</file>
<file xil_pn:name="../../ip_cores/gw-masterfip/rtl/masterfip_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="142"/>
</file>
<file xil_pn:name="../../ip_cores/gw-masterfip/rtl/fmc_masterFIP_core.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/gw-masterfip/rtl/decr_counter.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/gw-masterfip/rtl/incr_counter.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/gw-masterfip/rtl/irq_generator.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/gw-masterfip/rtl/masterFIP_pkg.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/gw-masterfip/rtl/masterfip_tx.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/gw-masterfip/rtl/masterfip_wbgen2_csr.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/gw-masterfip/rtl/wf_package.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_ds182x_interface.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/nanofip-gateware/src/wf_decr_counter.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/nanofip-gateware/src/wf_cons_bytes_processor.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/nanofip-gateware/src/wf_consumption.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/nanofip-gateware/src/wf_crc.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/nanofip-gateware/src/wf_dualram_512x8_clka_rd_clkb_wr.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/nanofip-gateware/src/wf_engine_control.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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<file xil_pn:name="../../ip_cores/nanofip-gateware/src/wf_fd_receiver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="484"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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<file xil_pn:name="../../ip_cores/nanofip-gateware/src/wf_fd_transmitter.vhd" xil_pn:type="FILE_VHDL">
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</file>
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<file xil_pn:name="../../ip_cores/nanofip-gateware/src/wf_jtag_controller.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/nanofip-gateware/src/wf_model_constr_decoder.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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<file xil_pn:name="../../ip_cores/nanofip-gateware/src/wf_prod_data_lgth_calc.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/nanofip-gateware/src/wf_prod_permit.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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<file xil_pn:name="../../ip_cores/nanofip-gateware/src/wf_production.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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<file xil_pn:name="../../ip_cores/nanofip-gateware/src/wf_reset_unit.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/nanofip-gateware/src/wf_rx_deglitcher.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="168"/>
</file>
<file xil_pn:name="../../ip_cores/nanofip-gateware/src/wf_rx_deserializer.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="167"/>
</file>
<file xil_pn:name="../../ip_cores/nanofip-gateware/src/wf_rx_osc.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="166"/>
</file>
<file xil_pn:name="../../ip_cores/nanofip-gateware/src/wf_status_bytes_gen.vhd" xil_pn:type="FILE_VHDL">
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</file>
<file xil_pn:name="../../ip_cores/nanofip-gateware/src/wf_tx_osc.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="165"/>
</file>
<file xil_pn:name="../../ip_cores/nanofip-gateware/src/wf_tx_serializer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="500"/>
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</file>
<file xil_pn:name="../../ip_cores/nanofip-gateware/src/wf_wb_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="501"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
<bindings>
<binding xil_pn:location="/spec_top_fmc_masterfip" xil_pn:name="../../top/spec/spec_top_fmc_masterfip.ucf"/>
<binding xil_pn:location="/spec_top_fmc_masterfip" xil_pn:name="../../top/spec/spec_masterfip_pts.ucf"/>
</bindings>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
......
#----------------------------------------
# BANK 0 P2V5: Clock
#----------------------------------------
NET "clk_125m_pllref_n_i" LOC = F10;
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_p_i" LOC = G9;
NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
#----------------------------------------
# BANK 1 P1V8: PCIe interface
#----------------------------------------
NET "l_rst_n_i" LOC = N20;
NET "l_rst_n_i" IOSTANDARD = "LVCMOS18";
NET "L2P_CLKN_o" LOC = K22;
NET "L2P_CLKN_o" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_CLKP_o" LOC = K21;
NET "L2P_CLKP_o" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_DFRAME_o" LOC = U22;
NET "L2P_DFRAME_o" IOSTANDARD = "SSTL18_I";
NET "L2P_EDB_o" LOC = U20;
NET "L2P_EDB_o" IOSTANDARD = "SSTL18_I";
NET "L2P_RDY_i" LOC = U19;
NET "L2P_RDY_i" IOSTANDARD = "SSTL18_I";
NET "L2P_VALID_o" LOC = T18;
NET "L2P_VALID_o" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY_i[0]" LOC = R20;
NET "L_WR_RDY_i[0]" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY_i[1]" LOC = T22;
NET "L_WR_RDY_i[1]" IOSTANDARD = "SSTL18_I";
NET "P2L_CLKN_i" LOC = M19;
NET "P2L_CLKN_i" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_CLKP_i" LOC = M20;
NET "P2L_CLKP_i" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_DFRAME_i" LOC = J22;
NET "P2L_DFRAME_i" IOSTANDARD = "SSTL18_I";
NET "P2L_RDY_o" LOC = J16;
NET "P2L_RDY_o" IOSTANDARD = "SSTL18_I";
NET "P2L_VALID_i" LOC = L19;
NET "P2L_VALID_i" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY_i[0]" LOC = N16;
NET "P_RD_D_RDY_i[0]" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY_i[1]" LOC = P19;
NET "P_RD_D_RDY_i[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY_o[0]" LOC = L15;
NET "P_WR_RDY_o[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY_o[1]" LOC = K16;
NET "P_WR_RDY_o[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ_i[0]" LOC = M22;
NET "P_WR_REQ_i[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ_i[1]" LOC = M21;
NET "P_WR_REQ_i[1]" IOSTANDARD = "SSTL18_I";
NET "RX_ERROR_o" LOC = J17;
NET "RX_ERROR_o" IOSTANDARD = "SSTL18_I";
NET "TX_ERROR_i" LOC = M17;
NET "TX_ERROR_i" IOSTANDARD = "SSTL18_I";
NET "VC_RDY_i[0]" LOC = B21;
NET "VC_RDY_i[0]" IOSTANDARD = "SSTL18_I";
NET "VC_RDY_i[1]" LOC = B22;
NET "VC_RDY_i[1]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[0]" LOC = P16;
NET "L2P_DATA_o[0]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[1]" LOC = P21;
NET "L2P_DATA_o[1]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[2]" LOC = P18;
NET "L2P_DATA_o[2]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[3]" LOC = T20;
NET "L2P_DATA_o[3]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[4]" LOC = V21;
NET "L2P_DATA_o[4]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[5]" LOC = V19;
NET "L2P_DATA_o[5]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[6]" LOC = W22;
NET "L2P_DATA_o[6]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[7]" LOC = Y22;
NET "L2P_DATA_o[7]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[8]" LOC = P22;
NET "L2P_DATA_o[8]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[9]" LOC = R22;
NET "L2P_DATA_o[9]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[10]" LOC = T21;
NET "L2P_DATA_o[10]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[11]" LOC = T19;
NET "L2P_DATA_o[11]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[12]" LOC = V22;
NET "L2P_DATA_o[12]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[13]" LOC = V20;
NET "L2P_DATA_o[13]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[14]" LOC = W20;
NET "L2P_DATA_o[14]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[15]" LOC = Y21;
NET "L2P_DATA_o[15]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[0]" LOC = K20;
NET "P2L_DATA_i[0]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[1]" LOC = H22;
NET "P2L_DATA_i[1]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[2]" LOC = H21;
NET "P2L_DATA_i[2]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[3]" LOC = L17;
NET "P2L_DATA_i[3]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[4]" LOC = K17;
NET "P2L_DATA_i[4]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[5]" LOC = G22;
NET "P2L_DATA_i[5]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[6]" LOC = G20;
NET "P2L_DATA_i[6]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[7]" LOC = K18;
NET "P2L_DATA_i[7]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[8]" LOC = K19;
NET "P2L_DATA_i[8]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[9]" LOC = H20;
NET "P2L_DATA_i[9]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[10]" LOC = J19;
NET "P2L_DATA_i[10]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[11]" LOC = E22;
NET "P2L_DATA_i[11]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[12]" LOC = E20;
NET "P2L_DATA_i[12]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[13]" LOC = F22;
NET "P2L_DATA_i[13]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[14]" LOC = F21;
NET "P2L_DATA_i[14]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[15]" LOC = H19;
NET "P2L_DATA_i[15]" IOSTANDARD = "SSTL18_I";
#----------------------------------------
# BANK 0 P2V5: SPEC LEDs
#----------------------------------------
NET "GPIO_b[1]" LOC = U16;
NET "GPIO_b[1]" IOSTANDARD = "LVCMOS25";
NET "GPIO_b[0]" LOC = AB19;
NET "GPIO_b[0]" IOSTANDARD = "LVCMOS25";
NET "LED_RED_O" LOC = D5;
NET "LED_RED_O" IOSTANDARD = "LVCMOS25";
NET "LED_GREEN_O" LOC = E5;
NET "LED_GREEN_O" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# BANK 0 P2V5: SPEC DAC
#----------------------------------------
NET "dac_cs_n_o[0]" LOC = A3;
NET "dac_cs_n_o[0]" IOSTANDARD = "LVCMOS25";
NET "dac_cs_n_o[1]" LOC = B3;
NET "dac_cs_n_o[1]" IOSTANDARD = "LVCMOS25";
NET "dac_sclk_o" LOC = A4;
NET "dac_sclk_o" IOSTANDARD = "LVCMOS25";
NET "dac_din_o" LOC = C4;
NET "dac_din_o" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# Bank 2 P2V5: FMC
#----------------------------------------
NET "fmc_prsnt_m2c_n_i" LOC = AB14;
NET "fmc_prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
NET "fmc_onewire_b" LOC = "C18";
NET "fmc_onewire_b" IOSTANDARD = "LVCMOS25";
NET "fd_rstn_o" LOC = "Y18";
NET "fd_rstn_o" IOSTANDARD = "LVCMOS25";
NET "fd_txd_o" LOC = "T14";
NET "fd_txd_o" IOSTANDARD = "LVCMOS25";
NET "fd_txck_o" LOC = "W17";
NET "fd_txck_o" IOSTANDARD = "LVCMOS25";
NET "fd_txer_i" LOC = "T11";
NET "fd_txer_i" IOSTANDARD = "LVCMOS25";
NET "fd_rxcdn_i" LOC = "T15";
NET "fd_rxcdn_i" IOSTANDARD = "LVCMOS25";
NET "fd_rxd_i" LOC = "U15";
NET "fd_rxd_i" IOSTANDARD = "LVCMOS25";
NET "fd_wdgn_i" LOC = "R11";
NET "fd_wdgn_i" IOSTANDARD = "LVCMOS25";
NET "fd_txena_o" LOC = "R13";
NET "fd_txena_o" IOSTANDARD = "LVCMOS25";
NET "speed_b0_i" LOC = Y5;
NET "speed_b0_i" IOSTANDARD = "LVCMOS25";
NET "speed_b1_i" LOC = AB5;
NET "speed_b1_i" IOSTANDARD = "LVCMOS25";
NET "ext_sync_term_en_o" LOC = AB13;
NET "ext_sync_term_en_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_i" LOC = T8;
NET "ext_sync_i" IOSTANDARD = "LVCMOS25";
NET "ext_sync_oe_n_o" LOC = W6;
NET "ext_sync_oe_n_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_dir_o" LOC = Y6;
NET "ext_sync_dir_o" IOSTANDARD = "LVCMOS25";
NET "adc_1v8_shdn_n_o" LOC = V17;
NET "adc_1v8_shdn_n_o" IOSTANDARD = "LVCMOS25";
NET "adc_m5v_shdn_n_o" LOC = W18;
NET "adc_m5v_shdn_n_o" IOSTANDARD = "LVCMOS25";
NET "adc_5v_en_n_o" LOC = R8;
NET "adc_5v_en_n_o" IOSTANDARD = "LVCMOS25";
NET "led_tx_err_n_o" LOC = C19;
NET "led_tx_err_n_o" IOSTANDARD = "LVCMOS25";
NET "led_tx_act_n_o" LOC = A19;
NET "led_tx_act_n_o" IOSTANDARD = "LVCMOS25";
NET "led_rx_err_n_o" LOC = B20;
NET "led_rx_err_n_o" IOSTANDARD = "LVCMOS25";
NET "led_rx_act_n_o" LOC = A20;
NET "led_rx_act_n_o" IOSTANDARD = "LVCMOS25";
NET "led_sync_act_n_o" LOC = W10;
NET "led_sync_act_n_o" IOSTANDARD = "LVCMOS25";
NET "led_sync_err_n_o" LOC = Y10;
NET "led_sync_err_n_o" IOSTANDARD = "LVCMOS25";
NET "tp1_o" LOC = AA16;
NET "tp1_o" IOSTANDARD = "LVCMOS25";
NET "tp2_o" LOC = AB16;
NET "tp2_o" IOSTANDARD = "LVCMOS25";
NET "tp3_o" LOC = Y17;
NET "tp3_o" IOSTANDARD = "LVCMOS25";
NET "tp4_o" LOC = AB17;
NET "tp4_o" IOSTANDARD = "LVCMOS25";
# <ucfgen_end>
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2015/07/27
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk" TNM_NET = U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk;
TIMESPEC TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_P_clk = PERIOD "U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback" TNM_NET = U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback;
TIMESPEC TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_feedback = PERIOD "U_Node_Template/U_GN4124_Core/cmp_clk_in/feedback" 5 ns HIGH 50%;
NET "l_rst_n_i" TIG;
NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/rst_*" TIG;
\ No newline at end of file
--_________________________________________________________________________________________________
-- |
-- |SPEC masterFIP| |
-- |
-- CERN, BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- spec_masterfip_pts |
-- |
---------------------------------------------------------------------------------------------------
-- File spec_masterfip_pts.vhd |
-- |
-- Description Top level of the masterFIP design with Mock Turtle on a SPEC carrier. |
-- |
-- Figure 1 shows the architecture and main components of the design. |
-- ______________________________________________________________________ |
-- | | |
-- | _________________________________________ | |
-- | | MOCK TURTLE | | |
-- _ | | _____ | | |
-- | | | | ___ | | | | |
-- |F| | . .| . . . . . . . . . . . >| | | | | | |
-- |I| | _____ . | | | | | | | |
-- |E| | | | . | . . . . . . . .>| | | | | | |
-- |L| <--| | | . | . HMQs | | | | | | |
-- |D| | | F | . | . | | | | | | |
-- |R| | | M | . | ______ | | | | | | |
-- |I| -->| | C | . | DP | | | | | | | | |
-- |V| | | | . .|. .>| CPU0 | _____ | X | | G | | | |
-- |E| | | M | ____ . | |______| | | | b | | N | | | <-PCIe->|
-- |_| | | A | | | . | | SH. | | a | | 4 | | | host |
-- | | S |....|Xbar|... | ______ | MEM | | r | | 1 | | | |
-- ext pulse --> | | T | |____| . | | | |_____| | | | 2 | | | |
-- | | E | . | DP | CPU1 | | | | 4 | | | |
-- | | R | . .|. .>|______| | | | | | | |
-- FMC 1wire <-->| | F | | . | | | | | | |
-- | | I | | . HMQs | | | | | | |
-- | | P | | . . . . . . . . >|___| | | | | |
-- FMC LEDs <--| | | | |_____| | | |
-- | |_____| | _^_ | | |
-- | | | | | | |
-- | | |VIC| | | |
-- | | |___| | | |
-- | |_________________________________________| | |
-- |______________________________________________________________________| |
-- Figure 1: spec_masterfip_pts architecture |
-- |
-- |
-- FMC MASTERFIP CORE: |
-- On one side the FMC MASTERFIP CORE is the interface to the FMC hardware (i.e. |
-- FielDrive chip, external pulse LEMO, 1-wire DS18B20 chip, LEDs) on the other side |
-- it provides a wbgen2 WISHBONE where a set of control and status registers have |
-- been defined to interface with the MOCK TURTLE. |
-- The core ignores the notion of the WorldFIP frame type (ID_DAT/RT_DAT/..etc), |
-- or the macrocycle sequence and macrocycle timing; the sw running on the Mock |
-- Turtle CPUs is responsible for managing these aspects and for providing to this |
-- core all the payload bytes (coming from the host) that have to be serializedand, |
-- together with a serialization startup trigger, or for enabling the deserializer |
-- and then providing to the host the deserialized bytes. |
-- Figure 2 shows the structure of a WorldFIP frame. The core is internally |
-- generating (in the case of serialization) or validating (in the case of |
-- deserialization) only the FSS, CRC and FES bytes; the rest of the bytes are |
-- retrieved from or provided to the MOCK TURTLE. The core also encodes/decodes all |
-- the bytes to/from the Manchester2 code (as specified by the WorldFIP protocol) and|
-- controls/monitors all the FielDrive signals. |
-- _____________________________________________________________________________ |
-- |_____FSS_____|__Ctrl__|_____________Payload_____________|_____CRC____|__FES__| |
-- |
-- Figure 2: WorldFIP frame structure |
-- |
-- MOCK TURTLE: |
-- Instead of having a big FSM in HDL that would be executing the WorldFIP |
-- macrocycle, we have software running on an embedded CPU, in order to add |
-- flexibility and ease the implementation of the design. Mock Turtle is the |
-- generic core that offers multi-CPU processing and all the infrastructure around. |
-- The interface between the CPUs and the PCIe host is though HostMessageQueues(HMQ).|
-- The interface between the CPUs with the FMC MASTERFIP CORE is a set of wbgen2- |
-- generated registers. |
-- In this design MT is configured with 2 CPUs: |
-- - CPU0 is the heart of the design; it is "playing" the WorldFIP macrocycle. |
-- For example,it initiates the delivery of a WorldFIP question frame, by providing|
-- the frame bytes to the FMC MASTERFIP CORE, and then awaits for the reception of |
-- the response frame.It retrieves these consumed data from the FMC MASTERFIP CORE,|
-- packs them in the corresponding HMQ (according to the frame type) and can notify|
-- the host through an IRQ. |
-- - CPU1 is mainly polling the host to retrieve new payload bytes for production. |
-- When new data is received from the host through a dedicated HMQ, CPU1 puts them |
-- into the Shared Memory for CPU0 to retrieve them and provide them to the |
-- FMC MASTERFIP CORE for serialization. |
-- CPU1 does not need access to the FMC MASTERFIP CORE; however access is possible |
-- for debugging purposes. |
-- |
-- XBAR: |
-- The crossbar between the FMC MASTERFIP CORE and MOCK TURTLE is used so that |
-- CPU0, CPU1 and to the PCIe host can access directly the wbgen2-defined regs |
-- in the FMC MASTERFIP CORE. |
-- Note that to give access to the FMC MASTERFIP CORE to both CPU0 and CPU1, we |
-- could have used the Shared Port of MT, instead of using the Dedicated Ports (DP) |
-- and this crossbar; this though would have also affected (potentially slowed down) |
-- the accesses to the MT Shared Memory. |
-- Note also that as mentioned above CPU1 is only accessing the FMC MASTERFIP CORE |
-- for debugging purposes; the same goes also for the PCIe host. |
-- |
-- CLK, RST: |
-- There is only one clock domain of 100 MHz, in the whole design. The clock is |
-- generated inside the MOCK TURTLE, from the 125 MHz SPEC PLL IC6 output clock |
-- (clk_125m_pllref_p_i,clk_125m_pllref_n_i) and it is used by both MOCK TURTLE CPUs,|
-- by the FMC MASTERFIP CORE and the XBAR. A PCIe reset signal, synchronous to |
-- the 100 MHz clock is also provided by MOCK TURTLE. |
-- |
-- MEMORY MAP AS SEEN FROM PCIe: |
-- 0x00000000 (size: 4 bytes) : SDB signature |
-- 0x00002000 (size: 64 bytes) : VIC |
-- 0x00010000 (size: 644 bytes) : Host access to the FMC MASTERFIP CORE |
-- 0x00020000 (size: 128 kB) : MOCK TURTLE |
-- |-- 0x00020000 : HMQ Global Control Registers |
-- |-- 0x00024000 : HMQ incoming slots (Host->CPUs) |
-- |-- 0x00028000 : HMQ outgoing slots (CPUs->Host) |
-- |-- 0x0002c000 : CPU Control/Status Registers |
-- |-- 0x00030000 : Shared Memory (64 KB) |
-- |
-- Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Eva Calvo Giraldo (Eva.Calvo.Giraldo@cern.ch) |
-- Tomasz Wlostowski (Tomasz.Wlostowski@cern.ch) |
-- |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, please download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all; -- std_logic definitions
use IEEE.numeric_std.all; -- conversion functions
library work;
use work.wishbone_pkg.all; -- for the wb_crossbar
use work.spec_node_pkg.all; -- for the spec_node_template definition
use work.wr_node_pkg.all; -- for the spec_node_template configuration
use work.wrn_mqueue_pkg.all; -- for the HMQ
use work.masterFIP_pkg.all; -- for the fmc_masterfip_core definition
use work.masterfip_wbgen2_pkg.all; -- for the masterfip_wbgen2_csr records
entity spec_masterfip_pts is
generic (g_simulation : boolean := false);
port
(-- Carrier signals
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Clock
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference,
clk_125m_pllref_n_i : in std_logic; -- used in MT to generate 100 MHz
-- GENNUM interface
l_rst_n_i : in std_logic; -- reset from GENNUM (RSTOUT18_N)
gpio_b : inout std_logic_vector(1 downto 0); -- general purpose interface
-- -- PCIe to Local [Inbound Data] - RX
p2l_rdy_o : out std_logic; -- rx buffer full flag
p2l_clkn_i : in std_logic; -- receiver source synch clock-
p2l_clkp_i : in std_logic; -- receiver source synch clock+
p2l_data_i : in std_logic_vector(15 downto 0);-- parallel receive data
p2l_dframe_i : in std_logic; -- receive frame
p2l_valid_i : in std_logic; -- receive data valid
-- -- Inbound Buffer Request/Status
p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe write request
p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe write ready
rx_error_o : out std_logic; -- receive error
-- -- Local to Parallel [Outbound Data] - TX
l2p_data_o : out std_logic_vector(15 downto 0);-- parallel transmit data
l2p_dframe_o : out std_logic; -- transmit data frame
l2p_valid_o : out std_logic; -- transmit data valid
l2p_clkn_o : out std_logic; -- transmitter source synch clock-
l2p_clkp_o : out std_logic; -- transmitter source synch clock+
l2p_edb_o : out std_logic; -- packet termination and discard
-- -- Outbound Buffer Status
l2p_rdy_i : in std_logic; -- tx buffer full flag
l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local read resp data ready
tx_error_i : in std_logic; -- transmit error
vc_rdy_i : in std_logic_vector(1 downto 0); -- channel ready
-- DAC I2C (driven by MT for max stability on the 100 MHz clk)
dac_cs_n_o : out std_logic_vector(1 downto 0); -- 0: select SPEC 25MHz OSC5 VCXO
dac_sclk_o : out std_logic; -- 1: select SPEC 20MHz OSC1 VCXO
dac_din_o : out std_logic;
-- SPEC LEDs
led_green_o : out std_logic; -- blinking with clk_100m_sys
led_red_o : out std_logic; -- active during a PCIe rst, l_rst_n_i
-- FMC signals
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- FMC presence
fmc_prsnt_m2c_n_i : in std_logic; -- FMC presence (used by MT)
-- FMC 1-wire
fmc_onewire_b : inout std_logic; -- temper and unique id
-- WorldFIP bus speed -- 31K25bps: speed_b1=0, speed_b0=0
speed_b0_i : in std_logic; -- 1Mbps : speed_b1=0, speed_b0=1
speed_b1_i : in std_logic; -- 2M5bps : speed_b1=1, speed_b0=0
-- 5Mbps : speed_b1=1, speed_b0=1
-- WorldFIP FielDrive
fd_rstn_o : out std_logic; -- reset
fd_rxcdn_i : in std_logic; -- rx carrier detect
fd_rxd_i : in std_logic; -- rx data
fd_txer_i : in std_logic; -- tx error
fd_wdgn_i : in std_logic; -- tx watchdog
fd_txck_o : out std_logic; -- tx clk
fd_txd_o : out std_logic; -- tx data
fd_txena_o : out std_logic; -- tx enable
-- External synchronisation pulse (input signal and transceiver control)
ext_sync_term_en_o : out std_logic; -- enable 50 Ohm termin of the pulse
ext_sync_dir_o : out std_logic := '0'; -- direction fixed B -> A
ext_sync_oe_n_o : out std_logic := '0'; -- output fixed to enabled
ext_sync_i : in std_logic; -- sync pulse
-- FMC Front panel LEDs: controlled by the MT firmware, updated every macrocycle
led_rx_act_n_o : out std_logic;
led_rx_err_n_o : out std_logic;
led_tx_act_n_o : out std_logic;
led_tx_err_n_o : out std_logic;
led_sync_act_n_o : out std_logic; -- stays OFF when ext_sync is not used
led_sync_err_n_o : out std_logic; -- stays OFF when ext_sync is not used
-- Test points
tp1_o : out std_logic; -- connected to fd_rxd
tp2_o : out std_logic; -- connected to fd_txd
tp3_o : out std_logic; -- connected to MT led&dbg reg bit 8
tp4_o : out std_logic; -- connected to MT led&dbg reg bit 9
-- To be removed on hw V3
adc_1v8_shdn_n_o : out std_logic;
adc_m5v_shdn_n_o : out std_logic;
adc_5v_en_n_o : out std_logic);
end spec_masterfip_pts;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of spec_masterfip_pts is
---------------------------------------------------------------------------------------------------
-- MOCK TURTLE CONSTANTS --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- HMQ: It total 10 HMQs have been defined. Each HMQ has 4 entries of 128 x 32 bits, each.
-- 8 "out HMQs" from the MT -> towards the host
-- - 0: HMQ from CPU0 with the WorldFIP payloads from periodic consumed variables
-- - 1: HMQ from CPU0 with the WorldFIP payloads from aperiodic consumed variables
-- (only for the case of identif variable, scheduled as periodic variable, by radMon app)
-- - 2: HMQ from CPU0 with the WorldFIP payloads from aperiodic consumed messages
-- - 3: HMQ from CPU0 with the WorldFIP payloads from periodic consumed diagnostic variables
-- (only for the case of the FIPdiag variable 0x067F)
-- - 4: HMQ from CPU0 with the WorldFIP payloads from aperiodic consumed diagnostic variables
-- (aperiodic presence and identification)
-- - 5: HMQ for debugging data from CPU0 and CPU1 towards the host
-- - 6: HMQ for the responses of CPU0 to the commands of the host, see below "in HMQ0"
-- (e.g.: acknowledgement of the configuration???)
-- - 7: HMQ for the responses of CPU1 to the commands of the host, see below "in HMQ1",
-- (e.g.: content of the report variable)
-- 2 "in HMQs" from the host -> towards MT
-- - 0: HMQ towards CPU0 with commands for the bus config, used only at startup (e.g.: HW_RESET,
-- PROGRAM_BA, BA_START, BA_RUNNING)
-- - 1: HMQ towards CPU1 with the payloads for produced WorldFIP frames (variables and messages;
-- CPU1 then puts this data into the Shared Memory for CPU0 to access and put them in the bus)
-- as well as requests for report data, requests for the scheduling of aperiodic traffic
-- (presence/ identification) etc (CPU1 again passes these requests into the Shared Memory).
constant C_HMQ_CONFIG : t_wrn_mqueue_config :=
(out_slot_count => 8, -- MT -> towards the host
out_slot_config =>
(0 => (width => 128, entries => 4),
1 => (width => 128, entries => 4),
2 => (width => 128, entries => 4),
3 => (width => 128, entries => 4),
4 => (width => 128, entries => 4),
5 => (width => 128, entries => 4),
6 => (width => 128, entries => 4),
7 => (width => 128, entries => 4),
others => (0, 0)),
in_slot_count => 2, -- host -> towards MT
in_slot_config =>
(0 => (width => 128, entries => 4),
1 => (width => 128, entries => 4),
others => (0, 0)));
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- RMQs not used!
constant C_RMQ_CONFIG : t_wrn_mqueue_config :=
(out_slot_count => 0,
out_slot_config => (others => (0, 0)),
in_slot_count => 0,
in_slot_config => (others => (0, 0)));
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
constant C_NODE_CONFIG : t_wr_node_config :=
(app_id => x"0f1dc03e",
cpu_count => 2,
cpu_memsizes => (98304, 8192, 0, 0, 0, 0, 0, 0), -- in bytes; for CPU0 the size should be enough
-- for the storage of the RT sw running on CPU0
-- and for the macrocycle configuration
hmq_config => C_HMQ_CONFIG,
rmq_config => C_RMQ_CONFIG,
shared_mem_size => 65536); -- in bytes
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- crossbar constants
constant C_SLAVE_ADDR : t_wishbone_address_array(0 downto 0):= (0 => x"00000000");
constant C_SLAVE_MASK : t_wishbone_address_array(0 downto 0):= (0 => x"00000000");
---------------------------------------------------------------------------------------------------
-- Signals --
---------------------------------------------------------------------------------------------------
-- clk, reset
signal clk_100m_sys : std_logic;
signal rst_n_sys : std_logic;
-- Mock Turtle
signal fmc_core_wb_out : t_wishbone_master_out_array(0 to 2);
signal fmc_core_wb_in : t_wishbone_master_in_array(0 to 2);
signal fmc_wb_muxed_out : t_wishbone_master_out;
signal fmc_wb_muxed_in : t_wishbone_master_in;
-- SPEC LEDs
signal led_divider : unsigned(22 downto 0);
signal leds : std_logic_vector(31 downto 0);
signal spec_led : std_logic_vector(7 downto 0);
signal fd_txd : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- FIXED SIGNALS --
---------------------------------------------------------------------------------------------------
ext_sync_dir_o <= '0'; -- Direction fixed to: B -> A
ext_sync_oe_n_o <= '0'; -- Output fixed to: enabled
-- To be removed on hw V3
-- Note: For the hw v1 signals ext_sync_tst_n_o, adc_prim_conn_n_o and adc_sec_conn_n_o, in order
-- to disable them (that is set them to 'Z'), the ISE setting "Unused IOB pins" is set to
-- "floating", so there is no need to declare them.
adc_1v8_shdn_n_o <= '0'; -- OFF
adc_m5v_shdn_n_o <= '0'; -- OFF
adc_5v_en_n_o <= '1'; -- OFF
---------------------------------------------------------------------------------------------------
-- MOCK TURTLE CORE --
---------------------------------------------------------------------------------------------------
cmp_mock_turtle : spec_node_template
generic map
(g_simulation => g_simulation,
g_with_wr_phy => false, -- no White Rabbit support, dah
g_with_white_rabbit => false,
g_double_wrnode_core_clock => false,
g_system_clock_freq => 100000000, -- both CPUs at 100 MHz
g_wr_node_config => C_NODE_CONFIG)
port map
(clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
rst_n_sys_o => rst_n_sys, -- PCIe rst, synced with clk_sys
clk_sys_o => clk_100m_sys, -- 100 MHz; one clk domain in the whole design
-- PCIe interface
l_rst_n => l_rst_n_i,
gpio => gpio_b,
p2l_rdy => p2l_rdy_o,
p2l_clkn => p2l_clkn_i,
p2l_clkp => p2l_clkp_i,
p2l_data => p2l_data_i,
p2l_dframe => p2l_dframe_i,
p2l_valid => p2l_valid_i,
p_wr_req => p_wr_req_i,
p_wr_rdy => p_wr_rdy_o,
rx_error => rx_error_o,
l2p_data => l2p_data_o,
l2p_dframe => l2p_dframe_o,
l2p_valid => l2p_valid_o,
l2p_clkn => l2p_clkn_o,
l2p_clkp => l2p_clkp_o,
l2p_edb => l2p_edb_o,
l2p_rdy => l2p_rdy_i,
l_wr_rdy => l_wr_rdy_i,
p_rd_d_rdy => p_rd_d_rdy_i,
tx_error => tx_error_i,
vc_rdy => vc_rdy_i,
-- DAC interface
dac_sclk_o => dac_sclk_o,
dac_din_o => dac_din_o,
dac_cs1_n_o => dac_cs_n_o(0),
dac_cs2_n_o => dac_cs_n_o(1),
-- FMC presence
fmc_prsnt_m2c_l_i => fmc_prsnt_m2c_n_i,
-- WISHBONE connection of the fmc_masterFIP_core to the MT CPUs
dp_master_o(0) => fmc_core_wb_out(0), -- access from MT CPU0 at base address 0x100000
dp_master_o(1) => fmc_core_wb_out(1),
dp_master_i(0) => fmc_core_wb_in(0), -- access from MT CPU1 at base address 0x100000
dp_master_i(1) => fmc_core_wb_in(1),
-- WISHBONE connection of the fmc_masterFIP_core to the host
fmc0_host_wb_o => fmc_core_wb_out(2), -- access from PCIe host at base address 0x10000
fmc0_host_wb_i => fmc_core_wb_in(2),
fmc0_host_irq_i => '0',
-- not used
clk_20m_vcxo_i => '0',
clk_125m_gtp_n_i => '0',
clk_125m_gtp_p_i => '1');
---------------------------------------------------------------------------------------------------
-- XBAR --
---------------------------------------------------------------------------------------------------
-- Crossbar to give access to the fmc_masterFIP_core to CPU0, CPU1 and directly to the PCIe host.
-- Note that to give access to the fmc_masterFIP_core to both CPU0 and CPU1, the SP of MT could
-- have been used instead of the DP and this crossbar; this though would have also affected
-- (potentially slowed down) the accesses to the MT Shared Memory.
-- Note that in the MT firmware the CPU1 is only accessing the masterfip_leds register for debugging
-- purposes. The PCIe host is accessing the core directly only for testing purposes.
cmp_wb_crossbar : xwb_crossbar
generic map
(g_num_masters => 3,
g_num_slaves => 1,
g_registered => true,
g_address => C_SLAVE_ADDR,
g_mask => C_SLAVE_MASK)
port map
(clk_sys_i => clk_100m_sys,
rst_n_i => rst_n_sys,
slave_i(0) => fmc_core_wb_out(0),
slave_i(1) => fmc_core_wb_out(1),
slave_i(2) => fmc_core_wb_out(2),
slave_o(0) => fmc_core_wb_in(0),
slave_o(1) => fmc_core_wb_in(1),
slave_o(2) => fmc_core_wb_in(2),
master_o(0) => fmc_wb_muxed_out,
master_i(0) => fmc_wb_muxed_in);
---------------------------------------------------------------------------------------------------
-- FMC MASTERFIP CORE --
---------------------------------------------------------------------------------------------------
cmp_masterFIP_core : fmc_masterFIP_core
generic map
(g_span => 32,
g_width => 32,
values_for_simul => g_simulation)
port map
(clk_i => clk_100m_sys,
rst_n_i => rst_n_sys,
-- FMC one-wire
onewire_b => fmc_onewire_b,
-- WorldFIP speed
speed_b0_i => speed_b0_i,
speed_b1_i => speed_b1_i,
-- FIELDRIVE
fd_rxcdn_a_i => fd_rxcdn_i,
fd_rxd_a_i => fd_rxd_i,
fd_txer_a_i => fd_txer_i,
fd_wdgn_a_i => fd_wdgn_i,
fd_rstn_o => fd_rstn_o,
fd_txck_o => fd_txck_o,
fd_txd_o => fd_txd,
fd_txena_o => fd_txena_o,
-- External Synch
ext_sync_term_en_o => ext_sync_term_en_o,
ext_sync_a_i => ext_sync_i,
ext_sync_dir_o => open, -- hard-wired to '0'
ext_sync_oe_n_o => open, -- hard-wired to '0'
-- LEDs
leds_o => leds,
-- WISHBONE interface with MT CPU0 and CPU1
wb_adr_i => fmc_wb_muxed_out.adr,
wb_dat_i => fmc_wb_muxed_out.dat,
wb_stb_i => fmc_wb_muxed_out.stb,
wb_we_i => fmc_wb_muxed_out.we,
wb_cyc_i => fmc_wb_muxed_out.cyc,
wb_sel_i => fmc_wb_muxed_out.sel,
wb_dat_o => fmc_wb_muxed_in.dat,
wb_ack_o => fmc_wb_muxed_in.ack,
wb_stall_o => fmc_wb_muxed_in.stall);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- unused WISHBONE signals
fmc_wb_muxed_in.err <= '0';
fmc_wb_muxed_in.rty <= '0';
fmc_wb_muxed_in.int <= '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
led_rx_act_n_o <= leds(0); -- probe on R4
led_rx_err_n_o <= leds(1); -- probe on R8
led_tx_act_n_o <= leds(2); -- probe on R4
led_tx_err_n_o <= leds(3); -- probe on R7
led_sync_act_n_o <= leds(4); -- probe on R1
led_sync_err_n_o <= leds(5); -- probe on R6
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
fd_txd_o <= fd_txd;
tp1_o <= fd_rxd_i;
tp2_o <= fd_txd;
tp3_o <= leds(8);
tp4_o <= leds(9);
---------------------------------------------------------------------------------------------------
-- SPEC front panel LEDs --
---------------------------------------------------------------------------------------------------
drive_led_clk_sys: process (clk_100m_sys)
begin
if rising_edge(clk_100m_sys) then
if(rst_n_sys = '0') then
spec_led <= "01111111";
led_divider <= (others => '0');
else
led_divider <= led_divider+ 1;
if(led_divider = 0) then
spec_led <= spec_led(6 downto 0) & spec_led(7);
end if;
end if;
end if;
end process;
led_green_o <= spec_led(7);
led_red_o <= not rst_n_sys;
end rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
--------------------------------------------------------------------------------------------------
\ No newline at end of file
......@@ -68,32 +68,23 @@ class fmcmasterfip:
# Carrier specific components
#------------------------------------
# Carrier CSR address
# TODO: recreate
CARRIER_CSR_ADDR = 0x00001200
# Carrier One Wire
CARR_ONEWIRE_ADDR = 0x00001100
CROSSBAR_MAIN = 0x20000
CROSSBAR_MAIN = 0x10000
#------------------------------------
# MasterFIP FMC address
# eeprom
# TODO: recreate
MASTERFIP_I2C_EEPROM = CROSSBAR_MAIN + 0x1000
# ADC configuration
MASTERFIP_SPI_ADC = CROSSBAR_MAIN + 0x1100
# SI570 configuration (not mount)
MASTERFIP_I2C_SI570 = CROSSBAR_MAIN + 0x1200
# ADC core registers
MASTERFIP_CSR_ADC = CROSSBAR_MAIN + 0x1300
# Thermometer
MASTERFIP_OW_THERM = CROSSBAR_MAIN + 0x1400
# Masterfip core registers
MASTERFIP_CORE_ADDR = CROSSBAR_MAIN + 0x8000
SAMPLING_FREQ_ADDR_IN_BINARY_DATA = 72;
# Masterfip core registers
MASTERFIP_CORE_ADDR = 0x10000
freq_options = [ 31250, 1e6, 25e5, 5e6 ]
adc_sampling_freq = 100e6
###############################################################################################
......@@ -118,10 +109,6 @@ class fmcmasterfip:
###################################################################
# creation of interfaces to modules controlling external devices
self.carr_onewire = ow.COpenCoresOneWire(self.carrier, self.CARR_ONEWIRE_ADDR, 199, 39) #for 40 MHz clock
self.carr_ds18b20 = ds18b20.CDS18B20(self.carr_onewire, 0)
self.fmc_onewire = ow.COpenCoresOneWire(self.carrier, self.MASTERFIP_OW_THERM, 499, 99) #for 40 MHz clock
self.fmc_ds18b20 = ds18b20.CDS18B20(self.fmc_onewire, 0)
......@@ -136,7 +123,7 @@ class fmcmasterfip:
###################### firmware initialization ####################
###################################################################
self.verify_bitstream_type();
self.verify_carrier_status();
# self.verify_carrier_status();
self.rst_core()
time.sleep(0.5)
......
......@@ -2,7 +2,7 @@
#
# * File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/python/regs/carrier_addrtable.py
# * Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/carrier_csr.wb
# * Created : Tue Mar 7 12:59:04 2017
# * Created : Wed Mar 15 14:47:52 2017
#
# THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/carrier_csr.wb
# DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
......
......@@ -2,7 +2,7 @@
#
# * File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/python/regs/masterfip_addrtable.py
# * Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/fmc_masterfip_csr.wb
# * Created : Tue Mar 7 12:59:02 2017
# * Created : Wed Mar 15 14:47:50 2017
#
# THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/fmc_masterfip_csr.wb
# DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
......
This source diff could not be displayed because it is too large. You can view the blob instead.
# Register definitions for slave core: FMC masterFIP core registers
#
# * File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/python/regs/masterfip_csr.py
# * Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/ip_cores/gw-masterfip/rtl/wbgen/masterfip_csr.wb
# * Created : Wed Mar 15 14:47:52 2017
#
# THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/ip_cores/gw-masterfip/rtl/wbgen/masterfip_csr.wb
# DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
#
addr = {
'rst' : [ 0x0, 0xffffffff, "w"],
'rst.core' : [ 0x0, 0x1, "w"],
'rst.fd' : [ 0x0, 0x2, "w"],
'id' : [ 0x1, 0xffffffff, "r"],
'led' : [ 0x2, 0xffffffff, "rw"],
'led.rx_act' : [ 0x2, 0x1, "rw"],
'led.rx_err' : [ 0x2, 0x2, "rw"],
'led.tx_act' : [ 0x2, 0x4, "rw"],
'led.tx_err' : [ 0x2, 0x8, "rw"],
'led.ext_sync_used' : [ 0x2, 0x10, "rw"],
'led.ext_sync_act' : [ 0x2, 0x20, "rw"],
'led.ext_sync_err' : [ 0x2, 0x40, "rw"],
'led.dbg' : [ 0x2, 0xFFFFFF00, "rw"],
'ds1820_temper' : [ 0x3, 0xffffffff, "r"],
'ds1820_id_lsb' : [ 0x4, 0xffffffff, "r"],
'ds1820_id_msb' : [ 0x5, 0xffffffff, "r"],
'ext_sync_ctrl' : [ 0x6, 0xffffffff, "rw"],
'ext_sync_ctrl.term_en' : [ 0x6, 0x1, "rw"],
'ext_sync_ctrl.dir' : [ 0x6, 0x2, "rw"],
'ext_sync_ctrl.oe_n' : [ 0x6, 0x4, "rw"],
'ext_sync_ctrl.p_cnt_rst' : [ 0x6, 0x100, "rw"],
'ext_sync_p_cnt' : [ 0x7, 0xffffffff, "r"],
'speed' : [ 0x8, 0xffffffff, "r"],
'macrocyc' : [ 0x9, 0xffffffff, "rw"],
'macrocyc.lgth' : [ 0x9, 0x7FFFFFFF, "rw"],
'macrocyc.start' : [ 0x9, 0x80000000, "rw"],
'macrocyc_time_cnt' : [ 0xA, 0xffffffff, "r"],
'macrocyc_num_cnt' : [ 0xB, 0xffffffff, "r"],
'turnar' : [ 0xC, 0xffffffff, "rw"],
'turnar.lgth' : [ 0xC, 0x7FFFFFFF, "rw"],
'turnar.start' : [ 0xC, 0x80000000, "rw"],
'turnar_time_cnt' : [ 0xD, 0xffffffff, "r"],
'silen' : [ 0xE, 0xffffffff, "rw"],
'silen.lgth' : [ 0xE, 0x7FFFFFFF, "rw"],
'silen.start' : [ 0xE, 0x80000000, "rw"],
'silen_time_cnt' : [ 0xF, 0xffffffff, "r"],
'tx_ctrl' : [ 0x10, 0xffffffff, "rw"],
'tx_ctrl.rst' : [ 0x10, 0x1, "rw"],
'tx_ctrl.start' : [ 0x10, 0x2, "rw"],
'tx_ctrl.bytes_num' : [ 0x10, 0x1FF00, "rw"],
'tx_stat' : [ 0x11, 0xffffffff, "r"],
'tx_stat.stop' : [ 0x11, 0x1, "r"],
'tx_stat.ena' : [ 0x11, 0x100, "r"],
'tx_stat.curr_byte_indx' : [ 0x11, 0x3FE00, "r"],
'fd' : [ 0x12, 0xffffffff, "r"],
'fd.wdg' : [ 0x12, 0x1, "r"],
'fd.cd' : [ 0x12, 0x2, "r"],
'fd_wdg_tstamp' : [ 0x13, 0xffffffff, "r"],
'fd_txer_cnt' : [ 0x14, 0xffffffff, "r"],
'fd_txer_tstamp' : [ 0x15, 0xffffffff, "r"],
'rx_ctrl' : [ 0x16, 0xffffffff, "rw"],
'rx_stat' : [ 0x17, 0xffffffff, "r"],
'rx_stat.pream_ok' : [ 0x17, 0x1, "r"],
'rx_stat.frame_ok' : [ 0x17, 0x2, "r"],
'rx_stat.frame_crc_err' : [ 0x17, 0x4, "r"],
'rx_stat.bytes_num' : [ 0x17, 0x1FF00, "r"],
'rx_stat_curr_word_indx' : [ 0x18, 0xffffffff, "r"],
'rx_stat_crc_err_cnt' : [ 0x19, 0xffffffff, "r"],
'rx_payld_ctrl' : [ 0x1A, 0xffffffff, "r"],
'rx_payld_reg1' : [ 0x1B, 0xffffffff, "r"],
'rx_payld_reg2' : [ 0x1C, 0xffffffff, "r"],
'rx_payld_reg3' : [ 0x1D, 0xffffffff, "r"],
'rx_payld_reg4' : [ 0x1E, 0xffffffff, "r"],
'rx_payld_reg5' : [ 0x1F, 0xffffffff, "r"],
'rx_payld_reg6' : [ 0x20, 0xffffffff, "r"],
'rx_payld_reg7' : [ 0x21, 0xffffffff, "r"],
'rx_payld_reg8' : [ 0x22, 0xffffffff, "r"],
'rx_payld_reg9' : [ 0x23, 0xffffffff, "r"],
'rx_payld_reg10' : [ 0x24, 0xffffffff, "r"],
'rx_payld_reg11' : [ 0x25, 0xffffffff, "r"],
'rx_payld_reg12' : [ 0x26, 0xffffffff, "r"],
'rx_payld_reg13' : [ 0x27, 0xffffffff, "r"],
'rx_payld_reg14' : [ 0x28, 0xffffffff, "r"],
'rx_payld_reg15' : [ 0x29, 0xffffffff, "r"],
'rx_payld_reg16' : [ 0x2A, 0xffffffff, "r"],
'rx_payld_reg17' : [ 0x2B, 0xffffffff, "r"],
'rx_payld_reg18' : [ 0x2C, 0xffffffff, "r"],
'rx_payld_reg19' : [ 0x2D, 0xffffffff, "r"],
'rx_payld_reg20' : [ 0x2E, 0xffffffff, "r"],
'rx_payld_reg21' : [ 0x2F, 0xffffffff, "r"],
'rx_payld_reg22' : [ 0x30, 0xffffffff, "r"],
'rx_payld_reg23' : [ 0x31, 0xffffffff, "r"],
'rx_payld_reg24' : [ 0x32, 0xffffffff, "r"],
'rx_payld_reg25' : [ 0x33, 0xffffffff, "r"],
'rx_payld_reg26' : [ 0x34, 0xffffffff, "r"],
'rx_payld_reg27' : [ 0x35, 0xffffffff, "r"],
'rx_payld_reg28' : [ 0x36, 0xffffffff, "r"],
'rx_payld_reg29' : [ 0x37, 0xffffffff, "r"],
'rx_payld_reg30' : [ 0x38, 0xffffffff, "r"],
'rx_payld_reg31' : [ 0x39, 0xffffffff, "r"],
'rx_payld_reg32' : [ 0x3A, 0xffffffff, "r"],
'rx_payld_reg33' : [ 0x3B, 0xffffffff, "r"],
'rx_payld_reg34' : [ 0x3C, 0xffffffff, "r"],
'rx_payld_reg35' : [ 0x3D, 0xffffffff, "r"],
'rx_payld_reg36' : [ 0x3E, 0xffffffff, "r"],
'rx_payld_reg37' : [ 0x3F, 0xffffffff, "r"],
'rx_payld_reg38' : [ 0x40, 0xffffffff, "r"],
'rx_payld_reg39' : [ 0x41, 0xffffffff, "r"],
'rx_payld_reg40' : [ 0x42, 0xffffffff, "r"],
'rx_payld_reg41' : [ 0x43, 0xffffffff, "r"],
'rx_payld_reg42' : [ 0x44, 0xffffffff, "r"],
'rx_payld_reg43' : [ 0x45, 0xffffffff, "r"],
'rx_payld_reg44' : [ 0x46, 0xffffffff, "r"],
'rx_payld_reg45' : [ 0x47, 0xffffffff, "r"],
'rx_payld_reg46' : [ 0x48, 0xffffffff, "r"],
'rx_payld_reg47' : [ 0x49, 0xffffffff, "r"],
'rx_payld_reg48' : [ 0x4A, 0xffffffff, "r"],
'rx_payld_reg49' : [ 0x4B, 0xffffffff, "r"],
'rx_payld_reg50' : [ 0x4C, 0xffffffff, "r"],
'rx_payld_reg51' : [ 0x4D, 0xffffffff, "r"],
'rx_payld_reg52' : [ 0x4E, 0xffffffff, "r"],
'rx_payld_reg53' : [ 0x4F, 0xffffffff, "r"],
'rx_payld_reg54' : [ 0x50, 0xffffffff, "r"],
'rx_payld_reg55' : [ 0x51, 0xffffffff, "r"],
'rx_payld_reg56' : [ 0x52, 0xffffffff, "r"],
'rx_payld_reg57' : [ 0x53, 0xffffffff, "r"],
'rx_payld_reg58' : [ 0x54, 0xffffffff, "r"],
'rx_payld_reg59' : [ 0x55, 0xffffffff, "r"],
'rx_payld_reg60' : [ 0x56, 0xffffffff, "r"],
'rx_payld_reg61' : [ 0x57, 0xffffffff, "r"],
'rx_payld_reg62' : [ 0x58, 0xffffffff, "r"],
'rx_payld_reg63' : [ 0x59, 0xffffffff, "r"],
'rx_payld_reg64' : [ 0x5A, 0xffffffff, "r"],
'rx_payld_reg65' : [ 0x5B, 0xffffffff, "r"],
'rx_payld_reg66' : [ 0x5C, 0xffffffff, "r"],
'rx_payld_reg67' : [ 0x5D, 0xffffffff, "r"],
'tx_payld_ctrl' : [ 0x5E, 0xffffffff, "rw"],
'tx_payld_reg1' : [ 0x5F, 0xffffffff, "rw"],
'tx_payld_reg2' : [ 0x60, 0xffffffff, "rw"],
'tx_payld_reg3' : [ 0x61, 0xffffffff, "rw"],
'tx_payld_reg4' : [ 0x62, 0xffffffff, "rw"],
'tx_payld_reg5' : [ 0x63, 0xffffffff, "rw"],
'tx_payld_reg6' : [ 0x64, 0xffffffff, "rw"],
'tx_payld_reg7' : [ 0x65, 0xffffffff, "rw"],
'tx_payld_reg8' : [ 0x66, 0xffffffff, "rw"],
'tx_payld_reg9' : [ 0x67, 0xffffffff, "rw"],
'tx_payld_reg10' : [ 0x68, 0xffffffff, "rw"],
'tx_payld_reg11' : [ 0x69, 0xffffffff, "rw"],
'tx_payld_reg12' : [ 0x6A, 0xffffffff, "rw"],
'tx_payld_reg13' : [ 0x6B, 0xffffffff, "rw"],
'tx_payld_reg14' : [ 0x6C, 0xffffffff, "rw"],
'tx_payld_reg15' : [ 0x6D, 0xffffffff, "rw"],
'tx_payld_reg16' : [ 0x6E, 0xffffffff, "rw"],
'tx_payld_reg17' : [ 0x6F, 0xffffffff, "rw"],
'tx_payld_reg18' : [ 0x70, 0xffffffff, "rw"],
'tx_payld_reg19' : [ 0x71, 0xffffffff, "rw"],
'tx_payld_reg20' : [ 0x72, 0xffffffff, "rw"],
'tx_payld_reg21' : [ 0x73, 0xffffffff, "rw"],
'tx_payld_reg22' : [ 0x74, 0xffffffff, "rw"],
'tx_payld_reg23' : [ 0x75, 0xffffffff, "rw"],
'tx_payld_reg24' : [ 0x76, 0xffffffff, "rw"],
'tx_payld_reg25' : [ 0x77, 0xffffffff, "rw"],
'tx_payld_reg26' : [ 0x78, 0xffffffff, "rw"],
'tx_payld_reg27' : [ 0x79, 0xffffffff, "rw"],
'tx_payld_reg28' : [ 0x7A, 0xffffffff, "rw"],
'tx_payld_reg29' : [ 0x7B, 0xffffffff, "rw"],
'tx_payld_reg30' : [ 0x7C, 0xffffffff, "rw"],
'tx_payld_reg31' : [ 0x7D, 0xffffffff, "rw"],
'tx_payld_reg32' : [ 0x7E, 0xffffffff, "rw"],
'tx_payld_reg33' : [ 0x7F, 0xffffffff, "rw"],
'tx_payld_reg34' : [ 0x80, 0xffffffff, "rw"],
'tx_payld_reg35' : [ 0x81, 0xffffffff, "rw"],
'tx_payld_reg36' : [ 0x82, 0xffffffff, "rw"],
'tx_payld_reg37' : [ 0x83, 0xffffffff, "rw"],
'tx_payld_reg38' : [ 0x84, 0xffffffff, "rw"],
'tx_payld_reg39' : [ 0x85, 0xffffffff, "rw"],
'tx_payld_reg40' : [ 0x86, 0xffffffff, "rw"],
'tx_payld_reg41' : [ 0x87, 0xffffffff, "rw"],
'tx_payld_reg42' : [ 0x88, 0xffffffff, "rw"],
'tx_payld_reg43' : [ 0x89, 0xffffffff, "rw"],
'tx_payld_reg44' : [ 0x8A, 0xffffffff, "rw"],
'tx_payld_reg45' : [ 0x8B, 0xffffffff, "rw"],
'tx_payld_reg46' : [ 0x8C, 0xffffffff, "rw"],
'tx_payld_reg47' : [ 0x8D, 0xffffffff, "rw"],
'tx_payld_reg48' : [ 0x8E, 0xffffffff, "rw"],
'tx_payld_reg49' : [ 0x8F, 0xffffffff, "rw"],
'tx_payld_reg50' : [ 0x90, 0xffffffff, "rw"],
'tx_payld_reg51' : [ 0x91, 0xffffffff, "rw"],
'tx_payld_reg52' : [ 0x92, 0xffffffff, "rw"],
'tx_payld_reg53' : [ 0x93, 0xffffffff, "rw"],
'tx_payld_reg54' : [ 0x94, 0xffffffff, "rw"],
'tx_payld_reg55' : [ 0x95, 0xffffffff, "rw"],
'tx_payld_reg56' : [ 0x96, 0xffffffff, "rw"],
'tx_payld_reg57' : [ 0x97, 0xffffffff, "rw"],
'tx_payld_reg58' : [ 0x98, 0xffffffff, "rw"],
'tx_payld_reg59' : [ 0x99, 0xffffffff, "rw"],
'tx_payld_reg60' : [ 0x9A, 0xffffffff, "rw"],
'tx_payld_reg61' : [ 0x9B, 0xffffffff, "rw"],
'tx_payld_reg62' : [ 0x9C, 0xffffffff, "rw"],
'tx_payld_reg63' : [ 0x9D, 0xffffffff, "rw"],
'tx_payld_reg64' : [ 0x9E, 0xffffffff, "rw"],
'tx_payld_reg65' : [ 0x9F, 0xffffffff, "rw"],
'tx_payld_reg66' : [ 0xA0, 0xffffffff, "rw"],
'tx_payld_reg67' : [ 0xA1, 0xffffffff, "rw"],
'':[0,0]
}
......@@ -27,4 +27,11 @@ top=`echo "$prg" | sed 's/fmcmasterfip\/.*/fmcmasterfip/'`
-P "$top/python/regs/carrier_addrtable.py" \
"$top/gateware/rtl/wbgen/carrier_csr.wb"
"$top/scripts/wbgen2" \
-D "$top/python/regs/masterfip_csr.htm" \
-P "$top/python/regs/masterfip_csr.py" \
-l vhdl \
-V "$top/gateware/rtl/wbgen/masterfip_csr.vhd" \
"$top/gateware/ip_cores/gw-masterfip/rtl/wbgen/masterfip_csr.wb"
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