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MasterFIP - Testing
Commit 39f4f710 authored by Marek Gumiński's avatar Marek Gumiński
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Removed ununed files and comments in vhdl files

parent caef7287
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Showing with 23 additions and 3019 deletions
gateware/syn/spec/spec_fmc_masterfip_pts.xise
View file @ 39f4f710
......@@ -501,7 +501,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/fmc-adc-100m14b4cha-gw/hdl/adc/rtl/fmc_adc_mezzanine_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="102"/>
<association xil_pn:name="Implementation" xil_pn:seqID="101"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
......@@ -594,7 +594,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../top/spec/spec_top_fmc_masterfip.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="104"/>
<association xil_pn:name="Implementation" xil_pn:seqID="103"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -603,7 +603,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="84"/>
</file>
<file xil_pn:name="../../rtl/fmc_masterfip_mezzanine.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="99"/>
<association xil_pn:name="Implementation" xil_pn:seqID="98"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -663,7 +663,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="100"/>
<association xil_pn:name="Implementation" xil_pn:seqID="99"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="82"/>
......@@ -696,7 +696,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="95"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="101"/>
<association xil_pn:name="Implementation" xil_pn:seqID="100"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="86"/>
......@@ -774,7 +774,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../top/spec/dma_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="97"/>
<association xil_pn:name="Implementation" xil_pn:seqID="96"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -810,7 +810,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="77"/>
</file>
<file xil_pn:name="../../top/spec/sdb_meta_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="96"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -861,7 +861,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="103"/>
<association xil_pn:name="Implementation" xil_pn:seqID="102"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="89"/>
......@@ -876,7 +876,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../../top/spec/carrier_csr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="98"/>
<association xil_pn:name="Implementation" xil_pn:seqID="97"/>
</file>
<file xil_pn:name="../../rtl/fmc_masterFIP_core_pts.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="73"/>
......
gateware/top/1:fmc-masterfip-EDA-03098-V1-3 deleted 100644 → 0
View file @ caef7287
masterfip_speed_b[0] : in std_logic;
masterfip_speed_b[1] : in std_logic;
masterfip_adc_outa_p[3] : in std_logic;
masterfip_adc_outa_n[3] : in std_logic;
masterfip_adc_outa_p[1] : in std_logic;
masterfip_adc_outa_n[1] : in std_logic;
masterfip_c2m_adc_clk_p : in std_logic;
masterfip_c2m_adc_clk_n : in std_logic;
masterfip_gbt_adc_clk_p : in std_logic;
masterfip_gbt_adc_clk_n : in std_logic;
masterfip_adc_outb_p[4] : in std_logic;
masterfip_adc_outb_n[4] : in std_logic;
masterfip_adc_outb_p[3] : in std_logic;
masterfip_adc_outb_n[3] : in std_logic;
masterfip_adc_outb_p[2] : in std_logic;
masterfip_adc_outb_n[2] : in std_logic;
masterfip_term_en_n : in std_logic;
masterfip_ext_sync_term_en : in std_logic;
masterfip_test_point[1] : in std_logic;
masterfip_test_point[2] : in std_logic;
masterfip_test_point[3] : in std_logic;
masterfip_test_point[4] : in std_logic;
masterfip_adc_fr_n : in std_logic;
masterfip_adc_fr_p : in std_logic;
masterfip_sec_conn_n : in std_logic;
masterfip_5v_en_n : in std_logic;
masterfip_adc_out2a_p : in std_logic;
masterfip_adc_out2a_n : in std_logic;
masterfip_fd_wdg_n : in std_logic;
masterfip_fd_txer : in std_logic;
masterfip_fd_txena : in std_logic;
masterfip_fd_txd : in std_logic;
masterfip_fd_cd_n : in std_logic;
masterfip_fd_rxd : in std_logic;
masterfip_fd_txck : in std_logic;
masterfip_fd_rst_n : in std_logic;
masterfip_one_wire : in std_logic;
masterfip_tx_err_led_n : in std_logic;
masterfip_tx_act_led_n : in std_logic;
masterfip_adc_dco_n : in std_logic;
masterfip_adc_dco_p : in std_logic;
masterfip_prim_conn_n : in std_logic;
masterfip_ext_sync : in std_logic;
masterfip_ext_sync_tst_n : in std_logic;
masterfip_adc_out4a_p : in std_logic;
masterfip_adc_out4a_n : in std_logic;
masterfip_sync_led_n : in std_logic;
masterfip_out_of_sync_led_ : in std_logic;
masterfip_adc_out1b_p : in std_logic;
masterfip_adc_out1b_n : in std_logic;
masterfip_si570_oe : in std_logic;
masterfip_si570_sda : in std_logic;
masterfip_si570_scl : in std_logic;
masterfip_adc_cs : in std_logic;
masterfip_adc_sck : in std_logic;
masterfip_adc_sdi : in std_logic;
masterfip_adc_sdo : in std_logic;
masterfip_1v8_shdn_n : in std_logic;
masterfip_m5v_shdn_n : in std_logic;
masterfip_rx_err_led_n : in std_logic;
masterfip_rx_act_led_n : in std_logic;
masterfip_ext_sync_oe : in std_logic;
masterfip_ext_sync_dir : in std_logic;
# <ucfgen_start>
# This section has bee generated automatically by ucfgen.py. Do not hand-modify if not really necessary.
# ucfgen pin assignments for mezzanine fmc-masterfip-EDA-03098-V1-3 slot 0
NET "masterfip_speed_b[0]" LOC = "Y5";
NET "masterfip_speed_b[0]" IOSTANDARD = "LVCMOS25";
NET "masterfip_speed_b[1]" LOC = "AB5";
NET "masterfip_speed_b[1]" IOSTANDARD = "LVCMOS25";
NET "masterfip_adc_outa_p[3]" LOC = "AA8";
NET "masterfip_adc_outa_p[3]" IOSTANDARD = "LVCMOS25";
NET "masterfip_adc_outa_n[3]" LOC = "AB8";
NET "masterfip_adc_outa_n[3]" IOSTANDARD = "LVCMOS25";
NET "masterfip_adc_outa_p[1]" LOC = "AA4";
NET "masterfip_adc_outa_p[1]" IOSTANDARD = "LVCMOS25";
NET "masterfip_adc_outa_n[1]" LOC = "AB4";
NET "masterfip_adc_outa_n[1]" IOSTANDARD = "LVCMOS25";
NET "masterfip_c2m_adc_clk_p" LOC = "T12";
NET "masterfip_c2m_adc_clk_p" IOSTANDARD = "LVCMOS25";
NET "masterfip_c2m_adc_clk_n" LOC = "U12";
NET "masterfip_c2m_adc_clk_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_gbt_adc_clk_p" LOC = "B6";
NET "masterfip_gbt_adc_clk_p" IOSTANDARD = "LVDS_25";
NET "masterfip_gbt_adc_clk_n" LOC = "A6";
NET "masterfip_gbt_adc_clk_n" IOSTANDARD = "LVDS_25";
NET "masterfip_adc_outb_p[4]" LOC = "AA6";
NET "masterfip_adc_outb_p[4]" IOSTANDARD = "LVDS_25";
NET "masterfip_adc_outb_n[4]" LOC = "AB6";
NET "masterfip_adc_outb_n[4]" IOSTANDARD = "LVDS_25";
NET "masterfip_adc_outb_p[3]" LOC = "Y7";
NET "masterfip_adc_outb_p[3]" IOSTANDARD = "LVDS_25";
NET "masterfip_adc_outb_n[3]" LOC = "AB7";
NET "masterfip_adc_outb_n[3]" IOSTANDARD = "LVDS_25";
NET "masterfip_adc_outb_p[2]" LOC = "Y9";
NET "masterfip_adc_outb_p[2]" IOSTANDARD = "LVDS_25";
NET "masterfip_adc_outb_n[2]" LOC = "AB9";
NET "masterfip_adc_outb_n[2]" IOSTANDARD = "LVDS_25";
NET "masterfip_term_en_n" LOC = "Y13";
NET "masterfip_term_en_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_ext_sync_term_en" LOC = "AB13";
NET "masterfip_ext_sync_term_en" IOSTANDARD = "LVCMOS25";
NET "masterfip_test_point[1]" LOC = "AA16";
NET "masterfip_test_point[1]" IOSTANDARD = "LVCMOS25";
NET "masterfip_test_point[2]" LOC = "AB16";
NET "masterfip_test_point[2]" IOSTANDARD = "LVCMOS25";
NET "masterfip_test_point[3]" LOC = "Y17";
NET "masterfip_test_point[3]" IOSTANDARD = "LVCMOS25";
NET "masterfip_test_point[4]" LOC = "AB17";
NET "masterfip_test_point[4]" IOSTANDARD = "LVCMOS25";
NET "masterfip_adc_fr_n" LOC = "AA12";
NET "masterfip_adc_fr_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_adc_fr_p" LOC = "AB12";
NET "masterfip_adc_fr_p" IOSTANDARD = "LVCMOS25";
NET "masterfip_sec_conn_n" LOC = "W8";
NET "masterfip_sec_conn_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_5v_en_n" LOC = "R8";
NET "masterfip_5v_en_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_adc_out2a_p" LOC = "W12";
NET "masterfip_adc_out2a_p" IOSTANDARD = "LVDS_25";
NET "masterfip_adc_out2a_n" LOC = "Y12";
NET "masterfip_adc_out2a_n" IOSTANDARD = "LVDS_25";
NET "masterfip_fd_wdg_n" LOC = "R11";
NET "masterfip_fd_wdg_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_fd_txer" LOC = "T11";
NET "masterfip_fd_txer" IOSTANDARD = "LVCMOS25";
NET "masterfip_fd_txena" LOC = "R13";
NET "masterfip_fd_txena" IOSTANDARD = "LVCMOS25";
NET "masterfip_fd_txd" LOC = "T14";
NET "masterfip_fd_txd" IOSTANDARD = "LVCMOS25";
NET "masterfip_fd_cd_n" LOC = "T15";
NET "masterfip_fd_cd_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_fd_rxd" LOC = "U15";
NET "masterfip_fd_rxd" IOSTANDARD = "LVCMOS25";
NET "masterfip_fd_txck" LOC = "W17";
NET "masterfip_fd_txck" IOSTANDARD = "LVCMOS25";
NET "masterfip_fd_rst_n" LOC = "Y18";
NET "masterfip_fd_rst_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_one_wire" LOC = "D7";
NET "masterfip_one_wire" IOSTANDARD = "LVCMOS25";
NET "masterfip_tx_err_led_n" LOC = "C18";
NET "masterfip_tx_err_led_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_tx_act_led_n" LOC = "C19";
NET "masterfip_tx_act_led_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_adc_dco_n" LOC = "Y11";
NET "masterfip_adc_dco_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_adc_dco_p" LOC = "AB11";
NET "masterfip_adc_dco_p" IOSTANDARD = "LVCMOS25";
NET "masterfip_prim_conn_n" LOC = "V7";
NET "masterfip_prim_conn_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_ext_sync" LOC = "T8";
NET "masterfip_ext_sync" IOSTANDARD = "LVCMOS25";
NET "masterfip_ext_sync_tst_n" LOC = "U8";
NET "masterfip_ext_sync_tst_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_adc_out4a_p" LOC = "U9";
NET "masterfip_adc_out4a_p" IOSTANDARD = "LVCMOS25";
NET "masterfip_adc_out4a_n" LOC = "V9";
NET "masterfip_adc_out4a_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_sync_led_n" LOC = "W10";
NET "masterfip_sync_led_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_out_of_sync_led_" LOC = "Y10";
NET "masterfip_out_of_sync_led_" IOSTANDARD = "LVCMOS25";
NET "masterfip_adc_out1b_p" LOC = "V11";
NET "masterfip_adc_out1b_p" IOSTANDARD = "LVCMOS25";
NET "masterfip_adc_out1b_n" LOC = "W11";
NET "masterfip_adc_out1b_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_si570_oe" LOC = "AB15";
NET "masterfip_si570_oe" IOSTANDARD = "LVCMOS25";
NET "masterfip_si570_sda" LOC = "V13";
NET "masterfip_si570_sda" IOSTANDARD = "LVCMOS25";
NET "masterfip_si570_scl" LOC = "W13";
NET "masterfip_si570_scl" IOSTANDARD = "LVCMOS25";
NET "masterfip_adc_cs" LOC = "W14";
NET "masterfip_adc_cs" IOSTANDARD = "LVCMOS25";
NET "masterfip_adc_sck" LOC = "Y14";
NET "masterfip_adc_sck" IOSTANDARD = "LVCMOS25";
NET "masterfip_adc_sdi" LOC = "Y16";
NET "masterfip_adc_sdi" IOSTANDARD = "LVCMOS25";
NET "masterfip_adc_sdo" LOC = "W15";
NET "masterfip_adc_sdo" IOSTANDARD = "LVCMOS25";
NET "masterfip_1v8_shdn_n" LOC = "V17";
NET "masterfip_1v8_shdn_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_m5v_shdn_n" LOC = "W18";
NET "masterfip_m5v_shdn_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_rx_err_led_n" LOC = "B20";
NET "masterfip_rx_err_led_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_rx_act_led_n" LOC = "A20";
NET "masterfip_rx_act_led_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_ext_sync_oe" LOC = "W6";
NET "masterfip_ext_sync_oe" IOSTANDARD = "LVCMOS25";
NET "masterfip_ext_sync_dir" LOC = "Y6";
NET "masterfip_ext_sync_dir" IOSTANDARD = "LVCMOS25";
# <ucfgen_end>
gateware/top/ports deleted 100644 → 0
View file @ caef7287
masterfip_speed_b[0] : in std_logic;
masterfip_speed_b[1] : in std_logic;
masterfip_adc_outa_p[3] : in std_logic;
masterfip_adc_outa_n[3] : in std_logic;
masterfip_adc_outa_p[1] : in std_logic;
masterfip_adc_outa_n[1] : in std_logic;
masterfip_c2m_adc_clk_p : out std_logic;
masterfip_c2m_adc_clk_n : out std_logic;
masterfip_gbt_adc_clk_p : out std_logic;
masterfip_gbt_adc_clk_n : out std_logic;
masterfip_adc_outb_p[4] : in std_logic;
masterfip_adc_outb_n[4] : in std_logic;
masterfip_adc_outb_p[3] : in std_logic;
masterfip_adc_outb_n[3] : in std_logic;
masterfip_adc_outb_p[2] : in std_logic;
masterfip_adc_outb_n[2] : in std_logic;
masterfip_term_en_n : out std_logic;
masterfip_ext_sync_term_en : out std_logic;
masterfip_test_point[1] : in std_logic;
masterfip_test_point[2] : in std_logic;
masterfip_test_point[3] : in std_logic;
masterfip_test_point[4] : in std_logic;
masterfip_adc_fr_n : in std_logic;
masterfip_adc_fr_p : in std_logic;
masterfip_sec_conn_n : out std_logic;
masterfip_5v_en_n : out std_logic;
masterfip_adc_out2a_p : in std_logic;
masterfip_adc_out2a_n : in std_logic;
masterfip_fd_wdg_n : in std_logic;
masterfip_fd_txer : in std_logic;
masterfip_fd_txena : out std_logic;
masterfip_fd_txd : out std_logic;
masterfip_fd_cd_n : in std_logic;
masterfip_fd_rxd : in std_logic;
masterfip_fd_txck : out std_logic;
masterfip_fd_rst_n : out std_logic;
masterfip_one_wire : inout std_logic;
masterfip_tx_err_led_n : out std_logic;
masterfip_tx_act_led_n : out std_logic;
masterfip_adc_dco_n : in std_logic;
masterfip_adc_dco_p : in std_logic;
masterfip_prim_conn_n : out std_logic;
masterfip_ext_sync : inout std_logic;
masterfip_ext_sync_tst_n : out std_logic;
masterfip_adc_out4a_p : in std_logic;
masterfip_adc_out4a_n : in std_logic;
masterfip_sync_led_n : out std_logic;
masterfip_out_of_sync_led_ : out std_logic;
masterfip_adc_out1b_p : in std_logic;
masterfip_adc_out1b_n : in std_logic;
masterfip_si570_oe : out std_logic;
masterfip_si570_sda : inout std_logic;
masterfip_si570_scl : out std_logic;
masterfip_adc_cs : out std_logic;
masterfip_adc_sck : out std_logic;
masterfip_adc_sdi : in std_logic;
masterfip_adc_sdo : out std_logic;
masterfip_1v8_shdn_n : out std_logic;
masterfip_m5v_shdn_n : out std_logic;
masterfip_rx_err_led_n : out std_logic;
masterfip_rx_act_led_n : out std_logic;
masterfip_ext_sync_oe : out std_logic;
masterfip_ext_sync_dir : out std_logic;
gateware/top/spec/sdb_meta_pkg.vhd
View file @ 39f4f710
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- FMC ADC 100Ms/s core
-- http://www.ohwr.org/projects/fmc-adc-100m14b4cha
--------------------------------------------------------------------------------
--
-- unit name: sdb_meta_pkg (sdb_meta_pkg.vhd)
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 11-03-2013
--
-- description: Sdb meta-information for the FMC ADC 100Ms/s design for SPEC.
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see git log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
-- Modified manually
library ieee;
use ieee.std_logic_1164.all;
......@@ -46,23 +15,23 @@ package sdb_meta_pkg is
-- Top module repository url
constant c_repo_url_sdb : t_sdb_repo_url := (
-- url (string, 63 char)
repo_url => "git://ohwr.org/fmc-projects/fmc-adc-100m14b4cha.git ");
repo_url => "git@ohwr.org:cern-fip/masterfip/masterfip-tst.git ");
-- Synthesis informations
constant c_synthesis_sdb : t_sdb_synthesis := (
-- Top module name (string, 16 char)
syn_module_name => "spec_top_fmc_adc",
syn_module_name => "spec_top_fmc_masterfip",
-- Commit ID (hex string, 128-bit = 32 char)
-- git log -1 --format="%H" | cut -c1-32
syn_commit_id => "26749f0a1873c215abb33942a8a335db",
syn_commit_id => "000000000000000000000000000000",
-- Synthesis tool name (string, 8 char)
syn_tool_name => "ISE ",
-- Synthesis tool version (bcd encoded, 32-bit)
syn_tool_version => x"00000133",
-- Synthesis date (bcd encoded, 32-bit, yyyymmdd)
syn_date => x"20140425",
syn_date => x"20160701",
-- Synthesised by (string, 15 char)
syn_username => "mcattin ");
syn_username => "mguminsk ");
-- Integration record
constant c_integration_sdb : t_sdb_integration := (
......@@ -71,7 +40,7 @@ package sdb_meta_pkg is
device_id => x"47c786a2", -- echo "spec_fmc-adc-100m14b4cha" | md5sum | cut -c1-8
version => x"00040000", -- bcd encoded, [31:16] = major, [15:0] = minor
date => x"20140425", -- yyyymmdd
name => "spec_fmcadc100m14b "));
name => "spec_fmcmasterfip "));
end sdb_meta_pkg;
......
gateware/top/spec/spec_masterfip.ucf deleted 100644 → 0
View file @ caef7287
#----------------------------------------
# Clocks
#----------------------------------------
NET "clk_20m_vcxo_i" LOC = H12;
NET "clk_20m_vcxo_i" IOSTANDARD = "LVCMOS25";
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo_i";
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
NET "p2l_clk_n_i" LOC = M19;
NET "p2l_clk_n_i" IOSTANDARD = "DIFF_SSTL18_I";
NET "p2l_clk_p_i" LOC = M20;
NET "p2l_clk_p_i" IOSTANDARD = "DIFF_SSTL18_I";
NET "p2l_clk_p_i" TNM_NET = "p2l_clk_p_i";
TIMESPEC TS_p2l_clk_p_i = PERIOD "p2l_clk_p_i" 5 ns HIGH 50%;
NET "p2l_clk_n_i" TNM_NET = "p2l_clk_n_i";
TIMESPEC TS_p2l_clk_n_i = PERIOD "p2l_clk_n_i" 5 ns HIGH 50%;
#----------------------------------------
# FMC slot
#----------------------------------------
NET "fd_rstn_o" LOC = "Y18";
NET "fd_rstn_o" IOSTANDARD = "LVCMOS25";
NET "fd_txd_o" LOC = "T14";
NET "fd_txd_o" IOSTANDARD = "LVCMOS25";
NET "fd_txck_o" LOC = "W17";
NET "fd_txck_o" IOSTANDARD = "LVCMOS25";
NET "fd_txer_i" LOC = "T11";
NET "fd_txer_i" IOSTANDARD = "LVCMOS25";
NET "fd_rxcdn_i" LOC = "T15";
NET "fd_rxcdn_i" IOSTANDARD = "LVCMOS25";
NET "fd_rxd_i" LOC = "U15";
NET "fd_rxd_i" IOSTANDARD = "LVCMOS25";
NET "fd_wdgn_i" LOC = "R11";
NET "fd_wdgn_i" IOSTANDARD = "LVCMOS25";
NET "fd_txena_o" LOC = "R13";
NET "fd_txena_o" IOSTANDARD = "LVCMOS25";
NET "speed_b0_i" LOC = Y5;
NET "speed_b0_i" IOSTANDARD = "LVCMOS25";
NET "speed_b1_i" LOC = AB5;
NET "speed_b1_i" IOSTANDARD = "LVCMOS25";
NET "led_tx_err_n_o" LOC = C19;
NET "led_tx_err_n_o" IOSTANDARD = "LVCMOS25";
NET "led_tx_act_n_o" LOC = A19;
NET "led_tx_act_n_o" IOSTANDARD = "LVCMOS25";
NET "led_rx_err_n_o" LOC = B20;
NET "led_rx_err_n_o" IOSTANDARD = "LVCMOS25";
NET "led_rx_act_n_o" LOC = A20;
NET "led_rx_act_n_o" IOSTANDARD = "LVCMOS25";
NET "bus_term_en_n_o" LOC = Y13;
NET "bus_term_en_n_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_term_en_o" LOC = AB13;
NET "ext_sync_term_en_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_i" LOC = T8;
NET "ext_sync_i" IOSTANDARD = "LVCMOS25";
NET "ext_sync_tst_n_o" LOC = U8;
NET "ext_sync_tst_n_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_oe_o" LOC = W6;
NET "ext_sync_oe_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_dir_o" LOC = Y6;
NET "ext_sync_dir_o" IOSTANDARD = "LVCMOS25";
NET "adc_1v8_shdn_n_o" LOC = V17;
NET "adc_1v8_shdn_n_o" IOSTANDARD = "LVCMOS25";
NET "adc_m5v_shdn_n_o" LOC = W18;
NET "adc_m5v_shdn_n_o" IOSTANDARD = "LVCMOS25";
NET "adc_5v_en_n_o" LOC = R8;
NET "adc_5v_en_n_o" IOSTANDARD = "LVCMOS25";
NET "adc_prim_conn_n_o" LOC = V7;
NET "adc_prim_conn_n_o" IOSTANDARD = "LVCMOS25";
NET "adc_sec_conn_n_o" LOC = W8;
NET "adc_sec_conn_n_o" IOSTANDARD = "LVCMOS25";
#NET "mezz_onewire_b" LOC = "A19";
#NET "mezz_onewire_b" IOSTANDARD = "LVCMOS25";
#NET "mezz_sys_scl_b" LOC = "F7";
#NET "mezz_sys_scl_b" IOSTANDARD = "LVCMOS25";
#NET "mezz_sys_sda_b" LOC = "F8";
#NET "mezz_sys_sda_b" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# 1-wire thermometer w/ ID
#----------------------------------------
NET "carrier_onewire_b" LOC = D4;
NET "carrier_onewire_b" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# GN4124 interface
#----------------------------------------
NET "rst_n_a_i" LOC = N20;
NET "rst_n_a_i" IOSTANDARD = "LVCMOS18";
NET "l2p_clk_n_o" LOC = K22;
NET "l2p_clk_n_o" IOSTANDARD = "DIFF_SSTL18_I";
NET "l2p_clk_p_o" LOC = K21;
NET "l2p_clk_p_o" IOSTANDARD = "DIFF_SSTL18_I";
NET "l2p_dframe_o" LOC = U22;
NET "l2p_dframe_o" IOSTANDARD = "SSTL18_I";
NET "l2p_edb_o" LOC = U20;
NET "l2p_edb_o" IOSTANDARD = "SSTL18_I";
NET "l2p_rdy_i" LOC = U19;
NET "l2p_rdy_i" IOSTANDARD = "SSTL18_I";
NET "l2p_valid_o" LOC = T18;
NET "l2p_valid_o" IOSTANDARD = "SSTL18_I";
NET "l_wr_rdy_i[0]" LOC = R20;
NET "l_wr_rdy_i[0]" IOSTANDARD = "SSTL18_I";
NET "l_wr_rdy_i[1]" LOC = T22;
NET "l_wr_rdy_i[1]" IOSTANDARD = "SSTL18_I";
#NET "L_CLKN" LOC = N19;
#NET "L_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
#NET "L_CLKP" LOC = P20;
#NET "L_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "p2l_dframe_i" LOC = J22;
NET "p2l_dframe_i" IOSTANDARD = "SSTL18_I";
NET "p2l_rdy_o" LOC = J16;
NET "p2l_rdy_o" IOSTANDARD = "SSTL18_I";
NET "p2l_valid_i" LOC = L19;
NET "p2l_valid_i" IOSTANDARD = "SSTL18_I";
NET "p_rd_d_rdy_i[0]" LOC = N16;
NET "p_rd_d_rdy_i[0]" IOSTANDARD = "SSTL18_I";
NET "p_rd_d_rdy_i[1]" LOC = P19;
NET "p_rd_d_rdy_i[1]" IOSTANDARD = "SSTL18_I";
NET "p_wr_rdy_o[0]" LOC = L15;
NET "p_wr_rdy_o[0]" IOSTANDARD = "SSTL18_I";
NET "p_wr_rdy_o[1]" LOC = K16;
NET "p_wr_rdy_o[1]" IOSTANDARD = "SSTL18_I";
NET "p_wr_req_i[0]" LOC = M22;
NET "p_wr_req_i[0]" IOSTANDARD = "SSTL18_I";
NET "p_wr_req_i[1]" LOC = M21;
NET "p_wr_req_i[1]" IOSTANDARD = "SSTL18_I";
NET "rx_error_o" LOC = J17;
NET "rx_error_o" IOSTANDARD = "SSTL18_I";
NET "tx_error_i" LOC = M17;
NET "tx_error_i" IOSTANDARD = "SSTL18_I";
NET "vc_rdy_i[0]" LOC = B21;
NET "vc_rdy_i[0]" IOSTANDARD = "SSTL18_I";
NET "vc_rdy_i[1]" LOC = B22;
NET "vc_rdy_i[1]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[0]" LOC = P16;
NET "l2p_data_o[0]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[1]" LOC = P21;
NET "l2p_data_o[1]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[2]" LOC = P18;
NET "l2p_data_o[2]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[3]" LOC = T20;
NET "l2p_data_o[3]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[4]" LOC = V21;
NET "l2p_data_o[4]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[5]" LOC = V19;
NET "l2p_data_o[5]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[6]" LOC = W22;
NET "l2p_data_o[6]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[7]" LOC = Y22;
NET "l2p_data_o[7]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[8]" LOC = P22;
NET "l2p_data_o[8]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[9]" LOC = R22;
NET "l2p_data_o[9]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[10]" LOC = T21;
NET "l2p_data_o[10]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[11]" LOC = T19;
NET "l2p_data_o[11]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[12]" LOC = V22;
NET "l2p_data_o[12]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[13]" LOC = V20;
NET "l2p_data_o[13]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[14]" LOC = W20;
NET "l2p_data_o[14]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[15]" LOC = Y21;
NET "l2p_data_o[15]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[0]" LOC = K20;
NET "p2l_data_i[0]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[1]" LOC = H22;
NET "p2l_data_i[1]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[2]" LOC = H21;
NET "p2l_data_i[2]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[3]" LOC = L17;
NET "p2l_data_i[3]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[4]" LOC = K17;
NET "p2l_data_i[4]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[5]" LOC = G22;
NET "p2l_data_i[5]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[6]" LOC = G20;
NET "p2l_data_i[6]" LOC = G20;
NET "p2l_data_i[6]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[7]" LOC = K18;
NET "p2l_data_i[7]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[8]" LOC = K19;
NET "p2l_data_i[8]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[9]" LOC = H20;
NET "p2l_data_i[9]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[10]" LOC = J19;
NET "p2l_data_i[10]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[11]" LOC = E22;
NET "p2l_data_i[11]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[12]" LOC = E20;
NET "p2l_data_i[12]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[13]" LOC = F22;
NET "p2l_data_i[13]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[14]" LOC = F21;
NET "p2l_data_i[14]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[15]" LOC = H19;
NET "p2l_data_i[15]" IOSTANDARD = "SSTL18_I";
NET "irq_p_o" LOC = U16;
NET "irq_p_o" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# PCB version number (coded with resistors)
#----------------------------------------
NET "pcb_ver_i[0]" LOC = P5;
NET "pcb_ver_i[0]" IOSTANDARD = "LVCMOS15";
NET "pcb_ver_i[1]" LOC = P4;
NET "pcb_ver_i[1]" IOSTANDARD = "LVCMOS15";
NET "pcb_ver_i[2]" LOC = AA2;
NET "pcb_ver_i[2]" IOSTANDARD = "LVCMOS15";
NET "pcb_ver_i[3]" LOC = AA1;
NET "pcb_ver_i[3]" IOSTANDARD = "LVCMOS15";
NET "pcb_ver_i[0]" LOC = P5;
NET "pcb_ver_i[0]" IOSTANDARD = "LVCMOS15";
NET "pcb_ver_i[1]" LOC = P4;
NET "pcb_ver_i[1]" IOSTANDARD = "LVCMOS15";
NET "pcb_ver_i[2]" LOC = AA2;
NET "pcb_ver_i[2]" IOSTANDARD = "LVCMOS15";
NET "pcb_ver_i[3]" LOC = AA1;
NET "pcb_ver_i[3]" IOSTANDARD = "LVCMOS15";
#----------------------------------------
# FMC Presence
#----------------------------------------
NET "prsnt_m2c_n_i" LOC = AB14;
NET "prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# Carrier LEDs and Buttons
#----------------------------------------
#NET "spec_aux0_i" LOC = C22;
#NET "spec_aux0_i" IOSTANDARD = "LVCMOS18";
#NET "spec_aux1_i" LOC = D21;
#NET "spec_aux1_i" IOSTANDARD = "LVCMOS18";
#NET "spec_aux2_o" LOC = G19;
#NET "spec_aux2_o" IOSTANDARD = "LVCMOS18";
#NET "spec_aux3_o" LOC = F20;
#NET "spec_aux3_o" IOSTANDARD = "LVCMOS18";
#NET "spec_aux4_o" LOC = F18;
#NET "spec_aux4_o" IOSTANDARD = "LVCMOS18";
#NET "spec_aux5_o" LOC = C20;
#NET "spec_aux5_o" IOSTANDARD = "LVCMOS18";
NET "button1_i" LOC = C22;
NET "button1_i" IOSTANDARD = "LVCMOS18";
NET "led_green_o" LOC = E5;
NET "led_green_o" IOSTANDARD = "LVCMOS25";
NET "led_red_o" LOC = D5;
NET "led_red_o" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# False Path
#----------------------------------------
# GN4124
NET "rst_n_a_i" TIG;
NET "cmp_gn4124_core/rst_*" TIG;
gateware/top/spec/spec_masterfip.vhd deleted 100644 → 0
View file @ caef7287
This diff is collapsed.
gateware/top/spec/spec_top_fmc_adc_100Ms.ucf deleted 100644 → 0
View file @ caef7287
This diff is collapsed.
gateware/top/spec/spec_top_fmc_adc_100Ms.vhd deleted 100644 → 0
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This diff is collapsed.
gateware/top/spec/spec_top_fmc_masterfip.vhd
View file @ 39f4f710
......@@ -47,7 +47,7 @@ use work.ddr3_ctrl_pkg.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.fmc_adc_mezzanine_pkg.all;
use work.sdb_meta_pkg.all;
-- use work.sdb_meta_pkg.all;
use work.timetag_core_pkg.all;
......@@ -329,18 +329,18 @@ architecture rtl of spec_top_fmc_masterfip is
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
-- Wishbone crossbar layout
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(8 downto 0) :=
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(5 downto 0) :=
(
0 => f_sdb_embed_device(c_wb_dma_ctrl_sdb, x"00001000"),
1 => f_sdb_embed_device(c_xwb_onewire_master_sdb, x"00001100"),
2 => f_sdb_embed_device(c_wb_spec_csr_sdb, x"00001200"),
3 => f_sdb_embed_device(c_xwb_vic_sdb, x"00001300"),
4 => f_sdb_embed_device(c_wb_dma_eic_sdb, x"00001400"),
5 => f_sdb_embed_bridge(c_fmc0_bridge_sdb, x"00020000"),
5 => f_sdb_embed_bridge(c_fmc0_bridge_sdb, x"00020000")
-- 5 => f_sdb_embed_bridge(c_fmc0_bridge_sdb, x"00002000"),
6 => f_sdb_embed_repo_url(c_repo_url_sdb),
7 => f_sdb_embed_synthesis(c_synthesis_sdb),
8 => f_sdb_embed_integration(c_integration_sdb)
-- 6 => f_sdb_embed_repo_url(c_repo_url_sdb),
-- 6 => f_sdb_embed_synthesis(c_synthesis_sdb),
-- 7 => f_sdb_embed_integration(c_integration_sdb)
);
-- VIC default vector setting
......
gateware/top/spec/synthesis_descriptor.vhd deleted 100644 → 0
View file @ caef7287
-------------------------------------------------------------------------------
-- Title : TDC FMC SPEC (Simple VME FMC Carrier) SDB descriptor
-- Project : TDC FMC (fmc-tdc-1ns-5cha)
-------------------------------------------------------------------------------
-- File : synthesis_descriptor.vhd
-- Author : Evangelia Gousiou
-- Company : CERN
-- Created : 2013-04-16
-- Last update: 2013-04-16
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: SDB descriptor for the top level of the FD on a SPEC carrier.
-- Contains synthesis & source repository information.
-- Warning: this file is modified whenever a synthesis is executed.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.STD_LOGIC_1164.all;
use work.wishbone_pkg.all;
package synthesis_descriptor is
constant c_sdb_synthesis_info : t_sdb_synthesis :=
(
syn_module_name => "spec_masterFIP ",
syn_commit_id => "00000000000000000000000000000000",
syn_tool_name => "ISE ",
syn_tool_version => x"00000147",
syn_date => x"20160128",
syn_username => "egousiou ");
constant c_sdb_repo_url : t_sdb_repo_url :=
(
repo_url => "http://svn.ohwr.org/projects/masterFIP "
);
end package synthesis_descriptor;
pts/fmcmasterfip.sh
View file @ 39f4f710
......@@ -157,7 +157,7 @@ do
cp $f "${LOGDIR}/adcdata/${newname}"
done
echo "ADC samples backed up in ${LOGDIR}/adcdata/${newname}"
echo "ADC samples backed up in ${LOGDIR}/adcdata"
else
echo "Did not find any ADC samples to backup"
fi
......
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