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MasterFIP - Testing
Commit 39f4f710 authored by Marek Gumiński's avatar Marek Gumiński
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Removed ununed files and comments in vhdl files

parent caef7287
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Showing with 23 additions and 3019 deletions
gateware/syn/spec/spec_fmc_masterfip_pts.xise
View file @ 39f4f710
......@@ -501,7 +501,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/fmc-adc-100m14b4cha-gw/hdl/adc/rtl/fmc_adc_mezzanine_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="102"/>
<association xil_pn:name="Implementation" xil_pn:seqID="101"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
......@@ -594,7 +594,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../top/spec/spec_top_fmc_masterfip.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="104"/>
<association xil_pn:name="Implementation" xil_pn:seqID="103"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -603,7 +603,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="84"/>
</file>
<file xil_pn:name="../../rtl/fmc_masterfip_mezzanine.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="99"/>
<association xil_pn:name="Implementation" xil_pn:seqID="98"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -663,7 +663,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="100"/>
<association xil_pn:name="Implementation" xil_pn:seqID="99"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="82"/>
......@@ -696,7 +696,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="95"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="101"/>
<association xil_pn:name="Implementation" xil_pn:seqID="100"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="86"/>
......@@ -774,7 +774,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../top/spec/dma_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="97"/>
<association xil_pn:name="Implementation" xil_pn:seqID="96"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -810,7 +810,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="77"/>
</file>
<file xil_pn:name="../../top/spec/sdb_meta_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="96"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -861,7 +861,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="103"/>
<association xil_pn:name="Implementation" xil_pn:seqID="102"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="89"/>
......@@ -876,7 +876,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../../top/spec/carrier_csr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="98"/>
<association xil_pn:name="Implementation" xil_pn:seqID="97"/>
</file>
<file xil_pn:name="../../rtl/fmc_masterFIP_core_pts.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="73"/>
......
gateware/top/1:fmc-masterfip-EDA-03098-V1-3 deleted 100644 → 0
View file @ caef7287
masterfip_speed_b[0] : in std_logic;
masterfip_speed_b[1] : in std_logic;
masterfip_adc_outa_p[3] : in std_logic;
masterfip_adc_outa_n[3] : in std_logic;
masterfip_adc_outa_p[1] : in std_logic;
masterfip_adc_outa_n[1] : in std_logic;
masterfip_c2m_adc_clk_p : in std_logic;
masterfip_c2m_adc_clk_n : in std_logic;
masterfip_gbt_adc_clk_p : in std_logic;
masterfip_gbt_adc_clk_n : in std_logic;
masterfip_adc_outb_p[4] : in std_logic;
masterfip_adc_outb_n[4] : in std_logic;
masterfip_adc_outb_p[3] : in std_logic;
masterfip_adc_outb_n[3] : in std_logic;
masterfip_adc_outb_p[2] : in std_logic;
masterfip_adc_outb_n[2] : in std_logic;
masterfip_term_en_n : in std_logic;
masterfip_ext_sync_term_en : in std_logic;
masterfip_test_point[1] : in std_logic;
masterfip_test_point[2] : in std_logic;
masterfip_test_point[3] : in std_logic;
masterfip_test_point[4] : in std_logic;
masterfip_adc_fr_n : in std_logic;
masterfip_adc_fr_p : in std_logic;
masterfip_sec_conn_n : in std_logic;
masterfip_5v_en_n : in std_logic;
masterfip_adc_out2a_p : in std_logic;
masterfip_adc_out2a_n : in std_logic;
masterfip_fd_wdg_n : in std_logic;
masterfip_fd_txer : in std_logic;
masterfip_fd_txena : in std_logic;
masterfip_fd_txd : in std_logic;
masterfip_fd_cd_n : in std_logic;
masterfip_fd_rxd : in std_logic;
masterfip_fd_txck : in std_logic;
masterfip_fd_rst_n : in std_logic;
masterfip_one_wire : in std_logic;
masterfip_tx_err_led_n : in std_logic;
masterfip_tx_act_led_n : in std_logic;
masterfip_adc_dco_n : in std_logic;
masterfip_adc_dco_p : in std_logic;
masterfip_prim_conn_n : in std_logic;
masterfip_ext_sync : in std_logic;
masterfip_ext_sync_tst_n : in std_logic;
masterfip_adc_out4a_p : in std_logic;
masterfip_adc_out4a_n : in std_logic;
masterfip_sync_led_n : in std_logic;
masterfip_out_of_sync_led_ : in std_logic;
masterfip_adc_out1b_p : in std_logic;
masterfip_adc_out1b_n : in std_logic;
masterfip_si570_oe : in std_logic;
masterfip_si570_sda : in std_logic;
masterfip_si570_scl : in std_logic;
masterfip_adc_cs : in std_logic;
masterfip_adc_sck : in std_logic;
masterfip_adc_sdi : in std_logic;
masterfip_adc_sdo : in std_logic;
masterfip_1v8_shdn_n : in std_logic;
masterfip_m5v_shdn_n : in std_logic;
masterfip_rx_err_led_n : in std_logic;
masterfip_rx_act_led_n : in std_logic;
masterfip_ext_sync_oe : in std_logic;
masterfip_ext_sync_dir : in std_logic;
# <ucfgen_start>
# This section has bee generated automatically by ucfgen.py. Do not hand-modify if not really necessary.
# ucfgen pin assignments for mezzanine fmc-masterfip-EDA-03098-V1-3 slot 0
NET "masterfip_speed_b[0]" LOC = "Y5";
NET "masterfip_speed_b[0]" IOSTANDARD = "LVCMOS25";
NET "masterfip_speed_b[1]" LOC = "AB5";
NET "masterfip_speed_b[1]" IOSTANDARD = "LVCMOS25";
NET "masterfip_adc_outa_p[3]" LOC = "AA8";
NET "masterfip_adc_outa_p[3]" IOSTANDARD = "LVCMOS25";
NET "masterfip_adc_outa_n[3]" LOC = "AB8";
NET "masterfip_adc_outa_n[3]" IOSTANDARD = "LVCMOS25";
NET "masterfip_adc_outa_p[1]" LOC = "AA4";
NET "masterfip_adc_outa_p[1]" IOSTANDARD = "LVCMOS25";
NET "masterfip_adc_outa_n[1]" LOC = "AB4";
NET "masterfip_adc_outa_n[1]" IOSTANDARD = "LVCMOS25";
NET "masterfip_c2m_adc_clk_p" LOC = "T12";
NET "masterfip_c2m_adc_clk_p" IOSTANDARD = "LVCMOS25";
NET "masterfip_c2m_adc_clk_n" LOC = "U12";
NET "masterfip_c2m_adc_clk_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_gbt_adc_clk_p" LOC = "B6";
NET "masterfip_gbt_adc_clk_p" IOSTANDARD = "LVDS_25";
NET "masterfip_gbt_adc_clk_n" LOC = "A6";
NET "masterfip_gbt_adc_clk_n" IOSTANDARD = "LVDS_25";
NET "masterfip_adc_outb_p[4]" LOC = "AA6";
NET "masterfip_adc_outb_p[4]" IOSTANDARD = "LVDS_25";
NET "masterfip_adc_outb_n[4]" LOC = "AB6";
NET "masterfip_adc_outb_n[4]" IOSTANDARD = "LVDS_25";
NET "masterfip_adc_outb_p[3]" LOC = "Y7";
NET "masterfip_adc_outb_p[3]" IOSTANDARD = "LVDS_25";
NET "masterfip_adc_outb_n[3]" LOC = "AB7";
NET "masterfip_adc_outb_n[3]" IOSTANDARD = "LVDS_25";
NET "masterfip_adc_outb_p[2]" LOC = "Y9";
NET "masterfip_adc_outb_p[2]" IOSTANDARD = "LVDS_25";
NET "masterfip_adc_outb_n[2]" LOC = "AB9";
NET "masterfip_adc_outb_n[2]" IOSTANDARD = "LVDS_25";
NET "masterfip_term_en_n" LOC = "Y13";
NET "masterfip_term_en_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_ext_sync_term_en" LOC = "AB13";
NET "masterfip_ext_sync_term_en" IOSTANDARD = "LVCMOS25";
NET "masterfip_test_point[1]" LOC = "AA16";
NET "masterfip_test_point[1]" IOSTANDARD = "LVCMOS25";
NET "masterfip_test_point[2]" LOC = "AB16";
NET "masterfip_test_point[2]" IOSTANDARD = "LVCMOS25";
NET "masterfip_test_point[3]" LOC = "Y17";
NET "masterfip_test_point[3]" IOSTANDARD = "LVCMOS25";
NET "masterfip_test_point[4]" LOC = "AB17";
NET "masterfip_test_point[4]" IOSTANDARD = "LVCMOS25";
NET "masterfip_adc_fr_n" LOC = "AA12";
NET "masterfip_adc_fr_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_adc_fr_p" LOC = "AB12";
NET "masterfip_adc_fr_p" IOSTANDARD = "LVCMOS25";
NET "masterfip_sec_conn_n" LOC = "W8";
NET "masterfip_sec_conn_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_5v_en_n" LOC = "R8";
NET "masterfip_5v_en_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_adc_out2a_p" LOC = "W12";
NET "masterfip_adc_out2a_p" IOSTANDARD = "LVDS_25";
NET "masterfip_adc_out2a_n" LOC = "Y12";
NET "masterfip_adc_out2a_n" IOSTANDARD = "LVDS_25";
NET "masterfip_fd_wdg_n" LOC = "R11";
NET "masterfip_fd_wdg_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_fd_txer" LOC = "T11";
NET "masterfip_fd_txer" IOSTANDARD = "LVCMOS25";
NET "masterfip_fd_txena" LOC = "R13";
NET "masterfip_fd_txena" IOSTANDARD = "LVCMOS25";
NET "masterfip_fd_txd" LOC = "T14";
NET "masterfip_fd_txd" IOSTANDARD = "LVCMOS25";
NET "masterfip_fd_cd_n" LOC = "T15";
NET "masterfip_fd_cd_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_fd_rxd" LOC = "U15";
NET "masterfip_fd_rxd" IOSTANDARD = "LVCMOS25";
NET "masterfip_fd_txck" LOC = "W17";
NET "masterfip_fd_txck" IOSTANDARD = "LVCMOS25";
NET "masterfip_fd_rst_n" LOC = "Y18";
NET "masterfip_fd_rst_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_one_wire" LOC = "D7";
NET "masterfip_one_wire" IOSTANDARD = "LVCMOS25";
NET "masterfip_tx_err_led_n" LOC = "C18";
NET "masterfip_tx_err_led_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_tx_act_led_n" LOC = "C19";
NET "masterfip_tx_act_led_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_adc_dco_n" LOC = "Y11";
NET "masterfip_adc_dco_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_adc_dco_p" LOC = "AB11";
NET "masterfip_adc_dco_p" IOSTANDARD = "LVCMOS25";
NET "masterfip_prim_conn_n" LOC = "V7";
NET "masterfip_prim_conn_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_ext_sync" LOC = "T8";
NET "masterfip_ext_sync" IOSTANDARD = "LVCMOS25";
NET "masterfip_ext_sync_tst_n" LOC = "U8";
NET "masterfip_ext_sync_tst_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_adc_out4a_p" LOC = "U9";
NET "masterfip_adc_out4a_p" IOSTANDARD = "LVCMOS25";
NET "masterfip_adc_out4a_n" LOC = "V9";
NET "masterfip_adc_out4a_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_sync_led_n" LOC = "W10";
NET "masterfip_sync_led_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_out_of_sync_led_" LOC = "Y10";
NET "masterfip_out_of_sync_led_" IOSTANDARD = "LVCMOS25";
NET "masterfip_adc_out1b_p" LOC = "V11";
NET "masterfip_adc_out1b_p" IOSTANDARD = "LVCMOS25";
NET "masterfip_adc_out1b_n" LOC = "W11";
NET "masterfip_adc_out1b_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_si570_oe" LOC = "AB15";
NET "masterfip_si570_oe" IOSTANDARD = "LVCMOS25";
NET "masterfip_si570_sda" LOC = "V13";
NET "masterfip_si570_sda" IOSTANDARD = "LVCMOS25";
NET "masterfip_si570_scl" LOC = "W13";
NET "masterfip_si570_scl" IOSTANDARD = "LVCMOS25";
NET "masterfip_adc_cs" LOC = "W14";
NET "masterfip_adc_cs" IOSTANDARD = "LVCMOS25";
NET "masterfip_adc_sck" LOC = "Y14";
NET "masterfip_adc_sck" IOSTANDARD = "LVCMOS25";
NET "masterfip_adc_sdi" LOC = "Y16";
NET "masterfip_adc_sdi" IOSTANDARD = "LVCMOS25";
NET "masterfip_adc_sdo" LOC = "W15";
NET "masterfip_adc_sdo" IOSTANDARD = "LVCMOS25";
NET "masterfip_1v8_shdn_n" LOC = "V17";
NET "masterfip_1v8_shdn_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_m5v_shdn_n" LOC = "W18";
NET "masterfip_m5v_shdn_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_rx_err_led_n" LOC = "B20";
NET "masterfip_rx_err_led_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_rx_act_led_n" LOC = "A20";
NET "masterfip_rx_act_led_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_ext_sync_oe" LOC = "W6";
NET "masterfip_ext_sync_oe" IOSTANDARD = "LVCMOS25";
NET "masterfip_ext_sync_dir" LOC = "Y6";
NET "masterfip_ext_sync_dir" IOSTANDARD = "LVCMOS25";
# <ucfgen_end>
gateware/top/ports deleted 100644 → 0
View file @ caef7287
masterfip_speed_b[0] : in std_logic;
masterfip_speed_b[1] : in std_logic;
masterfip_adc_outa_p[3] : in std_logic;
masterfip_adc_outa_n[3] : in std_logic;
masterfip_adc_outa_p[1] : in std_logic;
masterfip_adc_outa_n[1] : in std_logic;
masterfip_c2m_adc_clk_p : out std_logic;
masterfip_c2m_adc_clk_n : out std_logic;
masterfip_gbt_adc_clk_p : out std_logic;
masterfip_gbt_adc_clk_n : out std_logic;
masterfip_adc_outb_p[4] : in std_logic;
masterfip_adc_outb_n[4] : in std_logic;
masterfip_adc_outb_p[3] : in std_logic;
masterfip_adc_outb_n[3] : in std_logic;
masterfip_adc_outb_p[2] : in std_logic;
masterfip_adc_outb_n[2] : in std_logic;
masterfip_term_en_n : out std_logic;
masterfip_ext_sync_term_en : out std_logic;
masterfip_test_point[1] : in std_logic;
masterfip_test_point[2] : in std_logic;
masterfip_test_point[3] : in std_logic;
masterfip_test_point[4] : in std_logic;
masterfip_adc_fr_n : in std_logic;
masterfip_adc_fr_p : in std_logic;
masterfip_sec_conn_n : out std_logic;
masterfip_5v_en_n : out std_logic;
masterfip_adc_out2a_p : in std_logic;
masterfip_adc_out2a_n : in std_logic;
masterfip_fd_wdg_n : in std_logic;
masterfip_fd_txer : in std_logic;
masterfip_fd_txena : out std_logic;
masterfip_fd_txd : out std_logic;
masterfip_fd_cd_n : in std_logic;
masterfip_fd_rxd : in std_logic;
masterfip_fd_txck : out std_logic;
masterfip_fd_rst_n : out std_logic;
masterfip_one_wire : inout std_logic;
masterfip_tx_err_led_n : out std_logic;
masterfip_tx_act_led_n : out std_logic;
masterfip_adc_dco_n : in std_logic;
masterfip_adc_dco_p : in std_logic;
masterfip_prim_conn_n : out std_logic;
masterfip_ext_sync : inout std_logic;
masterfip_ext_sync_tst_n : out std_logic;
masterfip_adc_out4a_p : in std_logic;
masterfip_adc_out4a_n : in std_logic;
masterfip_sync_led_n : out std_logic;
masterfip_out_of_sync_led_ : out std_logic;
masterfip_adc_out1b_p : in std_logic;
masterfip_adc_out1b_n : in std_logic;
masterfip_si570_oe : out std_logic;
masterfip_si570_sda : inout std_logic;
masterfip_si570_scl : out std_logic;
masterfip_adc_cs : out std_logic;
masterfip_adc_sck : out std_logic;
masterfip_adc_sdi : in std_logic;
masterfip_adc_sdo : out std_logic;
masterfip_1v8_shdn_n : out std_logic;
masterfip_m5v_shdn_n : out std_logic;
masterfip_rx_err_led_n : out std_logic;
masterfip_rx_act_led_n : out std_logic;
masterfip_ext_sync_oe : out std_logic;
masterfip_ext_sync_dir : out std_logic;
gateware/top/spec/sdb_meta_pkg.vhd
View file @ 39f4f710
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- FMC ADC 100Ms/s core
-- http://www.ohwr.org/projects/fmc-adc-100m14b4cha
--------------------------------------------------------------------------------
--
-- unit name: sdb_meta_pkg (sdb_meta_pkg.vhd)
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 11-03-2013
--
-- description: Sdb meta-information for the FMC ADC 100Ms/s design for SPEC.
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see git log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
-- Modified manually
library ieee;
use ieee.std_logic_1164.all;
......@@ -46,23 +15,23 @@ package sdb_meta_pkg is
-- Top module repository url
constant c_repo_url_sdb : t_sdb_repo_url := (
-- url (string, 63 char)
repo_url => "git://ohwr.org/fmc-projects/fmc-adc-100m14b4cha.git ");
repo_url => "git@ohwr.org:cern-fip/masterfip/masterfip-tst.git ");
-- Synthesis informations
constant c_synthesis_sdb : t_sdb_synthesis := (
-- Top module name (string, 16 char)
syn_module_name => "spec_top_fmc_adc",
syn_module_name => "spec_top_fmc_masterfip",
-- Commit ID (hex string, 128-bit = 32 char)
-- git log -1 --format="%H" | cut -c1-32
syn_commit_id => "26749f0a1873c215abb33942a8a335db",
syn_commit_id => "000000000000000000000000000000",
-- Synthesis tool name (string, 8 char)
syn_tool_name => "ISE ",
-- Synthesis tool version (bcd encoded, 32-bit)
syn_tool_version => x"00000133",
-- Synthesis date (bcd encoded, 32-bit, yyyymmdd)
syn_date => x"20140425",
syn_date => x"20160701",
-- Synthesised by (string, 15 char)
syn_username => "mcattin ");
syn_username => "mguminsk ");
-- Integration record
constant c_integration_sdb : t_sdb_integration := (
......@@ -71,7 +40,7 @@ package sdb_meta_pkg is
device_id => x"47c786a2", -- echo "spec_fmc-adc-100m14b4cha" | md5sum | cut -c1-8
version => x"00040000", -- bcd encoded, [31:16] = major, [15:0] = minor
date => x"20140425", -- yyyymmdd
name => "spec_fmcadc100m14b "));
name => "spec_fmcmasterfip "));
end sdb_meta_pkg;
......
gateware/top/spec/spec_masterfip.ucf deleted 100644 → 0
View file @ caef7287
#----------------------------------------
# Clocks
#----------------------------------------
NET "clk_20m_vcxo_i" LOC = H12;
NET "clk_20m_vcxo_i" IOSTANDARD = "LVCMOS25";
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo_i";
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
NET "p2l_clk_n_i" LOC = M19;
NET "p2l_clk_n_i" IOSTANDARD = "DIFF_SSTL18_I";
NET "p2l_clk_p_i" LOC = M20;
NET "p2l_clk_p_i" IOSTANDARD = "DIFF_SSTL18_I";
NET "p2l_clk_p_i" TNM_NET = "p2l_clk_p_i";
TIMESPEC TS_p2l_clk_p_i = PERIOD "p2l_clk_p_i" 5 ns HIGH 50%;
NET "p2l_clk_n_i" TNM_NET = "p2l_clk_n_i";
TIMESPEC TS_p2l_clk_n_i = PERIOD "p2l_clk_n_i" 5 ns HIGH 50%;
#----------------------------------------
# FMC slot
#----------------------------------------
NET "fd_rstn_o" LOC = "Y18";
NET "fd_rstn_o" IOSTANDARD = "LVCMOS25";
NET "fd_txd_o" LOC = "T14";
NET "fd_txd_o" IOSTANDARD = "LVCMOS25";
NET "fd_txck_o" LOC = "W17";
NET "fd_txck_o" IOSTANDARD = "LVCMOS25";
NET "fd_txer_i" LOC = "T11";
NET "fd_txer_i" IOSTANDARD = "LVCMOS25";
NET "fd_rxcdn_i" LOC = "T15";
NET "fd_rxcdn_i" IOSTANDARD = "LVCMOS25";
NET "fd_rxd_i" LOC = "U15";
NET "fd_rxd_i" IOSTANDARD = "LVCMOS25";
NET "fd_wdgn_i" LOC = "R11";
NET "fd_wdgn_i" IOSTANDARD = "LVCMOS25";
NET "fd_txena_o" LOC = "R13";
NET "fd_txena_o" IOSTANDARD = "LVCMOS25";
NET "speed_b0_i" LOC = Y5;
NET "speed_b0_i" IOSTANDARD = "LVCMOS25";
NET "speed_b1_i" LOC = AB5;
NET "speed_b1_i" IOSTANDARD = "LVCMOS25";
NET "led_tx_err_n_o" LOC = C19;
NET "led_tx_err_n_o" IOSTANDARD = "LVCMOS25";
NET "led_tx_act_n_o" LOC = A19;
NET "led_tx_act_n_o" IOSTANDARD = "LVCMOS25";
NET "led_rx_err_n_o" LOC = B20;
NET "led_rx_err_n_o" IOSTANDARD = "LVCMOS25";
NET "led_rx_act_n_o" LOC = A20;
NET "led_rx_act_n_o" IOSTANDARD = "LVCMOS25";
NET "bus_term_en_n_o" LOC = Y13;
NET "bus_term_en_n_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_term_en_o" LOC = AB13;
NET "ext_sync_term_en_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_i" LOC = T8;
NET "ext_sync_i" IOSTANDARD = "LVCMOS25";
NET "ext_sync_tst_n_o" LOC = U8;
NET "ext_sync_tst_n_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_oe_o" LOC = W6;
NET "ext_sync_oe_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_dir_o" LOC = Y6;
NET "ext_sync_dir_o" IOSTANDARD = "LVCMOS25";
NET "adc_1v8_shdn_n_o" LOC = V17;
NET "adc_1v8_shdn_n_o" IOSTANDARD = "LVCMOS25";
NET "adc_m5v_shdn_n_o" LOC = W18;
NET "adc_m5v_shdn_n_o" IOSTANDARD = "LVCMOS25";
NET "adc_5v_en_n_o" LOC = R8;
NET "adc_5v_en_n_o" IOSTANDARD = "LVCMOS25";
NET "adc_prim_conn_n_o" LOC = V7;
NET "adc_prim_conn_n_o" IOSTANDARD = "LVCMOS25";
NET "adc_sec_conn_n_o" LOC = W8;
NET "adc_sec_conn_n_o" IOSTANDARD = "LVCMOS25";
#NET "mezz_onewire_b" LOC = "A19";
#NET "mezz_onewire_b" IOSTANDARD = "LVCMOS25";
#NET "mezz_sys_scl_b" LOC = "F7";
#NET "mezz_sys_scl_b" IOSTANDARD = "LVCMOS25";
#NET "mezz_sys_sda_b" LOC = "F8";
#NET "mezz_sys_sda_b" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# 1-wire thermometer w/ ID
#----------------------------------------
NET "carrier_onewire_b" LOC = D4;
NET "carrier_onewire_b" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# GN4124 interface
#----------------------------------------
NET "rst_n_a_i" LOC = N20;
NET "rst_n_a_i" IOSTANDARD = "LVCMOS18";
NET "l2p_clk_n_o" LOC = K22;
NET "l2p_clk_n_o" IOSTANDARD = "DIFF_SSTL18_I";
NET "l2p_clk_p_o" LOC = K21;
NET "l2p_clk_p_o" IOSTANDARD = "DIFF_SSTL18_I";
NET "l2p_dframe_o" LOC = U22;
NET "l2p_dframe_o" IOSTANDARD = "SSTL18_I";
NET "l2p_edb_o" LOC = U20;
NET "l2p_edb_o" IOSTANDARD = "SSTL18_I";
NET "l2p_rdy_i" LOC = U19;
NET "l2p_rdy_i" IOSTANDARD = "SSTL18_I";
NET "l2p_valid_o" LOC = T18;
NET "l2p_valid_o" IOSTANDARD = "SSTL18_I";
NET "l_wr_rdy_i[0]" LOC = R20;
NET "l_wr_rdy_i[0]" IOSTANDARD = "SSTL18_I";
NET "l_wr_rdy_i[1]" LOC = T22;
NET "l_wr_rdy_i[1]" IOSTANDARD = "SSTL18_I";
#NET "L_CLKN" LOC = N19;
#NET "L_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
#NET "L_CLKP" LOC = P20;
#NET "L_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "p2l_dframe_i" LOC = J22;
NET "p2l_dframe_i" IOSTANDARD = "SSTL18_I";
NET "p2l_rdy_o" LOC = J16;
NET "p2l_rdy_o" IOSTANDARD = "SSTL18_I";
NET "p2l_valid_i" LOC = L19;
NET "p2l_valid_i" IOSTANDARD = "SSTL18_I";
NET "p_rd_d_rdy_i[0]" LOC = N16;
NET "p_rd_d_rdy_i[0]" IOSTANDARD = "SSTL18_I";
NET "p_rd_d_rdy_i[1]" LOC = P19;
NET "p_rd_d_rdy_i[1]" IOSTANDARD = "SSTL18_I";
NET "p_wr_rdy_o[0]" LOC = L15;
NET "p_wr_rdy_o[0]" IOSTANDARD = "SSTL18_I";
NET "p_wr_rdy_o[1]" LOC = K16;
NET "p_wr_rdy_o[1]" IOSTANDARD = "SSTL18_I";
NET "p_wr_req_i[0]" LOC = M22;
NET "p_wr_req_i[0]" IOSTANDARD = "SSTL18_I";
NET "p_wr_req_i[1]" LOC = M21;
NET "p_wr_req_i[1]" IOSTANDARD = "SSTL18_I";
NET "rx_error_o" LOC = J17;
NET "rx_error_o" IOSTANDARD = "SSTL18_I";
NET "tx_error_i" LOC = M17;
NET "tx_error_i" IOSTANDARD = "SSTL18_I";
NET "vc_rdy_i[0]" LOC = B21;
NET "vc_rdy_i[0]" IOSTANDARD = "SSTL18_I";
NET "vc_rdy_i[1]" LOC = B22;
NET "vc_rdy_i[1]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[0]" LOC = P16;
NET "l2p_data_o[0]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[1]" LOC = P21;
NET "l2p_data_o[1]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[2]" LOC = P18;
NET "l2p_data_o[2]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[3]" LOC = T20;
NET "l2p_data_o[3]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[4]" LOC = V21;
NET "l2p_data_o[4]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[5]" LOC = V19;
NET "l2p_data_o[5]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[6]" LOC = W22;
NET "l2p_data_o[6]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[7]" LOC = Y22;
NET "l2p_data_o[7]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[8]" LOC = P22;
NET "l2p_data_o[8]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[9]" LOC = R22;
NET "l2p_data_o[9]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[10]" LOC = T21;
NET "l2p_data_o[10]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[11]" LOC = T19;
NET "l2p_data_o[11]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[12]" LOC = V22;
NET "l2p_data_o[12]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[13]" LOC = V20;
NET "l2p_data_o[13]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[14]" LOC = W20;
NET "l2p_data_o[14]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[15]" LOC = Y21;
NET "l2p_data_o[15]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[0]" LOC = K20;
NET "p2l_data_i[0]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[1]" LOC = H22;
NET "p2l_data_i[1]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[2]" LOC = H21;
NET "p2l_data_i[2]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[3]" LOC = L17;
NET "p2l_data_i[3]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[4]" LOC = K17;
NET "p2l_data_i[4]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[5]" LOC = G22;
NET "p2l_data_i[5]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[6]" LOC = G20;
NET "p2l_data_i[6]" LOC = G20;
NET "p2l_data_i[6]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[7]" LOC = K18;
NET "p2l_data_i[7]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[8]" LOC = K19;
NET "p2l_data_i[8]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[9]" LOC = H20;
NET "p2l_data_i[9]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[10]" LOC = J19;
NET "p2l_data_i[10]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[11]" LOC = E22;
NET "p2l_data_i[11]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[12]" LOC = E20;
NET "p2l_data_i[12]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[13]" LOC = F22;
NET "p2l_data_i[13]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[14]" LOC = F21;
NET "p2l_data_i[14]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[15]" LOC = H19;
NET "p2l_data_i[15]" IOSTANDARD = "SSTL18_I";
NET "irq_p_o" LOC = U16;
NET "irq_p_o" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# PCB version number (coded with resistors)
#----------------------------------------
NET "pcb_ver_i[0]" LOC = P5;
NET "pcb_ver_i[0]" IOSTANDARD = "LVCMOS15";
NET "pcb_ver_i[1]" LOC = P4;
NET "pcb_ver_i[1]" IOSTANDARD = "LVCMOS15";
NET "pcb_ver_i[2]" LOC = AA2;
NET "pcb_ver_i[2]" IOSTANDARD = "LVCMOS15";
NET "pcb_ver_i[3]" LOC = AA1;
NET "pcb_ver_i[3]" IOSTANDARD = "LVCMOS15";
NET "pcb_ver_i[0]" LOC = P5;
NET "pcb_ver_i[0]" IOSTANDARD = "LVCMOS15";
NET "pcb_ver_i[1]" LOC = P4;
NET "pcb_ver_i[1]" IOSTANDARD = "LVCMOS15";
NET "pcb_ver_i[2]" LOC = AA2;
NET "pcb_ver_i[2]" IOSTANDARD = "LVCMOS15";
NET "pcb_ver_i[3]" LOC = AA1;
NET "pcb_ver_i[3]" IOSTANDARD = "LVCMOS15";
#----------------------------------------
# FMC Presence
#----------------------------------------
NET "prsnt_m2c_n_i" LOC = AB14;
NET "prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# Carrier LEDs and Buttons
#----------------------------------------
#NET "spec_aux0_i" LOC = C22;
#NET "spec_aux0_i" IOSTANDARD = "LVCMOS18";
#NET "spec_aux1_i" LOC = D21;
#NET "spec_aux1_i" IOSTANDARD = "LVCMOS18";
#NET "spec_aux2_o" LOC = G19;
#NET "spec_aux2_o" IOSTANDARD = "LVCMOS18";
#NET "spec_aux3_o" LOC = F20;
#NET "spec_aux3_o" IOSTANDARD = "LVCMOS18";
#NET "spec_aux4_o" LOC = F18;
#NET "spec_aux4_o" IOSTANDARD = "LVCMOS18";
#NET "spec_aux5_o" LOC = C20;
#NET "spec_aux5_o" IOSTANDARD = "LVCMOS18";
NET "button1_i" LOC = C22;
NET "button1_i" IOSTANDARD = "LVCMOS18";
NET "led_green_o" LOC = E5;
NET "led_green_o" IOSTANDARD = "LVCMOS25";
NET "led_red_o" LOC = D5;
NET "led_red_o" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# False Path
#----------------------------------------
# GN4124
NET "rst_n_a_i" TIG;
NET "cmp_gn4124_core/rst_*" TIG;
gateware/top/spec/spec_masterfip.vhd deleted 100644 → 0
View file @ caef7287
--_________________________________________________________________________________________________
-- |
-- |SPEC masterFIP| |
-- |
-- CERN, BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- spec_masterfip |
-- |
---------------------------------------------------------------------------------------------------
-- File spec_masterfip.vhd |
-- |
-- Description Top level of a simple masterFIP on a SPEC carrier. |
-- Figure 1 shows the architecture of the unit. |
-- |
-- This design does not use the Mock Turtle core and can only be used for very |
-- simple WorldFIP manipulations. |
-- |
-- The fmc_masterFIP_core mainly implements the WorldFIP serializer and deserialiser.|
-- Its interface component fmc_masterfip_csr provides a set of registers to basically|
-- - control the serialiser to send out WorldFIP frames and |
-- - monitor if a WorldFIP frame has arrived to the deserialiser |
-- The core accesses all the WorldFIP-specific parts of the masterFIP mezzanine board|
-- However there is no access to the ADC part of the masterFIP mezzanine board. |
-- |
-- The SPEC_CSR module provides general information on the SPEC PCB version, PLLs |
-- locking state etc. |
-- |
-- The 1-Wire core provides communication with the SPEC Thermometer&UniqueID chip. |
-- |
-- All the cores communicate with the GN4124 core through the SDB crossbar. The SDB |
-- crossbar is responsible for managing the access to the GN4124 core. |
-- |
-- The design has only one clock domain, 100 MHz generated by a Xilinx internal PLL |
-- which is using the 20 MHz VCXO on the SPEC. |
-- |
-- __________________________________________________________________ |
-- | SPEC FPGA | |
-- ___________ | ___ _____ | |
-- | | | ____________________________ | | | | | |
-- | masterFIP | | | | | | | | | |
-- | mezz |<->| | masterFIP mezzanine | --- | | | | | |
-- |___________| | |____________________________| | | | G | | |
-- | | | | N | | |
-- | ____________________________ | S | | 4 | | |
-- SPEC 1Wire <->| | SPEC 1-Wire | ---- | D | <--> | 1 | | |
-- | |____________________________| | B | | 2 | | |
-- | | | | 4 | | |
-- | ____________________________ | | | | | |
-- | | SPEC CSR | ---- | | | | | |
-- | |____________________________| | | | | | |
-- | |___| |_____| | |
-- |__________________________________________________________________| |
-- Figure 1 |
-- |
-- |
-- Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 07/2014 |
-- Version v1 |
-- |
---------------- |
-- Last changes |
-- 07/2014 v1 EG concept validation using very basic board |
-- 07/2015 v2 EG validation of the masterFIP v1 prototype board |
-- 01/2016 v3 EG cleaned-up version to be used by PTS team |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.masterFIP_pkg.all;
use work.gn4124_core_pkg.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.synthesis_descriptor.all;
library UNISIM;
use UNISIM.vcomponents.all;
--=================================================================================================
-- Entity declaration for spec_masterfip
--=================================================================================================
entity spec_masterfip is
generic
(g_span : integer := 32; -- address span in bus interfaces
g_width : integer := 32; -- data width in bus interfaces
values_for_simul : boolean := FALSE); -- set to TRUE in test-bench instantiation
port
(-- SPEC carrier
clk_20m_vcxo_i : in std_logic; -- 20 MHz VCXO
carrier_onewire_b : inout std_logic; -- 1-wire
button1_i : in std_logic := '1'; -- reset button
button2_i : in std_logic := '1'; -- not used button
led_green_o : out std_logic; -- LEDs carrier front pannel
led_red_o : out std_logic;
pcb_ver_i : in std_logic_vector(3 downto 0); -- PCB version
prsnt_m2c_n_i : in std_logic; -- mezzanine presence
-- Interface with GN4124
rst_n_a_i : in std_logic;
-- P2L Direction
p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
p2l_data_i : in std_logic_vector(15 downto 0);-- Parallel receive data
p2l_dframe_i : in std_logic; -- Receive Frame
p2l_valid_i : in std_logic; -- Receive Data Valid
p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag
p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
rx_error_o : out std_logic; -- Receive Error
vc_rdy_i : in std_logic_vector(1 downto 0); -- Virtual channel ready
-- L2P Direction
l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+ (freq set in GN4124 config registers)
l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock- (freq set in GN4124 config registers)
l2p_data_o : out std_logic_vector(15 downto 0);-- Parallel transmit data
l2p_dframe_o : out std_logic; -- Transmit Data Frame
l2p_valid_o : out std_logic; -- Transmit Data Valid
l2p_edb_o : out std_logic; -- Packet termination and discard
l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag
l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
tx_error_i : in std_logic; -- Transmit Error
irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO 8
irq_aux_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO 9, aux signal
-- masterFIP mezzanine
speed_b0_i : in std_logic; -- WorldFIP bus Speed
speed_b1_i : in std_logic;
bus_term_en_n_o : out std_logic; -- WorldFIP bus termination
fd_rxcdn_i : in std_logic; -- FielDrive
fd_rxd_i : in std_logic;
fd_txer_i : in std_logic;
fd_wdgn_i : in std_logic;
fd_rstn_o : out std_logic;
fd_txck_o : out std_logic;
fd_txd_o : out std_logic;
fd_txena_o : out std_logic;
ext_sync_term_en_o : out std_logic; -- External synch pulse transceiver
ext_sync_dir_o : out std_logic;
ext_sync_oe_o : out std_logic;
ext_sync_tst_n_o : out std_logic;
ext_sync_i : in std_logic;
adc_1v8_shdn_n_o : out std_logic; -- Power supplies for the ADC
adc_m5v_shdn_n_o : out std_logic;
adc_5v_en_n_o : out std_logic;
adc_prim_conn_n_o : out std_logic;
adc_sec_conn_n_o : out std_logic;
led_tx_err_n_o : out std_logic; -- LEDs mezzanine front pannel
led_tx_act_n_o : out std_logic;
led_rx_err_n_o : out std_logic;
led_rx_act_n_o : out std_logic);
end spec_masterfip;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of spec_masterfip is
---------------------------------------------------------------------------------------------------
-- SDB CONSTANTS --
---------------------------------------------------------------------------------------------------
-- Note: All address in sdb and crossbar are BYTE addresses!
-- Master ports on the wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 3;
constant c_WB_SLAVE_SPEC_ONEWIRE: integer := 0; -- SPEC 1-wire
constant c_WB_SLAVE_SPEC_INFO : integer := 1; -- SPEC CSR
constant c_WB_SLAVE_MASTERFIP : integer := 2; -- masterFIP core
-- SDB header address
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
-- Slave port on the wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 1;
constant c_MASTER_GENNUM : integer := 0;
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(4 downto 0) :=
(0 => f_sdb_embed_device (c_ONEWIRE_SDB_DEVICE, x"00010000"),
1 => f_sdb_embed_device (c_SPEC_INFO_SDB_DEVICE, x"00020000"),
2 => f_sdb_embed_device (c_MASTERFIP_SDB_DEVICE, x"00030000"),
3 => f_sdb_embed_repo_url (c_SDB_REPO_URL),
4 => f_sdb_embed_synthesis (c_SDB_SYNTHESIS_INFO));
---------------------------------------------------------------------------------------------------
-- Signals --
---------------------------------------------------------------------------------------------------
-- clocks
signal clk_20m_vcxo, clk_20m_vcxo_buf : std_logic;
signal clk_100m_sys, pllout_clk_sys : std_logic;
signal pllout_clk_sys_fb : std_logic;
signal sys_locked, pll_status : std_logic;
-- reset
signal rst_sys, rst_sys_n : std_logic;
-- WISHBONE from crossbar master port
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
-- WISHBONE to crossbar slave port
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
signal gn_wb_adr : std_logic_vector(31 downto 0);
-- GN4124
signal gn4124_status : std_logic_vector(31 downto 0);
-- SPEC 1-wire
signal carrier_owr_en, carrier_owr_i : std_logic_vector(c_FMC_ONEWIRE_NB - 1 downto 0);
-- aux
signal aux : std_logic_vector(7 downto 0);
-- LEDs
signal led_clk_100m_divider : unsigned(22 downto 0);
signal led_clk_100m_aux : std_logic_vector(7 downto 0);
signal rx_err, rx_act, fd_txena : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- 100 MHz universal clk generation --
---------------------------------------------------------------------------------------------------
cmp_spec_clk_ibuf : IBUFG
port map
(I => clk_20m_vcxo_i,
O => clk_20m_vcxo_buf);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_sys_clk_pll : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 10, -- 100 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 8,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 16,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 50.0,
REF_JITTER => 0.016)
port map
(CLKFBOUT => pllout_clk_sys_fb,
CLKOUT0 => pllout_clk_sys,
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => sys_locked,
RST => '0',
CLKFBIN => pllout_clk_sys_fb,
CLKIN => clk_20m_vcxo_buf);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_sys_clk_buf : BUFG
port map
(O => clk_100m_sys,
I => pllout_clk_sys);
---------------------------------------------------------------------------------------------------
-- RESET --
---------------------------------------------------------------------------------------------------
cmp_spec_rst_gen : spec_reset_gen
port map
(clk_sys_i => clk_100m_sys,
rst_pcie_n_a_i => rst_n_a_i, -- reset from GN4124 chip
rst_button_n_a_i => button1_i, -- reset from SPEC button
rst_n_o => rst_sys_n);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
rst_sys <= not rst_sys_n;
---------------------------------------------------------------------------------------------------
-- CSR WISHBONE CROSSBAR --
---------------------------------------------------------------------------------------------------
-- 0x00000 -> SDB
-- 0x10000 -> SPEC 1-wire master
-- 0x20000 -> SPEC CSR information
-- 0x30000 -> masterFIP mezzanine SDB
cmp_sdb_crossbar : xwb_sdb_crossbar
generic map
(g_num_masters => c_NUM_WB_SLAVES,
g_num_slaves => c_NUM_WB_MASTERS,
g_registered => true,
g_wraparound => true,
g_layout => c_INTERCONNECT_LAYOUT,
g_sdb_addr => c_SDB_ADDRESS)
port map
(clk_sys_i => clk_100m_sys,
rst_n_i => rst_sys_n,
slave_i => cnx_slave_in,
slave_o => cnx_slave_out,
master_i => cnx_master_in,
master_o => cnx_master_out);
---------------------------------------------------------------------------------------------------
-- GN4124 CORE --
---------------------------------------------------------------------------------------------------
cmp_gn4124_core: gn4124_core
port map
(rst_n_a_i => rst_n_a_i,
status_o => gn4124_status,
-- P2L Direction Source Sync DDR related signals
p2l_clk_p_i => p2l_clk_p_i,
p2l_clk_n_i => p2l_clk_n_i,
p2l_data_i => p2l_data_i,
p2l_dframe_i => p2l_dframe_i,
p2l_valid_i => p2l_valid_i,
-- P2L Control
p2l_rdy_o => p2l_rdy_o,
p_wr_req_i => p_wr_req_i,
p_wr_rdy_o => p_wr_rdy_o,
rx_error_o => rx_error_o,
-- L2P Direction Source Sync DDR related signals
l2p_clk_p_o => l2p_clk_p_o,
l2p_clk_n_o => l2p_clk_n_o,
l2p_data_o => l2p_data_o ,
l2p_dframe_o => l2p_dframe_o,
l2p_valid_o => l2p_valid_o,
l2p_edb_o => l2p_edb_o,
-- L2P Control
l2p_rdy_i => l2p_rdy_i,
l_wr_rdy_i => l_wr_rdy_i,
p_rd_d_rdy_i => p_rd_d_rdy_i,
tx_error_i => tx_error_i,
vc_rdy_i => vc_rdy_i,
-- Interrupt interface
dma_irq_o => open,
irq_p_i => '0',
irq_p_o => irq_p_o,
-- CSR WISHBONE interface (master pipelined)
csr_clk_i => clk_100m_sys,
csr_adr_o => gn_wb_adr,
csr_dat_o => cnx_slave_in(c_MASTER_GENNUM).dat,
csr_sel_o => cnx_slave_in(c_MASTER_GENNUM).sel,
csr_stb_o => cnx_slave_in(c_MASTER_GENNUM).stb,
csr_we_o => cnx_slave_in(c_MASTER_GENNUM).we,
csr_cyc_o => cnx_slave_in(c_MASTER_GENNUM).cyc,
csr_dat_i => cnx_slave_out(c_MASTER_GENNUM).dat,
csr_ack_i => cnx_slave_out(c_MASTER_GENNUM).ack,
csr_stall_i => cnx_slave_out(c_MASTER_GENNUM).stall,
csr_err_i => cnx_slave_out(c_MASTER_GENNUM).err,
csr_rty_i => cnx_slave_out(c_MASTER_GENNUM).rty,
csr_int_i => '0',
-- DMA: not used
dma_clk_i => clk_100m_sys,
dma_adr_o => open,
dma_cyc_o => open,
dma_dat_o => open,
dma_sel_o => open,
dma_stb_o => open,
dma_we_o => open,
dma_err_i => '0',
dma_ack_i => '1',
dma_rty_i => '0',
dma_int_i => '0',
dma_dat_i => (others => '0'),
dma_stall_i => '0',
dma_reg_clk_i => clk_100m_sys,
dma_reg_adr_i => (others => '0'),
dma_reg_dat_i => (others => '0'),
dma_reg_sel_i => (others => '0'),
dma_reg_stb_i => '0',
dma_reg_we_i => '0',
dma_reg_cyc_i => '0',
dma_reg_dat_o => open,
dma_reg_ack_o => open,
dma_reg_stall_o => open);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Convert 32-bit word address into byte address for crossbar
cnx_slave_in(c_MASTER_GENNUM).adr <= gn_wb_adr(29 downto 0) & "00";
---------------------------------------------------------------------------------------------------
-- masterFIP core --
---------------------------------------------------------------------------------------------------
cmp_masterFIP_core : fmc_masterFIP_core
generic map
(g_span => 32,
g_width => 32,
values_for_simul => FALSE)
port map
(clk_i => clk_100m_sys,
rst_i => rst_sys,
-- Bus speed
speed_b0_i => speed_b0_i,
speed_b1_i => speed_b1_i,
-- Bus termination
bus_term_en_n_o => bus_term_en_n_o,
-- FielDrive
fd_rxcdn_i => fd_rxcdn_i,
fd_rxd_i => fd_rxd_i,
fd_txer_i => fd_txer_i,
fd_wdgn_i => fd_wdgn_i,
fd_rstn_o => fd_rstn_o,
fd_txck_o => fd_txck_o,
fd_txd_o => fd_txd_o,
fd_txena_o => fd_txena,
-- External synchronisation pulse transceiver
ext_sync_term_en_o => ext_sync_term_en_o,
ext_sync_dir_o => ext_sync_dir_o,
ext_sync_oe_o => ext_sync_oe_o,
ext_sync_tst_n_o => ext_sync_tst_n_o,
ext_sync_i => ext_sync_i,
-- Power supplies for the ADC
adc_1v8_shdn_n_o => adc_1v8_shdn_n_o,
adc_m5v_shdn_n_o => adc_m5v_shdn_n_o,
adc_5v_en_n_o => adc_5v_en_n_o,
adc_prim_conn_n_o => adc_prim_conn_n_o,
adc_sec_conn_n_o => adc_sec_conn_n_o,
-- WISHBONE interface with the GN4124 core
wb_adr_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).adr,
wb_dat_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).dat,
wb_stb_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).stb,
wb_we_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).we,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).cyc,
wb_sel_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).sel,
wb_dat_o => cnx_master_in(c_WB_SLAVE_MASTERFIP).dat,
wb_ack_o => cnx_master_in(c_WB_SLAVE_MASTERFIP).ack,
wb_stall_o => cnx_master_in(c_WB_SLAVE_MASTERFIP).stall,
-- Aux
aux_o => aux);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_MASTERFIP).err <= '0';
cnx_master_in(c_WB_SLAVE_MASTERFIP).rty <= '0';
cnx_master_in(c_WB_SLAVE_MASTERFIP).int <= '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
fd_txena_o <= fd_txena;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- LEDs font panel
led_tx_err_n_o <= fd_txer_i;
led_tx_act_n_o <= fd_txena;
led_rx_err_n_o <= rx_err;
led_rx_act_n_o <= rx_act;
cmp_rx_err_extend_p: gc_extend_pulse
generic map (g_width => 50000)
port map
(clk_i => clk_100m_sys,
rst_n_i => rst_sys_n,
pulse_i => aux(0),
extended_o => rx_err);
cmp_rx_act_extend_p: gc_extend_pulse
generic map (g_width => 50000)
port map
(clk_i => clk_100m_sys,
rst_n_i => rst_sys_n,
pulse_i => aux(1),
extended_o => rx_act);
---------------------------------------------------------------------------------------------------
-- SPEC 1-wire --
---------------------------------------------------------------------------------------------------
cmp_carrier_onewire : xwb_onewire_master
generic map
(g_interface_mode => CLASSIC,
g_address_granularity => BYTE,
g_num_ports => 1,
g_ow_btp_normal => "5.0",
g_ow_btp_overdrive => "1.0")
port map
(clk_sys_i => clk_100m_sys,
rst_n_i => rst_sys_n,
slave_i => cnx_master_out(c_WB_SLAVE_SPEC_ONEWIRE),
slave_o => cnx_master_in(c_WB_SLAVE_SPEC_ONEWIRE),
desc_o => open,
owr_pwren_o => open,
owr_en_o => carrier_owr_en,
owr_i => carrier_owr_i);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
carrier_onewire_b <= '0' when carrier_owr_en(0) = '1' else 'Z';
carrier_owr_i(0) <= carrier_onewire_b;
---------------------------------------------------------------------------------------------------
-- Carrier CSR information --
---------------------------------------------------------------------------------------------------
-- Information on carrier type, mezzanine presence, pcb version
cmp_carrier_csr : carrier_info
port map
(rst_n_i => rst_sys_n,
clk_sys_i => clk_100m_sys,
wb_adr_i => cnx_master_out(c_WB_SLAVE_SPEC_INFO).adr(3 downto 2),
wb_dat_i => cnx_master_out(c_WB_SLAVE_SPEC_INFO).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_SPEC_INFO).dat,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_SPEC_INFO).cyc,
wb_sel_i => cnx_master_out(c_WB_SLAVE_SPEC_INFO).sel,
wb_stb_i => cnx_master_out(c_WB_SLAVE_SPEC_INFO).stb,
wb_we_i => cnx_master_out(c_WB_SLAVE_SPEC_INFO).we,
wb_ack_o => cnx_master_in(c_WB_SLAVE_SPEC_INFO).ack,
wb_stall_o => cnx_master_in(c_WB_SLAVE_SPEC_INFO).stall,
carrier_info_carrier_pcb_rev_i => pcb_ver_i,
carrier_info_carrier_reserved_i => (others => '0'),
carrier_info_carrier_type_i => c_CARRIER_TYPE,
carrier_info_stat_fmc_pres_i => prsnt_m2c_n_i,
carrier_info_stat_p2l_pll_lck_i => gn4124_status(0),
carrier_info_stat_sys_pll_lck_i => pll_status,
carrier_info_stat_ddr3_cal_done_i => '0',
carrier_info_stat_reserved_i => (others => '0'),
carrier_info_ctrl_led_green_o => open,
carrier_info_ctrl_led_red_o => open,
carrier_info_ctrl_dac_clr_n_o => open,
carrier_info_ctrl_reserved_o => open,
carrier_info_rst_fmc0_n_o => open,
carrier_info_rst_fmc0_n_i => '1',
carrier_info_rst_fmc0_n_load_o => open,
carrier_info_rst_reserved_o => open);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_SPEC_INFO).err <= '0';
cnx_master_in(c_WB_SLAVE_SPEC_INFO).rty <= '0';
cnx_master_in(c_WB_SLAVE_SPEC_INFO).int <= '0';
---------------------------------------------------------------------------------------------------
-- SPEC LEDs --
---------------------------------------------------------------------------------------------------
led_clk_100m_sys: process (clk_100m_sys)
begin
if rising_edge(clk_100m_sys) then
if(rst_sys_n = '0') then
led_clk_100m_aux <= "01111111";
led_clk_100m_divider <= (others => '0');
else
led_clk_100m_divider <= led_clk_100m_divider+ 1;
if(led_clk_100m_divider = 0) then
led_clk_100m_aux <= led_clk_100m_aux(6 downto 0) & led_clk_100m_aux(7);
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
led_green_o <= led_clk_100m_aux(0);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
spec_red_led: gc_extend_pulse
generic map
(g_width => 5000000)
port map
(clk_i => clk_100m_sys,
rst_n_i => rst_sys_n,
pulse_i => (aux(0)),
extended_o => led_red_o);
end rtl;
----------------------------------------------------------------------------------------------------
-- architecture ends
----------------------------------------------------------------------------------------------------
\ No newline at end of file
gateware/top/spec/spec_top_fmc_adc_100Ms.ucf deleted 100644 → 0
View file @ caef7287
#===============================================================================
# The IO Location Constraints
#===============================================================================
#----------------------------------------
# Clock inputs
#----------------------------------------
NET "clk20_vcxo_i" LOC = H12; # CLK25_VCXO
NET "clk20_vcxo_i" IOSTANDARD = "LVCMOS25";
#NET "clk_125m_pllref_n_i" LOC = F10;
#NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
#NET "clk_125m_pllref_p_i" LOC = G9;
#NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
#----------------------------------------
# SFP slot
# !! SFP_TX_DISABLE and SFP_MOD_DEF1 are swapped in V1.1 schematics for control signals
#----------------------------------------
#NET "SFPRX_123_N" LOC = C15;
#NET "SFPRX_123_N" IOSTANDARD = "LVCMOS25";
#NET "SFPRX_123_P" LOC = D15;
#NET "SFPRX_123_P" IOSTANDARD = "LVCMOS25";
#NET "SFPTX_123_N" LOC = A16;
#NET "SFPTX_123_N" IOSTANDARD = "LVCMOS25";
#NET "SFPTX_123_P" LOC = B16;
#NET "SFPTX_123_P" IOSTANDARD = "LVCMOS25";
#NET "SFP_TX_FAULT" LOC = B18;
#NET "SFP_TX_FAULT" IOSTANDARD = "LVCMOS25";
#NET "SFP_TX_DISABLE" LOC = F17;
#NET "SFP_TX_DISABLE" IOSTANDARD = "LVCMOS25";
#NET "SFP_LOS" LOC = D18;
#NET "SFP_LOS" IOSTANDARD = "LVCMOS25";
#NET "SFP_MOD_DEF1" LOC = C17;
#NET "SFP_MOD_DEF1" IOSTANDARD = "LVCMOS25";
#NET "SFP_MOD_DEF0" LOC = G15;
#NET "SFP_MOD_DEF0" IOSTANDARD = "LVCMOS25";
#NET "SFP_MOD_DEF2" LOC = G16;
#NET "SFP_MOD_DEF2" IOSTANDARD = "LVCMOS25";
#NET "SFP_RATE_SELECT" LOC = H14;
#NET "SFP_RATE_SELECT" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# DAC interface (for VCXO)
#----------------------------------------
NET "pll25dac_sync_n_o" LOC = A3;
NET "pll25dac_sync_n_o" IOSTANDARD = "LVCMOS25";
NET "pll20dac_sync_n_o" LOC = B3;
NET "pll20dac_sync_n_o" IOSTANDARD = "LVCMOS25";
NET "plldac_din_o" LOC = C4;
NET "plldac_din_o" IOSTANDARD = "LVCMOS25";
NET "plldac_sclk_o" LOC = A4;
NET "plldac_sclk_o" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# 1-wire thermometer w/ ID
#----------------------------------------
NET "CARRIER_ONE_WIRE_B" LOC = D4;
NET "CARRIER_ONE_WIRE_B" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# GN4124 interface
#----------------------------------------
NET "L_RST_N" LOC = N20;
NET "L_RST_N" IOSTANDARD = "LVCMOS18";
NET "L2P_CLKN" LOC = K22;
NET "L2P_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_CLKP" LOC = K21;
NET "L2P_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_DFRAME" LOC = U22;
NET "L2P_DFRAME" IOSTANDARD = "SSTL18_I";
NET "L2P_EDB" LOC = U20;
NET "L2P_EDB" IOSTANDARD = "SSTL18_I";
NET "L2P_RDY" LOC = U19;
NET "L2P_RDY" IOSTANDARD = "SSTL18_I";
NET "L2P_VALID" LOC = T18;
NET "L2P_VALID" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY[0]" LOC = R20;
NET "L_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY[1]" LOC = T22;
NET "L_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "L_CLKN" LOC = N19;
NET "L_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "L_CLKP" LOC = P20;
NET "L_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_CLKN" LOC = M19;
NET "P2L_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_CLKP" LOC = M20;
NET "P2L_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_DFRAME" LOC = J22;
NET "P2L_DFRAME" IOSTANDARD = "SSTL18_I";
NET "P2L_RDY" LOC = J16;
NET "P2L_RDY" IOSTANDARD = "SSTL18_I";
NET "P2L_VALID" LOC = L19;
NET "P2L_VALID" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY[0]" LOC = N16;
NET "P_RD_D_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY[1]" LOC = P19;
NET "P_RD_D_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY[0]" LOC = L15;
NET "P_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY[1]" LOC = K16;
NET "P_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ[0]" LOC = M22;
NET "P_WR_REQ[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ[1]" LOC = M21;
NET "P_WR_REQ[1]" IOSTANDARD = "SSTL18_I";
NET "RX_ERROR" LOC = J17;
NET "RX_ERROR" IOSTANDARD = "SSTL18_I";
NET "TX_ERROR" LOC = M17;
NET "TX_ERROR" IOSTANDARD = "SSTL18_I";
NET "VC_RDY[0]" LOC = B21;
NET "VC_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "VC_RDY[1]" LOC = B22;
NET "VC_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[0]" LOC = P16;
NET "L2P_DATA[0]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[1]" LOC = P21;
NET "L2P_DATA[1]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[2]" LOC = P18;
NET "L2P_DATA[2]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[3]" LOC = T20;
NET "L2P_DATA[3]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[4]" LOC = V21;
NET "L2P_DATA[4]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[5]" LOC = V19;
NET "L2P_DATA[5]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[6]" LOC = W22;
NET "L2P_DATA[6]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[7]" LOC = Y22;
NET "L2P_DATA[7]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[8]" LOC = P22;
NET "L2P_DATA[8]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[9]" LOC = R22;
NET "L2P_DATA[9]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[10]" LOC = T21;
NET "L2P_DATA[10]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[11]" LOC = T19;
NET "L2P_DATA[11]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[12]" LOC = V22;
NET "L2P_DATA[12]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[13]" LOC = V20;
NET "L2P_DATA[13]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[14]" LOC = W20;
NET "L2P_DATA[14]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[15]" LOC = Y21;
NET "L2P_DATA[15]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[0]" LOC = K20;
NET "P2L_DATA[0]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[1]" LOC = H22;
NET "P2L_DATA[1]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[2]" LOC = H21;
NET "P2L_DATA[2]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[3]" LOC = L17;
NET "P2L_DATA[3]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[4]" LOC = K17;
NET "P2L_DATA[4]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[5]" LOC = G22;
NET "P2L_DATA[5]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[6]" LOC = G20;
NET "P2L_DATA[6]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[7]" LOC = K18;
NET "P2L_DATA[7]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[8]" LOC = K19;
NET "P2L_DATA[8]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[9]" LOC = H20;
NET "P2L_DATA[9]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[10]" LOC = J19;
NET "P2L_DATA[10]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[11]" LOC = E22;
NET "P2L_DATA[11]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[12]" LOC = E20;
NET "P2L_DATA[12]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[13]" LOC = F22;
NET "P2L_DATA[13]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[14]" LOC = F21;
NET "P2L_DATA[14]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[15]" LOC = H19;
NET "P2L_DATA[15]" IOSTANDARD = "SSTL18_I";
NET "GPIO[0]" LOC = U16;
NET "GPIO[0]" IOSTANDARD = "LVCMOS25";
NET "GPIO[1]" LOC = AB19;
NET "GPIO[1]" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# FMC slot
#----------------------------------------
NET "adc0_ext_trigger_n_i" LOC = AB13; # LA17_N
NET "adc0_ext_trigger_n_i" IOSTANDARD = "LVDS_25";
NET "adc0_ext_trigger_p_i" LOC = Y13; # LA17_P
NET "adc0_ext_trigger_p_i" IOSTANDARD = "LVDS_25";
# dco_p and dco_n are swapped compared to the FMC ADC schematics
# this is to be coherent in the hdl design
NET "adc0_dco_n_i" LOC = AB11; # LA00_N
NET "adc0_dco_n_i" IOSTANDARD = "LVDS_25";
NET "adc0_dco_p_i" LOC = Y11; # LA00_P
NET "adc0_dco_p_i" IOSTANDARD = "LVDS_25";
# fr_p and fr_n are swapped compared to the FMC ADC schematics
# this is to be coherent in the hdl design
NET "adc0_fr_n_i" LOC = AB12; # LA01_N
NET "adc0_fr_n_i" IOSTANDARD = "LVDS_25";
NET "adc0_fr_p_i" LOC = AA12; # LA01_P
NET "adc0_fr_p_i" IOSTANDARD = "LVDS_25";
NET "adc0_outa_n_i[0]" LOC = AB4; # LA14_N
NET "adc0_outa_n_i[0]" IOSTANDARD = "LVDS_25";
NET "adc0_outa_p_i[0]" LOC = AA4; # LA14_P
NET "adc0_outa_p_i[0]" IOSTANDARD = "LVDS_25";
NET "adc0_outb_n_i[0]" LOC = W11; # LA15_N
NET "adc0_outb_n_i[0]" IOSTANDARD = "LVDS_25";
NET "adc0_outb_p_i[0]" LOC = V11; # LA15_P
NET "adc0_outb_p_i[0]" IOSTANDARD = "LVDS_25";
NET "adc0_outa_n_i[1]" LOC = Y12; # LA16_N
NET "adc0_outa_n_i[1]" IOSTANDARD = "LVDS_25";
NET "adc0_outa_p_i[1]" LOC = W12; # LA16_P
NET "adc0_outa_p_i[1]" IOSTANDARD = "LVDS_25";
NET "adc0_outb_n_i[1]" LOC = AB9; # LA13_N
NET "adc0_outb_n_i[1]" IOSTANDARD = "LVDS_25";
NET "adc0_outb_p_i[1]" LOC = Y9; # LA13_P
NET "adc0_outb_p_i[1]" IOSTANDARD = "LVDS_25";
NET "adc0_outa_n_i[2]" LOC = AB8; # LA10_N
NET "adc0_outa_n_i[2]" IOSTANDARD = "LVDS_25";
NET "adc0_outa_p_i[2]" LOC = AA8; # LA10_P
NET "adc0_outa_p_i[2]" IOSTANDARD = "LVDS_25";
NET "adc0_outb_n_i[2]" LOC = AB7; # LA09_N
NET "adc0_outb_n_i[2]" IOSTANDARD = "LVDS_25";
NET "adc0_outb_p_i[2]" LOC = Y7; # LA09_P
NET "adc0_outb_p_i[2]" IOSTANDARD = "LVDS_25";
NET "adc0_outa_n_i[3]" LOC = V9; # LA07_N
NET "adc0_outa_n_i[3]" IOSTANDARD = "LVDS_25";
NET "adc0_outa_p_i[3]" LOC = U9; # LA07_P
NET "adc0_outa_p_i[3]" IOSTANDARD = "LVDS_25";
NET "adc0_outb_n_i[3]" LOC = AB6; # LA05_N
NET "adc0_outb_n_i[3]" IOSTANDARD = "LVDS_25";
NET "adc0_outb_p_i[3]" LOC = AA6; # LA05_P
NET "adc0_outb_p_i[3]" IOSTANDARD = "LVDS_25";
NET "adc0_spi_din_i" LOC = T15; # LA25_P
NET "adc0_spi_din_i" IOSTANDARD = "LVCMOS25";
NET "adc0_spi_dout_o" LOC = C18; # LA31_N
NET "adc0_spi_dout_o" IOSTANDARD = "LVCMOS25";
NET "adc0_spi_sck_o" LOC = D17; # LA31_P
NET "adc0_spi_sck_o" IOSTANDARD = "LVCMOS25";
NET "adc0_spi_cs_adc_n_o" LOC = V17; # LA30_P
NET "adc0_spi_cs_adc_n_o" IOSTANDARD = "LVCMOS25";
NET "adc0_spi_cs_dac1_n_o" LOC = B20; # LA32_P
NET "adc0_spi_cs_dac1_n_o" IOSTANDARD = "LVCMOS25";
NET "adc0_spi_cs_dac2_n_o" LOC = A20; # LA32_N
NET "adc0_spi_cs_dac2_n_o" IOSTANDARD = "LVCMOS25";
NET "adc0_spi_cs_dac3_n_o" LOC = C19; # LA33_P
NET "adc0_spi_cs_dac3_n_o" IOSTANDARD = "LVCMOS25";
NET "adc0_spi_cs_dac4_n_o" LOC = A19; # LA33_N
NET "adc0_spi_cs_dac4_n_o" IOSTANDARD = "LVCMOS25";
NET "adc0_gpio_dac_clr_n_o" LOC = W18; # LA30_N
NET "adc0_gpio_dac_clr_n_o" IOSTANDARD = "LVCMOS25";
NET "adc0_gpio_led_acq_o" LOC = W15; # LA28_N
NET "adc0_gpio_led_acq_o" IOSTANDARD = "LVCMOS25";
NET "adc0_gpio_led_trig_o" LOC = Y16; # LA28_P
NET "adc0_gpio_led_trig_o" IOSTANDARD = "LVCMOS25";
NET "adc0_gpio_ssr_ch1_o[0]" LOC = Y17; # LA26_P
NET "adc0_gpio_ssr_ch1_o[0]" IOSTANDARD = "LVCMOS25";
NET "adc0_gpio_ssr_ch1_o[1]" LOC = AB17; # LA26_N
NET "adc0_gpio_ssr_ch1_o[1]" IOSTANDARD = "LVCMOS25";
NET "adc0_gpio_ssr_ch1_o[2]" LOC = AB18; # LA27_N
NET "adc0_gpio_ssr_ch1_o[2]" IOSTANDARD = "LVCMOS25";
NET "adc0_gpio_ssr_ch1_o[3]" LOC = U15; # LA25_N
NET "adc0_gpio_ssr_ch1_o[3]" IOSTANDARD = "LVCMOS25";
NET "adc0_gpio_ssr_ch1_o[4]" LOC = W14; # LA24_P
NET "adc0_gpio_ssr_ch1_o[4]" IOSTANDARD = "LVCMOS25";
NET "adc0_gpio_ssr_ch1_o[5]" LOC = Y14; # LA24_N
NET "adc0_gpio_ssr_ch1_o[5]" IOSTANDARD = "LVCMOS25";
NET "adc0_gpio_ssr_ch1_o[6]" LOC = W17; # LA29_P
NET "adc0_gpio_ssr_ch1_o[6]" IOSTANDARD = "LVCMOS25";
NET "adc0_gpio_ssr_ch2_o[0]" LOC = R11; # LA20_P
NET "adc0_gpio_ssr_ch2_o[0]" IOSTANDARD = "LVCMOS25";
NET "adc0_gpio_ssr_ch2_o[1]" LOC = AB15; # LA19_N
NET "adc0_gpio_ssr_ch2_o[1]" IOSTANDARD = "LVCMOS25";
NET "adc0_gpio_ssr_ch2_o[2]" LOC = R13; # LA22_P
NET "adc0_gpio_ssr_ch2_o[2]" IOSTANDARD = "LVCMOS25";
NET "adc0_gpio_ssr_ch2_o[3]" LOC = T14; # LA22_N
NET "adc0_gpio_ssr_ch2_o[3]" IOSTANDARD = "LVCMOS25";
NET "adc0_gpio_ssr_ch2_o[4]" LOC = V13; # LA21_P
NET "adc0_gpio_ssr_ch2_o[4]" IOSTANDARD = "LVCMOS25";
NET "adc0_gpio_ssr_ch2_o[5]" LOC = AA18; # LA27_P
NET "adc0_gpio_ssr_ch2_o[5]" IOSTANDARD = "LVCMOS25";
NET "adc0_gpio_ssr_ch2_o[6]" LOC = W13; # LA21_N
NET "adc0_gpio_ssr_ch2_o[6]" IOSTANDARD = "LVCMOS25";
NET "adc0_gpio_ssr_ch3_o[0]" LOC = R9; # LA08_P
NET "adc0_gpio_ssr_ch3_o[0]" IOSTANDARD = "LVCMOS25";
NET "adc0_gpio_ssr_ch3_o[1]" LOC = R8; # LA08_N
NET "adc0_gpio_ssr_ch3_o[1]" IOSTANDARD = "LVCMOS25";
NET "adc0_gpio_ssr_ch3_o[2]" LOC = T10; # LA12_P
NET "adc0_gpio_ssr_ch3_o[2]" IOSTANDARD = "LVCMOS25";
NET "adc0_gpio_ssr_ch3_o[3]" LOC = U10; # LA12_N
NET "adc0_gpio_ssr_ch3_o[3]" IOSTANDARD = "LVCMOS25";
NET "adc0_gpio_ssr_ch3_o[4]" LOC = W10; # LA11_P
NET "adc0_gpio_ssr_ch3_o[4]" IOSTANDARD = "LVCMOS25";
NET "adc0_gpio_ssr_ch3_o[5]" LOC = Y10; # LA11_N
NET "adc0_gpio_ssr_ch3_o[5]" IOSTANDARD = "LVCMOS25";
NET "adc0_gpio_ssr_ch3_o[6]" LOC = T11; # LA20_N
NET "adc0_gpio_ssr_ch3_o[6]" IOSTANDARD = "LVCMOS25";
NET "adc0_gpio_ssr_ch4_o[0]" LOC = W6; # LA02_P
NET "adc0_gpio_ssr_ch4_o[0]" IOSTANDARD = "LVCMOS25";
NET "adc0_gpio_ssr_ch4_o[1]" LOC = Y6; # LA02_N
NET "adc0_gpio_ssr_ch4_o[1]" IOSTANDARD = "LVCMOS25";
NET "adc0_gpio_ssr_ch4_o[2]" LOC = V7; # LA03_P
NET "adc0_gpio_ssr_ch4_o[2]" IOSTANDARD = "LVCMOS25";
NET "adc0_gpio_ssr_ch4_o[3]" LOC = W8; # LA03_N
NET "adc0_gpio_ssr_ch4_o[3]" IOSTANDARD = "LVCMOS25";
NET "adc0_gpio_ssr_ch4_o[4]" LOC = T8; # LA04_P
NET "adc0_gpio_ssr_ch4_o[4]" IOSTANDARD = "LVCMOS25";
NET "adc0_gpio_ssr_ch4_o[5]" LOC = Y5; # LA06_P
NET "adc0_gpio_ssr_ch4_o[5]" IOSTANDARD = "LVCMOS25";
NET "adc0_gpio_ssr_ch4_o[6]" LOC = U8; # LA04_N
NET "adc0_gpio_ssr_ch4_o[6]" IOSTANDARD = "LVCMOS25";
NET "adc0_gpio_si570_oe_o" LOC = AB5; # LA06_N
NET "adc0_gpio_si570_oe_o" IOSTANDARD = "LVCMOS25";
NET "adc0_si570_scl_b" LOC = U12; # LA18_N
NET "adc0_si570_scl_b" IOSTANDARD = "LVCMOS25";
NET "adc0_si570_sda_b" LOC = T12; # LA18_P
NET "adc0_si570_sda_b" IOSTANDARD = "LVCMOS25";
NET "adc0_one_wire_b" LOC = Y18; # LA29_N
NET "adc0_one_wire_b" IOSTANDARD = "LVCMOS25";
NET "fmc0_prsnt_m2c_n_i" LOC = AB14; # PRSNT_M2C_L
NET "fmc0_prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_sys_scl_b" LOC = F7; # SCL
NET "fmc0_sys_scl_b" IOSTANDARD = "LVCMOS25";
NET "fmc0_sys_sda_b" LOC = F8; # SDA
NET "fmc0_sys_sda_b" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# FMC slot (unused pins)
#----------------------------------------
#NET "PG_C2M" LOC = AA14;
#NET "PG_C2M" IOSTANDARD = "LVCMOS25";
#NET "LA19_P" LOC = Y15;
#NET "LA19_P" IOSTANDARD = "LVCMOS25";
#NET "LA23_N" LOC = AB16;
#NET "LA23_N" IOSTANDARD = "LVCMOS25";
#NET "LA23_P" LOC = AA16;
#NET "LA23_P" IOSTANDARD = "LVCMOS25";
#NET "TDO_FROM_FMC" LOC = F9;
#NET "TDO_FROM_FMC" IOSTANDARD = "LVCMOS25";
#NET "TCK_TO_FMC" LOC = G8;
#NET "TCK_TO_FMC" IOSTANDARD = "LVCMOS25";
#NET "TDI_TO_FMC" LOC = H11;
#NET "TDI_TO_FMC" IOSTANDARD = "LVCMOS25";
#NET "TMS_TO_FMC" LOC = H10;
#NET "TMS_TO_FMC" IOSTANDARD = "LVCMOS25";
#NET "TRST_TO_FMC" LOC = E6;
#NET "TRST_TO_FMC" IOSTANDARD = "LVCMOS25";
#NET "CLK0_M2C_P" LOC = E16;
#NET "CLK0_M2C_P" IOSTANDARD = "LVDS_25";
#NET "CLK0_M2C_N" LOC = F16;
#NET "CLK0_M2C_N" IOSTANDARD = "LVDS_25";
#NET "CLK1_M2C_P" LOC = L20;
#NET "CLK1_M2C_P" IOSTANDARD = "LVDS_18";
#NET "CLK1_M2C_N" LOC = L22;
#NET "CLK1_M2C_N" IOSTANDARD = "LVDS_18";
#----------------------------------------
# SI57x interface
#----------------------------------------
#NET "SI57X_SCL" LOC = A18;
#NET "SI57X_SCL" IOSTANDARD = "LVCMOS25";
#NET "SI57X_SDA" LOC = A17;
#NET "SI57X_SDA" IOSTANDARD = "LVCMOS25";
#NET "SI57X_OE" LOC = H13;
#NET "SI57X_OE" IOSTANDARD = "LVCMOS25";
#NET "SI57X_CLK_N" LOC = F15;
#NET "SI57X_CLK_N" IOSTANDARD = "LVDS_25";
#NET "SI57X_CLK_P" LOC = F14;
#NET "SI57X_CLK_P" IOSTANDARD = "LVDS_25";
#----------------------------------------
# Carrier front panel LEDs
#----------------------------------------
NET "led_red_o" LOC = D5;
NET "led_red_o" IOSTANDARD = "LVCMOS25";
NET "led_green_o" LOC = E5;
NET "led_green_o" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# PCB version number (coded with resistors)
#----------------------------------------
NET "pcb_ver_i[0]" LOC = P5;
NET "pcb_ver_i[0]" IOSTANDARD = "LVCMOS15";
NET "pcb_ver_i[1]" LOC = P4;
NET "pcb_ver_i[1]" IOSTANDARD = "LVCMOS15";
NET "pcb_ver_i[2]" LOC = AA2;
NET "pcb_ver_i[2]" IOSTANDARD = "LVCMOS15";
NET "pcb_ver_i[3]" LOC = AA1;
NET "pcb_ver_i[3]" IOSTANDARD = "LVCMOS15";
#----------------------------------------
# DDR3 interface
#----------------------------------------
NET "DDR3_CAS_N" LOC = M4;
NET "DDR3_CAS_N" IOSTANDARD = "SSTL15_II";
NET "DDR3_CK_N" LOC = K3;
NET "DDR3_CK_N" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_CK_P" LOC = K4;
NET "DDR3_CK_P" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_CKE" LOC = F2;
NET "DDR3_CKE" IOSTANDARD = "SSTL15_II";
NET "DDR3_LDM" LOC = N4;
NET "DDR3_LDM" IOSTANDARD = "SSTL15_II";
NET "DDR3_LDQS_N" LOC = N1;
NET "DDR3_LDQS_N" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_LDQS_P" LOC = N3;
NET "DDR3_LDQS_P" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_ODT" LOC = L6;
NET "DDR3_ODT" IOSTANDARD = "SSTL15_II";
NET "DDR3_RAS_N" LOC = M5;
NET "DDR3_RAS_N" IOSTANDARD = "SSTL15_II";
NET "DDR3_RESET_N" LOC = E3;
NET "DDR3_RESET_N" IOSTANDARD = "SSTL15_II";
NET "DDR3_UDM" LOC = P3;
NET "DDR3_UDM" IOSTANDARD = "SSTL15_II";
NET "DDR3_UDQS_N" LOC = V1;
NET "DDR3_UDQS_N" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_UDQS_P" LOC = V2;
NET "DDR3_UDQS_P" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_WE_N" LOC = H2;
NET "DDR3_WE_N" IOSTANDARD = "SSTL15_II";
NET "DDR3_RZQ" LOC = K7;
NET "DDR3_RZQ" IOSTANDARD = "SSTL15_II";
NET "DDR3_ZIO" LOC = M7;
NET "DDR3_ZIO" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[0]" LOC = K2;
NET "DDR3_A[0]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[1]" LOC = K1;
NET "DDR3_A[1]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[2]" LOC = K5;
NET "DDR3_A[2]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[3]" LOC = M6;
NET "DDR3_A[3]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[4]" LOC = H3;
NET "DDR3_A[4]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[5]" LOC = M3;
NET "DDR3_A[5]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[6]" LOC = L4;
NET "DDR3_A[6]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[7]" LOC = K6;
NET "DDR3_A[7]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[8]" LOC = G3;
NET "DDR3_A[8]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[9]" LOC = G1;
NET "DDR3_A[9]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[10]" LOC = J4;
NET "DDR3_A[10]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[11]" LOC = E1;
NET "DDR3_A[11]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[12]" LOC = F1;
NET "DDR3_A[12]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[13]" LOC = J6;
NET "DDR3_A[13]" IOSTANDARD = "SSTL15_II";
#NET "DDR3_A[14]" LOC = H5;
#NET "DDR3_A[14]" IOSTANDARD = "SSTL15_II";
NET "DDR3_BA[0]" LOC = J3;
NET "DDR3_BA[0]" IOSTANDARD = "SSTL15_II";
NET "DDR3_BA[1]" LOC = J1;
NET "DDR3_BA[1]" IOSTANDARD = "SSTL15_II";
NET "DDR3_BA[2]" LOC = H1;
NET "DDR3_BA[2]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[0]" LOC = R3;
NET "DDR3_DQ[0]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[1]" LOC = R1;
NET "DDR3_DQ[1]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[2]" LOC = P2;
NET "DDR3_DQ[2]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[3]" LOC = P1;
NET "DDR3_DQ[3]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[4]" LOC = L3;
NET "DDR3_DQ[4]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[5]" LOC = L1;
NET "DDR3_DQ[5]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[6]" LOC = M2;
NET "DDR3_DQ[6]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[7]" LOC = M1;
NET "DDR3_DQ[7]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[8]" LOC = T2;
NET "DDR3_DQ[8]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[9]" LOC = T1;
NET "DDR3_DQ[9]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[10]" LOC = U3;
NET "DDR3_DQ[10]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[11]" LOC = U1;
NET "DDR3_DQ[11]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[12]" LOC = W3;
NET "DDR3_DQ[12]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[13]" LOC = W1;
NET "DDR3_DQ[13]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[14]" LOC = Y2;
NET "DDR3_DQ[14]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[15]" LOC = Y1;
NET "DDR3_DQ[15]" IOSTANDARD = "SSTL15_II";
#----------------------------------------
# UART
#----------------------------------------
#NET "UART_TXD" LOC = A2; # FPGA input
#NET "UART_TXD" IOSTANDARD = "LVCMOS25";
#NET "UART_RXD" LOC = B2; # FPGA output
#NET "UART_RXD" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# Buttons and LEDs
#----------------------------------------
NET "AUX_BUTTONS_I[0]" LOC = C22;
NET "AUX_BUTTONS_I[0]" IOSTANDARD = "LVCMOS18";
NET "AUX_BUTTONS_I[1]" LOC = D21;
NET "AUX_BUTTONS_I[1]" IOSTANDARD = "LVCMOS18";
NET "AUX_LEDS_O[0]" LOC = G19;
NET "AUX_LEDS_O[0]" IOSTANDARD = "LVCMOS18";
NET "AUX_LEDS_O[1]" LOC = F20;
NET "AUX_LEDS_O[1]" IOSTANDARD = "LVCMOS18";
NET "AUX_LEDS_O[2]" LOC = F18;
NET "AUX_LEDS_O[2]" IOSTANDARD = "LVCMOS18";
NET "AUX_LEDS_O[3]" LOC = C20;
NET "AUX_LEDS_O[3]" IOSTANDARD = "LVCMOS18";
#===============================================================================
# IOBs
#===============================================================================
INST "cmp_gn4124_core/l2p_rdy_t" IOB=FALSE;
INST "cmp_gn4124_core/l_wr_rdy_t*" IOB=FALSE;
INST "cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/s_out" IOB=FALSE;
INST "cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/clgen/clk_out" IOB=FALSE;
#===============================================================================
# Terminations
#===============================================================================
# DDR3
NET "DDR3_DQ[*]" IN_TERM = NONE;
NET "DDR3_LDQS_P" IN_TERM = NONE;
NET "DDR3_LDQS_N" IN_TERM = NONE;
NET "DDR3_UDQS_P" IN_TERM = NONE;
NET "DDR3_UDQS_N" IN_TERM = NONE;
#===============================================================================
# Timing constraints
#===============================================================================
# GN4124
#NET "L_CLKp" TNM_NET = "l_clkp_grp";
#TIMESPEC TS_l_clkp = PERIOD "l_clkp_grp" 5 ns HIGH 50%;
NET "P2L_CLKp" TNM_NET = "p2l_clkp_grp";
TIMESPEC TS_p2l_clkp = PERIOD "p2l_clkp_grp" 5 ns HIGH 50%;
NET "P2L_CLKn" TNM_NET = "p2l_clkn_grp";
TIMESPEC TS_p2l_clkn = PERIOD "p2l_clkn_grp" 5 ns HIGH 50%;
NET "L2P_CLKN" TNM = "gn4124_data_bus_out";
NET "L2P_CLKP" TNM = "gn4124_data_bus_out";
NET "L2P_VALID" TNM = "gn4124_data_bus_out";
NET "L2P_DFRAME" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[0]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[1]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[2]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[3]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[4]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[5]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[6]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[7]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[8]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[9]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[10]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[11]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[12]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[13]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[14]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[15]" TNM = "gn4124_data_bus_out";
#TIMEGRP "gn4124_data_bus_out" OFFSET = OUT AFTER "cmp_gn4124_core/io_clk" REFERENCE_PIN "L2P_CLKP";
NET "P2L_CLKN" TNM = "gn4124_data_bus_in";
NET "P2L_CLKP" TNM = "gn4124_data_bus_in";
NET "P2L_DFRAME" TNM = "gn4124_data_bus_in";
NET "P2L_VALID" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[0]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[1]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[2]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[3]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[4]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[5]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[6]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[7]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[8]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[9]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[10]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[11]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[12]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[13]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[14]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[15]" TNM = "gn4124_data_bus_in";
#TIMEGRP "gn4124_data_bus_in" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE "cmp_gn4124_core/io_clk" RISING;
#TIMEGRP "gn4124_data_bus_in" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE "cmp_gn4124_core/io_clk" FALLING;
# System clock
NET "clk20_vcxo_i" TNM_NET = "clk20_vcxo_i_grp";
TIMESPEC TS_clk20_vcxo_i = PERIOD "clk20_vcxo_i_grp" 50 ns HIGH 50%;
# DDR3
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK5";
TIMESPEC "TS_SYS_CLK5" = PERIOD "SYS_CLK5" 3.0 ns HIGH 50 %;
# ADC
NET "adc0_dco_n_i" TNM_NET = adc_dco_n_i;
TIMESPEC TS_adc_dco_n_i = PERIOD "adc_dco_n_i" 2 ns HIGH 50%;
#===============================================================================
# False Path
#===============================================================================
# GN4124
NET "l_rst_n" TIG;
NET "cmp_gn4124_core/rst_*" TIG;
# DDR3
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/c3_pll_lock" TIG;
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/hard_done_cal" TIG;
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
# Reset
NET "powerup_rst_n" TIG;
NET "sw_rst_fmc0_n" TIG;
gateware/top/spec/spec_top_fmc_adc_100Ms.vhd deleted 100644 → 0
View file @ caef7287
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Top level entity for Simple PCIe FMC Carrier
-- http://www.ohwr.org/projects/spec
--------------------------------------------------------------------------------
--
-- unit name: spec_top_fmc_adc_100Ms (spec_top_fmc_adc_100Ms.vhd)
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 24-02-2011
--
-- version: see sdb_meta_pkg.vhd
--
-- description: Top entity of FMC ADC 100Ms/s design for SPEC board.
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see git log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.vcomponents.all;
library work;
use work.gn4124_core_pkg.all;
use work.ddr3_ctrl_pkg.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.fmc_adc_mezzanine_pkg.all;
use work.sdb_meta_pkg.all;
use work.timetag_core_pkg.all;
entity spec_top_fmc_adc_100Ms is
generic(
g_SIMULATION : string := "FALSE";
g_CALIB_SOFT_IP : string := "TRUE");
port
(
-- Local oscillator
clk20_vcxo_i : in std_logic; -- 20MHz VCXO clock
-- DAC interface (20MHz and 25MHz VCXO)
pll25dac_sync_n_o : out std_logic; -- 25MHz VCXO
pll20dac_sync_n_o : out std_logic; -- 20MHz VCXO
plldac_din_o : out std_logic;
plldac_sclk_o : out std_logic;
-- Carrier font panel LEDs
led_red_o : out std_logic;
led_green_o : out std_logic;
-- Auxiliary pins
aux_leds_o : out std_logic_vector(3 downto 0);
aux_buttons_i : in std_logic_vector(1 downto 0);
-- PCB version
pcb_ver_i : in std_logic_vector(3 downto 0);
-- Carrier 1-wire interface (DS18B20 thermometer + unique ID)
carrier_one_wire_b : inout std_logic;
-- GN4124 interface
L_CLKp : in std_logic; -- Local bus clock (frequency set in GN4124 config registers)
L_CLKn : in std_logic; -- Local bus clock (frequency set in GN4124 config registers)
L_RST_N : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
P2L_RDY : out std_logic; -- Rx Buffer Full Flag
P2L_CLKn : in std_logic; -- Receiver Source Synchronous Clock-
P2L_CLKp : in std_logic; -- Receiver Source Synchronous Clock+
P2L_DATA : in std_logic_vector(15 downto 0); -- Parallel receive data
P2L_DFRAME : in std_logic; -- Receive Frame
P2L_VALID : in std_logic; -- Receive Data Valid
P_WR_REQ : in std_logic_vector(1 downto 0); -- PCIe Write Request
P_WR_RDY : out std_logic_vector(1 downto 0); -- PCIe Write Ready
RX_ERROR : out std_logic; -- Receive Error
L2P_DATA : out std_logic_vector(15 downto 0); -- Parallel transmit data
L2P_DFRAME : out std_logic; -- Transmit Data Frame
L2P_VALID : out std_logic; -- Transmit Data Valid
L2P_CLKn : out std_logic; -- Transmitter Source Synchronous Clock-
L2P_CLKp : out std_logic; -- Transmitter Source Synchronous Clock+
L2P_EDB : out std_logic; -- Packet termination and discard
L2P_RDY : in std_logic; -- Tx Buffer Full Flag
L_WR_RDY : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
P_RD_D_RDY : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
TX_ERROR : in std_logic; -- Transmit Error
VC_RDY : in std_logic_vector(1 downto 0); -- Channel ready
GPIO : inout std_logic_vector(1 downto 0); -- GPIO[0] -> GN4124 GPIO8
-- GPIO[1] -> GN4124 GPIO9
-- DDR3 interface
DDR3_CAS_N : out std_logic;
DDR3_CK_N : out std_logic;
DDR3_CK_P : out std_logic;
DDR3_CKE : out std_logic;
DDR3_LDM : out std_logic;
DDR3_LDQS_N : inout std_logic;
DDR3_LDQS_P : inout std_logic;
DDR3_ODT : out std_logic;
DDR3_RAS_N : out std_logic;
DDR3_RESET_N : out std_logic;
DDR3_UDM : out std_logic;
DDR3_UDQS_N : inout std_logic;
DDR3_UDQS_P : inout std_logic;
DDR3_WE_N : out std_logic;
DDR3_DQ : inout std_logic_vector(15 downto 0);
DDR3_A : out std_logic_vector(13 downto 0);
DDR3_BA : out std_logic_vector(2 downto 0);
DDR3_ZIO : inout std_logic;
DDR3_RZQ : inout std_logic;
-- FMC slot
adc0_ext_trigger_p_i : in std_logic; -- External trigger
adc0_ext_trigger_n_i : in std_logic;
adc0_dco_p_i : in std_logic; -- ADC data clock
adc0_dco_n_i : in std_logic;
adc0_fr_p_i : in std_logic; -- ADC frame start
adc0_fr_n_i : in std_logic;
adc0_outa_p_i : in std_logic_vector(3 downto 0); -- ADC serial data (odd bits)
adc0_outa_n_i : in std_logic_vector(3 downto 0);
adc0_outb_p_i : in std_logic_vector(3 downto 0); -- ADC serial data (even bits)
adc0_outb_n_i : in std_logic_vector(3 downto 0);
adc0_spi_din_i : in std_logic; -- SPI data from FMC
adc0_spi_dout_o : out std_logic; -- SPI data to FMC
adc0_spi_sck_o : out std_logic; -- SPI clock
adc0_spi_cs_adc_n_o : out std_logic; -- SPI ADC chip select (active low)
adc0_spi_cs_dac1_n_o : out std_logic; -- SPI channel 1 offset DAC chip select (active low)
adc0_spi_cs_dac2_n_o : out std_logic; -- SPI channel 2 offset DAC chip select (active low)
adc0_spi_cs_dac3_n_o : out std_logic; -- SPI channel 3 offset DAC chip select (active low)
adc0_spi_cs_dac4_n_o : out std_logic; -- SPI channel 4 offset DAC chip select (active low)
adc0_gpio_dac_clr_n_o : out std_logic; -- offset DACs clear (active low)
adc0_gpio_led_acq_o : out std_logic; -- Mezzanine front panel power LED (PWR)
adc0_gpio_led_trig_o : out std_logic; -- Mezzanine front panel trigger LED (TRIG)
adc0_gpio_ssr_ch1_o : out std_logic_vector(6 downto 0); -- Channel 1 solid state relays control
adc0_gpio_ssr_ch2_o : out std_logic_vector(6 downto 0); -- Channel 2 solid state relays control
adc0_gpio_ssr_ch3_o : out std_logic_vector(6 downto 0); -- Channel 3 solid state relays control
adc0_gpio_ssr_ch4_o : out std_logic_vector(6 downto 0); -- Channel 4 solid state relays control
adc0_gpio_si570_oe_o : out std_logic; -- Si570 (programmable oscillator) output enable
adc0_si570_scl_b : inout std_logic; -- I2C bus clock (Si570)
adc0_si570_sda_b : inout std_logic; -- I2C bus data (Si570)
adc0_one_wire_b : inout std_logic; -- Mezzanine 1-wire interface (DS18B20 thermometer + unique ID)
-- FMC slot management
fmc0_prsnt_m2c_n_i : in std_logic; -- Mezzanine present (active low)
fmc0_sys_scl_b : inout std_logic; -- Mezzanine system I2C clock (EEPROM)
fmc0_sys_sda_b : inout std_logic -- Mezzanine system I2C data (EEPROM)
);
end spec_top_fmc_adc_100Ms;
architecture rtl of spec_top_fmc_adc_100Ms is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component carrier_csr
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
carrier_csr_carrier_pcb_rev_i : in std_logic_vector(3 downto 0);
carrier_csr_carrier_reserved_i : in std_logic_vector(11 downto 0);
carrier_csr_carrier_type_i : in std_logic_vector(15 downto 0);
carrier_csr_stat_fmc_pres_i : in std_logic;
carrier_csr_stat_p2l_pll_lck_i : in std_logic;
carrier_csr_stat_sys_pll_lck_i : in std_logic;
carrier_csr_stat_ddr3_cal_done_i : in std_logic;
carrier_csr_ctrl_led_green_o : out std_logic;
carrier_csr_ctrl_led_red_o : out std_logic;
carrier_csr_ctrl_dac_clr_n_o : out std_logic;
carrier_csr_rst_fmc0_n_o : out std_logic;
carrier_csr_rst_fmc0_n_i : in std_logic;
carrier_csr_rst_fmc0_n_load_o : out std_logic
);
end component carrier_csr;
component dma_eic
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
irq_dma_done_i : in std_logic;
irq_dma_error_i : in std_logic
);
end component dma_eic;
------------------------------------------------------------------------------
-- SDB crossbar constants declaration
--
-- WARNING: All address in sdb and crossbar are BYTE addresses!
------------------------------------------------------------------------------
-- Number of master port(s) on the wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 6;
-- Number of slave port(s) on the wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 1;
-- Wishbone master(s)
constant c_MASTER_GENNUM : integer := 0;
-- Wishbone slave(s)
constant c_WB_SLAVE_DMA : integer := 0; -- DMA controller in the Gennum core
constant c_WB_SLAVE_ONEWIRE : integer := 1; -- Carrier onewire interface
constant c_WB_SLAVE_SPEC_CSR : integer := 2; -- SPEC control and status registers
constant c_WB_SLAVE_VIC : integer := 3; -- Vectored interrupt controller
constant c_WB_SLAVE_DMA_EIC : integer := 4; -- DMA interrupt controller
constant c_WB_SLAVE_FMC_ADC : integer := 5; -- FMC ADC mezzanine
-- Devices sdb description
constant c_wb_dma_ctrl_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000003F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000601",
version => x"00000001",
date => x"20121116",
name => "WB-DMA.Control ")));
constant c_wb_spec_csr_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000001F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000603",
version => x"00000001",
date => x"20121116",
name => "WB-SPEC-CSR ")));
constant c_wb_dma_eic_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000000F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"d5735ab4", -- echo "WB-DMA.EIC " | md5sum | cut -c1-8
version => x"00000001",
date => x"20131204",
name => "WB-DMA.EIC ")));
-- f_xwb_bridge_manual_sdb(size, sdb_addr)
-- Note: sdb_addr is the sdb records address relative to the bridge base address
constant c_fmc0_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00001fff", x"00000000");
-- sdb header address
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
-- Wishbone crossbar layout
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(8 downto 0) :=
(
0 => f_sdb_embed_device(c_wb_dma_ctrl_sdb, x"00001000"),
1 => f_sdb_embed_device(c_xwb_onewire_master_sdb, x"00001100"),
2 => f_sdb_embed_device(c_wb_spec_csr_sdb, x"00001200"),
3 => f_sdb_embed_device(c_xwb_vic_sdb, x"00001300"),
4 => f_sdb_embed_device(c_wb_dma_eic_sdb, x"00001400"),
5 => f_sdb_embed_bridge(c_fmc0_bridge_sdb, x"00002000"),
6 => f_sdb_embed_repo_url(c_repo_url_sdb),
7 => f_sdb_embed_synthesis(c_synthesis_sdb),
8 => f_sdb_embed_integration(c_integration_sdb)
);
-- VIC default vector setting
constant c_VIC_VECTOR_TABLE : t_wishbone_address_array(0 to 1) :=
(0 => x"00003500",
1 => x"00001400");
------------------------------------------------------------------------------
-- Other constants declaration
------------------------------------------------------------------------------
-- SPEC carrier CSR constants
constant c_CARRIER_TYPE : std_logic_vector(15 downto 0) := X"0001";
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
-- System clock
signal sys_clk_in : std_logic;
signal sys_clk_125_buf : std_logic;
signal sys_clk_250_buf : std_logic;
signal sys_clk_125 : std_logic;
signal sys_clk_250 : std_logic;
signal sys_clk_fb : std_logic;
signal sys_clk_pll_locked : std_logic;
-- DDR3 clock
signal ddr_clk : std_logic;
signal ddr_clk_buf : std_logic;
-- LCLK from GN4124
signal l_clk : std_logic;
-- Reset
signal powerup_reset_cnt : unsigned(7 downto 0) := "00000000";
signal powerup_rst_n : std_logic := '0';
signal sw_rst_fmc0_n : std_logic := '1';
signal sw_rst_fmc0_n_o : std_logic;
signal sw_rst_fmc0_n_i : std_logic;
signal sw_rst_fmc0_n_load : std_logic;
signal sys_rst_n : std_logic;
signal fmc0_rst_n : std_logic;
-- Wishbone buse(s) from crossbar master port(s)
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
-- Wishbone buse(s) to crossbar slave port(s)
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
-- Wishbone address from GN4124 core (32-bit word address)
signal gn_wb_adr : std_logic_vector(31 downto 0);
-- Wishbone address from to DMA controller (32-bit word address)
signal dma_ctrl_wb_adr : std_logic_vector(31 downto 0);
-- GN4124 core DMA port to DDR wishbone bus
signal wb_dma_adr : std_logic_vector(31 downto 0);
signal wb_dma_dat_i : std_logic_vector(31 downto 0);
signal wb_dma_dat_o : std_logic_vector(31 downto 0);
signal wb_dma_sel : std_logic_vector(3 downto 0);
signal wb_dma_cyc : std_logic;
signal wb_dma_stb : std_logic;
signal wb_dma_we : std_logic;
signal wb_dma_ack : std_logic;
signal wb_dma_stall : std_logic;
signal wb_dma_err : std_logic;
signal wb_dma_rty : std_logic;
signal wb_dma_int : std_logic;
-- FMC ADC core to DDR wishbone bus
signal wb_ddr_adr : std_logic_vector(31 downto 0);
signal wb_ddr_dat_o : std_logic_vector(63 downto 0);
signal wb_ddr_sel : std_logic_vector(7 downto 0);
signal wb_ddr_cyc : std_logic;
signal wb_ddr_stb : std_logic;
signal wb_ddr_we : std_logic;
signal wb_ddr_ack : std_logic;
signal wb_ddr_stall : std_logic;
-- Interrupts stuff
signal dma_irq : std_logic_vector(1 downto 0);
signal dma_irq_p : std_logic_vector(1 downto 0);
signal trig_irq_p : std_logic;
signal acq_end_irq_p : std_logic;
signal irq_sources : std_logic_vector(3 downto 0);
signal irq_to_gn4124 : std_logic;
signal irq_sources_2_led : std_logic_vector(3 downto 0);
signal ddr_wr_fifo_empty : std_logic;
signal dma_eic_irq : std_logic;
signal fmc0_eic_irq : std_logic;
-- LED control from carrier CSR register
signal led_red : std_logic;
signal led_green : std_logic;
-- CSR whisbone slaves for test
signal gpio_stat : std_logic_vector(31 downto 0);
signal gpio_ctrl_1 : std_logic_vector(31 downto 0);
signal gpio_ctrl_2 : std_logic_vector(31 downto 0);
signal gpio_ctrl_3 : std_logic_vector(31 downto 0);
signal gpio_led_ctrl : std_logic_vector(31 downto 0);
-- GN4124
signal gn4124_status : std_logic_vector(31 downto 0);
signal p2l_pll_locked : std_logic;
-- DDR3
signal ddr3_status : std_logic_vector(31 downto 0);
signal ddr3_calib_done : std_logic;
-- SPI
signal spi_din_t : std_logic_vector(3 downto 0);
signal spi_ss_t : std_logic_vector(7 downto 0);
-- Carrier 1-wire
signal carrier_owr_en : std_logic_vector(0 downto 0);
signal carrier_owr_i : std_logic_vector(0 downto 0);
-- led pwm
signal led_pwm_update_cnt : unsigned(9 downto 0);
signal led_pwm_update : std_logic;
signal led_pwm_val : unsigned(16 downto 0);
signal led_pwm_val_down : std_logic;
signal led_pwm_cnt : unsigned(16 downto 0);
signal led_pwm : std_logic;
begin
------------------------------------------------------------------------------
-- Clocks distribution from 20MHz TCXO
-- 125.000 MHz system clock
-- 250.000 MHz fast system clock
-- 333.333 MHz DDR3 clock
------------------------------------------------------------------------------
-- AD5662BRMZ-1 DAC output powers up to 0V. The output remains valid until a
-- write sequence arrives to the DAC.
-- To avoid spurious writes, the DAC interface outputs are fixed to safe values.
pll25dac_sync_n_o <= '1';
pll20dac_sync_n_o <= '1';
plldac_din_o <= '0';
plldac_sclk_o <= '0';
cmp_sys_clk_buf : IBUFG
port map (
I => clk20_vcxo_i,
O => sys_clk_in);
cmp_sys_clk_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 8,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 4,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 3,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 50.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => sys_clk_fb,
CLKOUT0 => sys_clk_125_buf,
CLKOUT1 => sys_clk_250_buf,
CLKOUT2 => ddr_clk_buf,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => sys_clk_pll_locked,
RST => '0',
CLKFBIN => sys_clk_fb,
CLKIN => sys_clk_in);
cmp_clk_125_buf : BUFG
port map (
O => sys_clk_125,
I => sys_clk_125_buf);
cmp_clk_250_buf : BUFG
port map (
O => sys_clk_250,
I => sys_clk_250_buf);
cmp_ddr_clk_buf : BUFG
port map (
O => ddr_clk,
I => ddr_clk_buf);
------------------------------------------------------------------------------
-- Local clock from gennum LCLK
------------------------------------------------------------------------------
cmp_l_clk_buf : IBUFDS
generic map (
DIFF_TERM => false, -- Differential Termination
IBUF_LOW_PWR => true, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => l_clk, -- Buffer output
I => L_CLKp, -- Diff_p buffer input (connect directly to top-level port)
IB => L_CLKn -- Diff_n buffer input (connect directly to top-level port)
);
------------------------------------------------------------------------------
-- System reset
------------------------------------------------------------------------------
p_powerup_reset : process(sys_clk_125)
begin
if rising_edge(sys_clk_125) then
if(L_RST_N = '0') then
powerup_rst_n <= '0';
elsif sys_clk_pll_locked = '1' then
if(powerup_reset_cnt = "11111111") then
powerup_rst_n <= '1';
else
powerup_rst_n <= '0';
powerup_reset_cnt <= powerup_reset_cnt + 1;
end if;
else
powerup_rst_n <= '0';
powerup_reset_cnt <= "00000000";
end if;
end if;
end process;
sys_rst_n <= powerup_rst_n;
fmc0_rst_n <= powerup_rst_n and sw_rst_fmc0_n;
------------------------------------------------------------------------------
-- GN4124 interface
------------------------------------------------------------------------------
cmp_gn4124_core : gn4124_core
port map(
rst_n_a_i => sys_rst_n,
status_o => gn4124_status,
-- P2L Direction Source Sync DDR related signals
p2l_clk_p_i => P2L_CLKp,
p2l_clk_n_i => P2L_CLKn,
p2l_data_i => P2L_DATA,
p2l_dframe_i => P2L_DFRAME,
p2l_valid_i => P2L_VALID,
-- P2L Control
p2l_rdy_o => P2L_RDY,
p_wr_req_i => P_WR_REQ,
p_wr_rdy_o => P_WR_RDY,
rx_error_o => RX_ERROR,
-- L2P Direction Source Sync DDR related signals
l2p_clk_p_o => L2P_CLKp,
l2p_clk_n_o => L2P_CLKn,
l2p_data_o => L2P_DATA,
l2p_dframe_o => L2P_DFRAME,
l2p_valid_o => L2P_VALID,
l2p_edb_o => L2P_EDB,
-- L2P Control
l2p_rdy_i => L2P_RDY,
l_wr_rdy_i => L_WR_RDY,
p_rd_d_rdy_i => P_RD_D_RDY,
tx_error_i => TX_ERROR,
vc_rdy_i => VC_RDY,
-- Interrupt interface
dma_irq_o => dma_irq,
irq_p_i => irq_to_gn4124,
irq_p_o => GPIO(0),
-- DMA registers wishbone interface (slave classic)
dma_reg_clk_i => sys_clk_125,
dma_reg_adr_i => dma_ctrl_wb_adr,
dma_reg_dat_i => cnx_master_out(c_WB_SLAVE_DMA).dat,
dma_reg_sel_i => cnx_master_out(c_WB_SLAVE_DMA).sel,
dma_reg_stb_i => cnx_master_out(c_WB_SLAVE_DMA).stb,
dma_reg_we_i => cnx_master_out(c_WB_SLAVE_DMA).we,
dma_reg_cyc_i => cnx_master_out(c_WB_SLAVE_DMA).cyc,
dma_reg_dat_o => cnx_master_in(c_WB_SLAVE_DMA).dat,
dma_reg_ack_o => cnx_master_in(c_WB_SLAVE_DMA).ack,
dma_reg_stall_o => cnx_master_in(c_WB_SLAVE_DMA).stall,
-- CSR wishbone interface (master pipelined)
csr_clk_i => sys_clk_125,
csr_adr_o => gn_wb_adr,
csr_dat_o => cnx_slave_in(c_MASTER_GENNUM).dat,
csr_sel_o => cnx_slave_in(c_MASTER_GENNUM).sel,
csr_stb_o => cnx_slave_in(c_MASTER_GENNUM).stb,
csr_we_o => cnx_slave_in(c_MASTER_GENNUM).we,
csr_cyc_o => cnx_slave_in(c_MASTER_GENNUM).cyc,
csr_dat_i => cnx_slave_out(c_MASTER_GENNUM).dat,
csr_ack_i => cnx_slave_out(c_MASTER_GENNUM).ack,
csr_stall_i => cnx_slave_out(c_MASTER_GENNUM).stall,
csr_err_i => cnx_slave_out(c_MASTER_GENNUM).err,
csr_rty_i => cnx_slave_out(c_MASTER_GENNUM).rty,
csr_int_i => cnx_slave_out(c_MASTER_GENNUM).int,
-- DMA wishbone interface (pipelined)
dma_clk_i => sys_clk_125,
dma_adr_o => wb_dma_adr,
dma_dat_o => wb_dma_dat_o,
dma_sel_o => wb_dma_sel,
dma_stb_o => wb_dma_stb,
dma_we_o => wb_dma_we,
dma_cyc_o => wb_dma_cyc,
dma_dat_i => wb_dma_dat_i,
dma_ack_i => wb_dma_ack,
dma_stall_i => wb_dma_stall,
dma_err_i => wb_dma_err,
dma_rty_i => wb_dma_rty,
dma_int_i => wb_dma_int
);
p2l_pll_locked <= gn4124_status(0);
-- Convert 32-bit word address into byte address for crossbar
cnx_slave_in(c_MASTER_GENNUM).adr <= gn_wb_adr(29 downto 0) & "00";
-- Convert 32-bit byte address into word address for DMA controller
dma_ctrl_wb_adr <= "00" & cnx_master_out(c_WB_SLAVE_DMA).adr(31 downto 2);
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_DMA).err <= '0';
cnx_master_in(c_WB_SLAVE_DMA).rty <= '0';
cnx_master_in(c_WB_SLAVE_DMA).int <= '0';
------------------------------------------------------------------------------
-- CSR wishbone crossbar
------------------------------------------------------------------------------
cmp_sdb_crossbar : xwb_sdb_crossbar
generic map (
g_num_masters => c_NUM_WB_SLAVES,
g_num_slaves => c_NUM_WB_MASTERS,
g_registered => true,
g_wraparound => true,
g_layout => c_INTERCONNECT_LAYOUT,
g_sdb_addr => c_SDB_ADDRESS)
port map (
clk_sys_i => sys_clk_125,
rst_n_i => sys_rst_n,
slave_i => cnx_slave_in,
slave_o => cnx_slave_out,
master_i => cnx_master_in,
master_o => cnx_master_out);
------------------------------------------------------------------------------
-- Carrier SPI master
-- VCXO DAC control
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Carrier 1-wire master
-- DS18B20 (thermometer + unique ID)
------------------------------------------------------------------------------
cmp_carrier_onewire : xwb_onewire_master
generic map(
g_interface_mode => CLASSIC,
g_address_granularity => BYTE,
g_num_ports => 1,
g_ow_btp_normal => "5.0",
g_ow_btp_overdrive => "1.0"
)
port map(
clk_sys_i => sys_clk_125,
rst_n_i => sys_rst_n,
slave_i => cnx_master_out(c_WB_SLAVE_ONEWIRE),
slave_o => cnx_master_in(c_WB_SLAVE_ONEWIRE),
desc_o => open,
owr_pwren_o => open,
owr_en_o => carrier_owr_en,
owr_i => carrier_owr_i
);
carrier_one_wire_b <= '0' when carrier_owr_en(0) = '1' else 'Z';
carrier_owr_i(0) <= carrier_one_wire_b;
------------------------------------------------------------------------------
-- Carrier CSR
-- Carrier type and PCB version
-- Bitstream (firmware) type and date
-- Release tag
-- VCXO DAC control (CLR_N)
------------------------------------------------------------------------------
cmp_carrier_csr : carrier_csr
port map(
rst_n_i => sys_rst_n,
clk_sys_i => sys_clk_125,
wb_adr_i => cnx_master_out(c_WB_SLAVE_SPEC_CSR).adr(3 downto 2), -- cnx_master_out.adr is byte address
wb_dat_i => cnx_master_out(c_WB_SLAVE_SPEC_CSR).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_SPEC_CSR).dat,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_SPEC_CSR).cyc,
wb_sel_i => cnx_master_out(c_WB_SLAVE_SPEC_CSR).sel,
wb_stb_i => cnx_master_out(c_WB_SLAVE_SPEC_CSR).stb,
wb_we_i => cnx_master_out(c_WB_SLAVE_SPEC_CSR).we,
wb_ack_o => cnx_master_in(c_WB_SLAVE_SPEC_CSR).ack,
wb_stall_o => open,
carrier_csr_carrier_pcb_rev_i => pcb_ver_i,
carrier_csr_carrier_reserved_i => X"000",
carrier_csr_carrier_type_i => c_CARRIER_TYPE,
carrier_csr_stat_fmc_pres_i => fmc0_prsnt_m2c_n_i,
carrier_csr_stat_p2l_pll_lck_i => p2l_pll_locked,
carrier_csr_stat_sys_pll_lck_i => sys_clk_pll_locked,
carrier_csr_stat_ddr3_cal_done_i => ddr3_calib_done,
carrier_csr_ctrl_led_green_o => led_green,
carrier_csr_ctrl_led_red_o => led_red,
carrier_csr_ctrl_dac_clr_n_o => open,
carrier_csr_rst_fmc0_n_o => sw_rst_fmc0_n_o,
carrier_csr_rst_fmc0_n_i => sw_rst_fmc0_n_i,
carrier_csr_rst_fmc0_n_load_o => sw_rst_fmc0_n_load
);
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_SPEC_CSR).err <= '0';
cnx_master_in(c_WB_SLAVE_SPEC_CSR).rty <= '0';
cnx_master_in(c_WB_SLAVE_SPEC_CSR).stall <= '0';
cnx_master_in(c_WB_SLAVE_SPEC_CSR).int <= '0';
-- SPEC front panel leds
led_red_o <= led_red;
led_green_o <= led_green;
-- external software reset register (to assign a non-zero default value)
p_sw_rst_fmc0 : process (sys_clk_125)
begin
if rising_edge(sys_clk_125) then
if sys_rst_n = '0' then
sw_rst_fmc0_n <= '1';
elsif sw_rst_fmc0_n_load = '1' then
sw_rst_fmc0_n <= sw_rst_fmc0_n_o;
end if;
end if;
end process p_sw_rst_fmc0;
sw_rst_fmc0_n_i <= sw_rst_fmc0_n;
------------------------------------------------------------------------------
-- Vectored interrupt controller (VIC)
------------------------------------------------------------------------------
cmp_vic : xwb_vic
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_num_interrupts => 2,
g_init_vectors => c_VIC_VECTOR_TABLE)
port map (
clk_sys_i => sys_clk_125,
rst_n_i => sys_rst_n,
slave_i => cnx_master_out(c_WB_SLAVE_VIC),
slave_o => cnx_master_in(c_WB_SLAVE_VIC),
irqs_i(0) => fmc0_eic_irq,
irqs_i(1) => dma_eic_irq,
irq_master_o => irq_to_gn4124);
------------------------------------------------------------------------------
-- GN4124 DMA interrupt controller
------------------------------------------------------------------------------
cmp_dma_eic : dma_eic
port map(
rst_n_i => sys_rst_n,
clk_sys_i => sys_clk_125,
wb_adr_i => cnx_master_out(c_WB_SLAVE_DMA_EIC).adr(3 downto 2), -- cnx_master_out.adr is byte address
wb_dat_i => cnx_master_out(c_WB_SLAVE_DMA_EIC).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_DMA_EIC).dat,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_DMA_EIC).cyc,
wb_sel_i => cnx_master_out(c_WB_SLAVE_DMA_EIC).sel,
wb_stb_i => cnx_master_out(c_WB_SLAVE_DMA_EIC).stb,
wb_we_i => cnx_master_out(c_WB_SLAVE_DMA_EIC).we,
wb_ack_o => cnx_master_in(c_WB_SLAVE_DMA_EIC).ack,
wb_stall_o => cnx_master_in(c_WB_SLAVE_DMA_EIC).stall,
wb_int_o => dma_eic_irq,
irq_dma_done_i => dma_irq(0),
irq_dma_error_i => dma_irq(1)
);
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_DMA_EIC).err <= '0';
cnx_master_in(c_WB_SLAVE_DMA_EIC).rty <= '0';
cnx_master_in(c_WB_SLAVE_DMA_EIC).int <= '0';
------------------------------------------------------------------------------
-- FMC ADC mezzanine (wb bridge)
-- System managment I2C master
-- SPI master
-- I2C
-- ADC core csr
-- 1-wire master
-- eic
-- timetag core
------------------------------------------------------------------------------
cmp_fmc_adc_mezzanine_0 : fmc_adc_mezzanine
generic map(
g_multishot_ram_size => 2048,
g_carrier_type => "SPEC"
)
port map(
sys_clk_i => sys_clk_125,
sys_rst_n_i => fmc0_rst_n,
wb_csr_adr_i => cnx_master_out(c_WB_SLAVE_FMC_ADC).adr,
wb_csr_dat_i => cnx_master_out(c_WB_SLAVE_FMC_ADC).dat,
wb_csr_dat_o => cnx_master_in(c_WB_SLAVE_FMC_ADC).dat,
wb_csr_cyc_i => cnx_master_out(c_WB_SLAVE_FMC_ADC).cyc,
wb_csr_sel_i => cnx_master_out(c_WB_SLAVE_FMC_ADC).sel,
wb_csr_stb_i => cnx_master_out(c_WB_SLAVE_FMC_ADC).stb,
wb_csr_we_i => cnx_master_out(c_WB_SLAVE_FMC_ADC).we,
wb_csr_ack_o => cnx_master_in(c_WB_SLAVE_FMC_ADC).ack,
wb_csr_stall_o => cnx_master_in(c_WB_SLAVE_FMC_ADC).stall,
wb_ddr_clk_i => sys_clk_125,
wb_ddr_adr_o => wb_ddr_adr,
wb_ddr_dat_o => wb_ddr_dat_o,
wb_ddr_sel_o => wb_ddr_sel,
wb_ddr_stb_o => wb_ddr_stb,
wb_ddr_we_o => wb_ddr_we,
wb_ddr_cyc_o => wb_ddr_cyc,
wb_ddr_ack_i => wb_ddr_ack,
wb_ddr_stall_i => wb_ddr_stall,
ddr_wr_fifo_empty_i => ddr_wr_fifo_empty,
trig_irq_o => trig_irq_p,
acq_end_irq_o => acq_end_irq_p,
eic_irq_o => fmc0_eic_irq,
ext_trigger_p_i => adc0_ext_trigger_p_i,
ext_trigger_n_i => adc0_ext_trigger_n_i,
adc_dco_p_i => adc0_dco_p_i,
adc_dco_n_i => adc0_dco_n_i,
adc_fr_p_i => adc0_fr_p_i,
adc_fr_n_i => adc0_fr_n_i,
adc_outa_p_i => adc0_outa_p_i,
adc_outa_n_i => adc0_outa_n_i,
adc_outb_p_i => adc0_outb_p_i,
adc_outb_n_i => adc0_outb_n_i,
gpio_dac_clr_n_o => adc0_gpio_dac_clr_n_o,
gpio_led_acq_o => adc0_gpio_led_acq_o,
gpio_led_trig_o => adc0_gpio_led_trig_o,
gpio_ssr_ch1_o => adc0_gpio_ssr_ch1_o,
gpio_ssr_ch2_o => adc0_gpio_ssr_ch2_o,
gpio_ssr_ch3_o => adc0_gpio_ssr_ch3_o,
gpio_ssr_ch4_o => adc0_gpio_ssr_ch4_o,
gpio_si570_oe_o => adc0_gpio_si570_oe_o,
spi_din_i => adc0_spi_din_i,
spi_dout_o => adc0_spi_dout_o,
spi_sck_o => adc0_spi_sck_o,
spi_cs_adc_n_o => adc0_spi_cs_adc_n_o,
spi_cs_dac1_n_o => adc0_spi_cs_dac1_n_o,
spi_cs_dac2_n_o => adc0_spi_cs_dac2_n_o,
spi_cs_dac3_n_o => adc0_spi_cs_dac3_n_o,
spi_cs_dac4_n_o => adc0_spi_cs_dac4_n_o,
si570_scl_b => adc0_si570_scl_b,
si570_sda_b => adc0_si570_sda_b,
mezz_one_wire_b => adc0_one_wire_b,
sys_scl_b => fmc0_sys_scl_b,
sys_sda_b => fmc0_sys_sda_b
);
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_FMC_ADC).err <= '0';
cnx_master_in(c_WB_SLAVE_FMC_ADC).rty <= '0';
cnx_master_in(c_WB_SLAVE_FMC_ADC).int <= '0';
------------------------------------------------------------------------------
-- DMA wishbone bus slaves
-- -> DDR3 controller
------------------------------------------------------------------------------
cmp_ddr_ctrl : ddr3_ctrl
generic map(
g_BANK_PORT_SELECT => "SPEC_BANK3_64B_32B",
g_MEMCLK_PERIOD => 3000,
g_SIMULATION => g_SIMULATION,
g_CALIB_SOFT_IP => g_CALIB_SOFT_IP,
g_P0_MASK_SIZE => 8,
g_P0_DATA_PORT_SIZE => 64,
g_P0_BYTE_ADDR_WIDTH => 30,
g_P1_MASK_SIZE => 4,
g_P1_DATA_PORT_SIZE => 32,
g_P1_BYTE_ADDR_WIDTH => 30)
port map (
clk_i => ddr_clk,
rst_n_i => fmc0_rst_n,
status_o => ddr3_status,
ddr3_dq_b => DDR3_DQ,
ddr3_a_o => DDR3_A,
ddr3_ba_o => DDR3_BA,
ddr3_ras_n_o => DDR3_RAS_N,
ddr3_cas_n_o => DDR3_CAS_N,
ddr3_we_n_o => DDR3_WE_N,
ddr3_odt_o => DDR3_ODT,
ddr3_rst_n_o => DDR3_RESET_N,
ddr3_cke_o => DDR3_CKE,
ddr3_dm_o => DDR3_LDM,
ddr3_udm_o => DDR3_UDM,
ddr3_dqs_p_b => DDR3_LDQS_P,
ddr3_dqs_n_b => DDR3_LDQS_N,
ddr3_udqs_p_b => DDR3_UDQS_P,
ddr3_udqs_n_b => DDR3_UDQS_N,
ddr3_clk_p_o => DDR3_CK_P,
ddr3_clk_n_o => DDR3_CK_N,
ddr3_rzq_b => DDR3_RZQ,
ddr3_zio_b => DDR3_ZIO,
wb0_clk_i => sys_clk_125,
wb0_sel_i => wb_ddr_sel,
wb0_cyc_i => wb_ddr_cyc,
wb0_stb_i => wb_ddr_stb,
wb0_we_i => wb_ddr_we,
wb0_addr_i => wb_ddr_adr,
wb0_data_i => wb_ddr_dat_o,
wb0_data_o => open,
wb0_ack_o => wb_ddr_ack,
wb0_stall_o => wb_ddr_stall,
p0_cmd_empty_o => open,
p0_cmd_full_o => open,
p0_rd_full_o => open,
p0_rd_empty_o => open,
p0_rd_count_o => open,
p0_rd_overflow_o => open,
p0_rd_error_o => open,
p0_wr_full_o => open,
p0_wr_empty_o => ddr_wr_fifo_empty,
p0_wr_count_o => open,
p0_wr_underrun_o => open,
p0_wr_error_o => open,
wb1_clk_i => sys_clk_125,
wb1_sel_i => wb_dma_sel,
wb1_cyc_i => wb_dma_cyc,
wb1_stb_i => wb_dma_stb,
wb1_we_i => wb_dma_we,
wb1_addr_i => wb_dma_adr,
wb1_data_i => wb_dma_dat_o,
wb1_data_o => wb_dma_dat_i,
wb1_ack_o => wb_dma_ack,
wb1_stall_o => wb_dma_stall,
p1_cmd_empty_o => open,
p1_cmd_full_o => open,
p1_rd_full_o => open,
p1_rd_empty_o => open,
p1_rd_count_o => open,
p1_rd_overflow_o => open,
p1_rd_error_o => open,
p1_wr_full_o => open,
p1_wr_empty_o => open,
p1_wr_count_o => open,
p1_wr_underrun_o => open,
p1_wr_error_o => open
);
ddr3_calib_done <= ddr3_status(0);
-- unused Wishbone signals
wb_dma_err <= '0';
wb_dma_rty <= '0';
wb_dma_int <= '0';
------------------------------------------------------------------------------
-- Assign unused outputs
------------------------------------------------------------------------------
GPIO(1) <= '0'; -- connection to GN4124
------------------------------------------------------------------------------
-- FPGA loaded led (heart beat)
------------------------------------------------------------------------------
p_led_pwn_update_cnt : process (sys_clk_125)
begin
if rising_edge(sys_clk_125) then
if (sys_rst_n = '0') then
led_pwm_update_cnt <= (others => '0');
led_pwm_update <= '0';
elsif (led_pwm_update_cnt = to_unsigned(954, 10)) then
led_pwm_update_cnt <= (others => '0');
led_pwm_update <= '1';
else
led_pwm_update_cnt <= led_pwm_update_cnt + 1;
led_pwm_update <= '0';
end if;
end if;
end process p_led_pwn_update_cnt;
p_led_pwn_val : process (sys_clk_125)
begin
if rising_edge(sys_clk_125) then
if (sys_rst_n = '0') then
led_pwm_val <= (others => '0');
led_pwm_val_down <= '0';
elsif (led_pwm_update = '1') then
if led_pwm_val_down = '1' then
if led_pwm_val = X"100" then
led_pwm_val_down <= '0';
end if;
led_pwm_val <= led_pwm_val - 1;
else
if led_pwm_val = X"1FFFE" then
led_pwm_val_down <= '1';
end if;
led_pwm_val <= led_pwm_val + 1;
end if;
end if;
end if;
end process p_led_pwn_val;
p_led_pwn_cnt : process (sys_clk_125)
begin
if rising_edge(sys_clk_125) then
if (sys_rst_n = '0') then
led_pwm_cnt <= (others => '0');
else
led_pwm_cnt <= led_pwm_cnt + 1;
end if;
end if;
end process p_led_pwn_cnt;
p_led_pwn : process (sys_clk_125)
begin
if rising_edge(sys_clk_125) then
if (sys_rst_n = '0') then
led_pwm <= '0';
elsif (led_pwm_cnt = 0) then
led_pwm <= '1';
elsif (led_pwm_cnt = led_pwm_val) then
led_pwm <= '0';
end if;
end if;
end process p_led_pwn;
aux_leds_o(0) <= led_pwm;
-- IRQ LEDs
-- 0 -> End of DMA transfer
-- 1 -> DMA transfer error
-- 2 -> Trigger
-- 3 -> End of acquisition (data written to DDR)
irq_sources(1 downto 0) <= dma_irq;
irq_sources(2) <= trig_irq_p;
irq_sources(3) <= acq_end_irq_p;
gen_irq_led : for I in 0 to irq_sources'length-1 generate
cmp_irq_led : gc_extend_pulse
generic map (
g_width => 5000000)
port map (
clk_i => sys_clk_125,
rst_n_i => sys_rst_n,
pulse_i => irq_sources(I),
extended_o => irq_sources_2_led(I));
end generate gen_irq_led;
aux_leds_o(1) <= not(irq_sources_2_led(2));
aux_leds_o(2) <= not(irq_sources_2_led(3));
aux_leds_o(3) <= not(irq_sources_2_led(0));
end rtl;
gateware/top/spec/spec_top_fmc_masterfip.vhd
View file @ 39f4f710
......@@ -47,7 +47,7 @@ use work.ddr3_ctrl_pkg.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.fmc_adc_mezzanine_pkg.all;
use work.sdb_meta_pkg.all;
-- use work.sdb_meta_pkg.all;
use work.timetag_core_pkg.all;
......@@ -329,18 +329,18 @@ architecture rtl of spec_top_fmc_masterfip is
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
-- Wishbone crossbar layout
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(8 downto 0) :=
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(5 downto 0) :=
(
0 => f_sdb_embed_device(c_wb_dma_ctrl_sdb, x"00001000"),
1 => f_sdb_embed_device(c_xwb_onewire_master_sdb, x"00001100"),
2 => f_sdb_embed_device(c_wb_spec_csr_sdb, x"00001200"),
3 => f_sdb_embed_device(c_xwb_vic_sdb, x"00001300"),
4 => f_sdb_embed_device(c_wb_dma_eic_sdb, x"00001400"),
5 => f_sdb_embed_bridge(c_fmc0_bridge_sdb, x"00020000"),
5 => f_sdb_embed_bridge(c_fmc0_bridge_sdb, x"00020000")
-- 5 => f_sdb_embed_bridge(c_fmc0_bridge_sdb, x"00002000"),
6 => f_sdb_embed_repo_url(c_repo_url_sdb),
7 => f_sdb_embed_synthesis(c_synthesis_sdb),
8 => f_sdb_embed_integration(c_integration_sdb)
-- 6 => f_sdb_embed_repo_url(c_repo_url_sdb),
-- 6 => f_sdb_embed_synthesis(c_synthesis_sdb),
-- 7 => f_sdb_embed_integration(c_integration_sdb)
);
-- VIC default vector setting
......
gateware/top/spec/synthesis_descriptor.vhd deleted 100644 → 0
View file @ caef7287
-------------------------------------------------------------------------------
-- Title : TDC FMC SPEC (Simple VME FMC Carrier) SDB descriptor
-- Project : TDC FMC (fmc-tdc-1ns-5cha)
-------------------------------------------------------------------------------
-- File : synthesis_descriptor.vhd
-- Author : Evangelia Gousiou
-- Company : CERN
-- Created : 2013-04-16
-- Last update: 2013-04-16
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: SDB descriptor for the top level of the FD on a SPEC carrier.
-- Contains synthesis & source repository information.
-- Warning: this file is modified whenever a synthesis is executed.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.STD_LOGIC_1164.all;
use work.wishbone_pkg.all;
package synthesis_descriptor is
constant c_sdb_synthesis_info : t_sdb_synthesis :=
(
syn_module_name => "spec_masterFIP ",
syn_commit_id => "00000000000000000000000000000000",
syn_tool_name => "ISE ",
syn_tool_version => x"00000147",
syn_date => x"20160128",
syn_username => "egousiou ");
constant c_sdb_repo_url : t_sdb_repo_url :=
(
repo_url => "http://svn.ohwr.org/projects/masterFIP "
);
end package synthesis_descriptor;
pts/fmcmasterfip.sh
View file @ 39f4f710
......@@ -157,7 +157,7 @@ do
cp $f "${LOGDIR}/adcdata/${newname}"
done
echo "ADC samples backed up in ${LOGDIR}/adcdata/${newname}"
echo "ADC samples backed up in ${LOGDIR}/adcdata"
else
echo "Did not find any ADC samples to backup"
fi
......
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