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MasterFIP - Testing
Commit 30c3283c authored by Marek Gumiński's avatar Marek Gumiński
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Small fixes in python scripts. 

Output binary not included!!!!
Removed one of CPU cores from mockturtle.
Fixed path bug in pts/fmcmasterfip.py
Update csr interfaces for updated gw-masterfip.
parent ca15afbd
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Showing with 470 additions and 53355 deletions
gateware/rtl/masterFIP_pkg.vhd 0 → 100644
View file @ 30c3283c
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gateware/rtl/wbgen/masterfip_csr.vhd
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gateware/rtl/wbgen/masterfip_pts_csr.vhd
View file @ 30c3283c
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.vhd
-- Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.wb
-- Created : Mon Apr 3 13:15:24 2017
-- Created : Mon Apr 24 10:20:17 2017
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.wb
......
gateware/top/spec/spec_masterfip_pts.ucf
View file @ 30c3283c
......@@ -286,7 +286,7 @@ TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk" TNM_NET = U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk;
TIMESPEC TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_P_clk = PERIOD "U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback" TNM_NET = U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback;
TIMESPEC TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_feedback = PERIOD "U_Node_Template/U_GN4124_Core/cmp_clk_in/feedback" 5 ns HIGH 50%;
TIMESPEC TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_feedback = PERIOD "U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback" 5 ns HIGH 50%;
NET "l_rst_n_i" TIG;
NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/rst_*" TIG;
\ No newline at end of file
gateware/top/spec/spec_masterfip_pts.vhd
View file @ 30c3283c
......@@ -319,8 +319,8 @@ architecture rtl of spec_masterfip_pts is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
constant C_NODE_CONFIG : t_wr_node_config :=
(app_id => x"0f1dc03e",
cpu_count => 2,
cpu_memsizes => (98304, 8192, 0, 0, 0, 0, 0, 0), -- in bytes; for CPU0 the size should be enough
cpu_count => 1,
cpu_memsizes => (98304, 0, 0, 0, 0, 0, 0, 0), -- in bytes; for CPU0 the size should be enough
-- for the storage of the RT sw running on CPU0
-- and for the macrocycle configuration
hmq_config => C_HMQ_CONFIG,
......@@ -362,8 +362,8 @@ architecture rtl of spec_masterfip_pts is
signal clk_100m_sys : std_logic;
signal rst_n_sys : std_logic;
-- Mock Turtle
signal wbmain_masters_ms : t_wishbone_master_out_array(2 downto 0);
signal wbmain_masters_sm : t_wishbone_master_in_array(2 downto 0);
signal wbmain_masters_ms : t_wishbone_master_out_array(1 downto 0);
signal wbmain_masters_sm : t_wishbone_master_in_array(1 downto 0);
signal wbmain_slaves_ms : t_wishbone_master_out_array(c_NUM_WB_SLAVES-1 downto 0);
signal wbmain_slaves_sm : t_wishbone_master_in_array(c_NUM_WB_SLAVES-1 downto 0);
-- SPEC LEDs
......@@ -453,12 +453,12 @@ begin
fmc_prsnt_m2c_l_i => fmc_prsnt_m2c_n_i,
-- WISHBONE connection of the fmc_masterFIP_core to the MT CPUs
dp_master_o(0) => wbmain_masters_ms(0), -- access from MT CPU0 at base address 0x100000
dp_master_o(1) => wbmain_masters_ms(1),
-- dp_master_o(1) => wbmain_masters_ms(1),
dp_master_i(0) => wbmain_masters_sm(0), -- access from MT CPU1 at base address 0x100000
dp_master_i(1) => wbmain_masters_sm(1),
-- dp_master_i(1) => wbmain_masters_sm(1),
-- WISHBONE connection of the fmc_masterFIP_core to the host
fmc0_host_wb_o => wbmain_masters_ms(2), -- access from PCIe host at base address 0x10000
fmc0_host_wb_i => wbmain_masters_sm(2),
fmc0_host_wb_o => wbmain_masters_ms(1), -- access from PCIe host at base address 0x10000
fmc0_host_wb_i => wbmain_masters_sm(1),
fmc0_host_irq_i => '0',
-- not used
clk_20m_vcxo_i => '0',
......@@ -477,7 +477,7 @@ begin
-- purposes. The PCIe host is accessing the core directly only for testing purposes.
cmp_wb_crossbar : xwb_crossbar
generic map
(g_num_masters => 3,
(g_num_masters => 2,
g_num_slaves => c_NUM_WB_SLAVES,
g_registered => true,
g_address => C_SLAVE_ADDR,
......
pts/fmcmasterfip.sh
View file @ 30c3283c
......@@ -141,7 +141,7 @@ do
echo " "
# run tests
sudo ${top}/pts/ptsFip.py -b FmcMasterFip -s $serial -e $extra_serial -t../python -l $LOGDIR 00 01 02 04 05 06
sudo ${top}/pts/ptsFip.py -b FmcMasterFip -s $serial -e $extra_serial "-t${top}/python -l $LOGDIR 00 01 02 04 05 06
# backup eeprom image
......
python/regs/carrier_addrtable.py
View file @ 30c3283c
......@@ -2,7 +2,7 @@
#
# * File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/python/regs/carrier_addrtable.py
# * Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/carrier_csr.wb
# * Created : Mon Apr 3 13:15:22 2017
# * Created : Mon Apr 24 10:20:14 2017
#
# THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/carrier_csr.wb
# DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
......
python/regs/masterfip_addrtable.htm deleted 100644 → 0
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python/regs/masterfip_addrtable.py deleted 100644 → 0
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python/regs/masterfip_csr.htm
View file @ 30c3283c
......@@ -3169,23 +3169,6 @@ masterfip_led_tx_err_o
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
masterfip_led_ext_sync_used_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
masterfip_led_ext_sync_act_o
......@@ -3489,6 +3472,40 @@ masterfip_ext_sync_ctrl_p_cnt_rst_o
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
masterfip_ext_sync_ctrl_opt_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
masterfip_ext_sync_ctrl_safe_wind_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
......@@ -4072,7 +4089,7 @@ masterfip_tx_ctrl_start_o
</td>
<td class="td_pblock_right">
masterfip_tx_ctrl_bytes_num_o[8:0]
masterfip_tx_ctrl_bytes_num_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -4157,7 +4174,7 @@ masterfip_tx_stat_ena_i
</td>
<td class="td_pblock_right">
masterfip_tx_stat_curr_byte_indx_i[8:0]
masterfip_tx_stat_curr_byte_indx_i[15:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -4531,7 +4548,7 @@ masterfip_rx_stat_frame_crc_err_i
</td>
<td class="td_pblock_right">
masterfip_rx_stat_bytes_num_i[8:0]
masterfip_rx_stat_bytes_num_i[15:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -4582,7 +4599,7 @@ masterfip_rx_stat_bytes_num_i[8:0]
</td>
<td class="td_pblock_right">
masterfip_rx_stat_curr_word_indx_i[6:0]
masterfip_rx_stat_curr_word_indx_i[7:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -12336,6 +12353,9 @@ DBG[7:0]
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
EXT_SYNC_ERR
</td>
......@@ -12343,9 +12363,6 @@ EXT_SYNC_ERR
EXT_SYNC_ACT
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
EXT_SYNC_USED
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
TX_ERR
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
......@@ -12373,9 +12390,6 @@ TX_ACT
TX_ERR
</b>[<i>read/write</i>]: tx err red led
<li><b>
EXT_SYNC_USED
</b>[<i>read/write</i>]: write 1 to indicate that the ext sync is used
<li><b>
EXT_SYNC_ACT
</b>[<i>read/write</i>]: ext sync act green led
<li><b>
......@@ -12384,6 +12398,7 @@ EXT_SYNC_ERR
<li><b>
DBG
</b>[<i>read/write</i>]: dbg
<br>bit 8 is connected to TP3; bit 9 is connected to TP4
</ul>
<a name="DS1820_TEMPER"></a>
<h3><a name="sect_3_4">3.4. fmc temperature</a></h3>
......@@ -13250,8 +13265,8 @@ EXT_SYNC_CTRL
<td class="td_unused">
-
</td>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=1 class="td_field">
SAFE_WIND
</td>
</tr>
</table>
......@@ -13304,8 +13319,8 @@ EXT_SYNC_CTRL
<td class="td_unused">
-
</td>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=1 class="td_field">
OPT
</td>
</tr>
</table>
......@@ -13429,11 +13444,19 @@ DIR
<li><b>
OE_N
</b>[<i>read/write</i>]: transceiver output enable negative logic
<br>write 0: normal operation, the external sync pulse arrives to the FPGA<br> write 1: the external sync pulse does not arrive to the FPGA<br> WARNING: this bit is hard-wired in the HDL top to 0
<br>write 0: normal operation, the external sync pulse arrives to the FPGA and controls the macrocycle counter<br> write 1: the external sync pulse is disabled; the macrocycle counting is based on internal counters
<li><b>
P_CNT_RST
</b>[<i>read/write</i>]: pulses counter reset
<br>resets the pulses counter
<li><b>
OPT
</b>[<i>read/write</i>]: counting options
<br>0: external pulse resets the macrocycle counter whenever it arrives<br> 1: external pulse resets the macrocycle counter, only when it arrives in a window as expected by the<br> processor and the macrocycle configuration. In this option for example if a macrocycle is set at 20 ms<br> but a pulse arrives every 10 ms by mistake, then one every 2 pulses will be ignored.<br> Note that the ext_sync_p_cnt will be counting in any case all the incoming pulses, so the error will<br> be reported, but the macrocycle will run smoothly at 20 ms
<li><b>
SAFE_WIND
</b>[<i>read/write</i>]: safe window
<br>0: processor busy with periodic traffic; reception of a new external pulse is NOT safe<br> 1: processor ready for a new external pulse; macrocycle periodic part has been played
</ul>
<a name="EXT_SYNC_P_CNT"></a>
<h3><a name="sect_3_8">3.8. ext sync pulses cnt</a></h3>
......@@ -13691,7 +13714,7 @@ EXT_SYNC_P_CNT[7:0]
<li><b>
EXT_SYNC_P_CNT
</b>[<i>read-only</i>]: ext_sync_p_cnt
<br>number of ext sync pulses since the application startup OR a rst_core OR a ext_sync_p_cnt_rst;<br> for the fastest macrocycle of 20ms, the counter can keep counting for up to >2.5 years.
<br>number of ext sync pulses since the application startup OR a rst_core OR a ext_sync_p_cnt_rst;<br> for the fastest macrocycle of 20ms, the counter can keep counting for up to 2.7 years.
</ul>
<a name="SPEED"></a>
<h3><a name="sect_3_9">3.9. bus speed</a></h3>
......@@ -14727,7 +14750,7 @@ MACROCYC_NUM_CNT[7:0]
<li><b>
MACROCYC_NUM_CNT
</b>[<i>read-only</i>]: number of macrocycles
<br>amount of macrocycles that have been counted since the application startup OR a rst_core;<br> for the fastest macrocycle of 20ms, the counter can keep counting for up to >2.5 years.
<br>amount of macrocycles that have been counted since the application startup OR a rst_core;<br> for the fastest macrocycle of 20ms, the counter can keep counting for up to 2.7 years.
</ul>
<a name="TURNAR"></a>
<h3><a name="sect_3_13">3.13. turnaround lgth</a></h3>
......@@ -15887,29 +15910,29 @@ TX_CTRL
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
BYTES_NUM[15:8]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
BYTES_NUM[8:8]
<td >
</td>
</tr>
</table>
......@@ -16099,29 +16122,29 @@ TX_STAT
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
CURR_BYTE_INDX[15:8]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -16153,26 +16176,26 @@ TX_STAT
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
CURR_BYTE_INDX[7:0]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td style="border: solid 1px black;" colspan=2 class="td_field">
CURR_BYTE_INDX[8:7]
<td >
</td>
<td >
......@@ -16207,29 +16230,29 @@ CURR_BYTE_INDX[8:7]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=7 class="td_field">
CURR_BYTE_INDX[6:0]
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
ENA
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td style="border: solid 1px black;" colspan=1 class="td_field">
ENA
</td>
</tr>
</table>
......@@ -17716,29 +17739,29 @@ RX_STAT
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
BYTES_NUM[15:8]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
BYTES_NUM[8:8]
<td >
</td>
</tr>
</table>
......@@ -18094,11 +18117,11 @@ RX_STAT_CURR_WORD_INDX
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
RX_STAT_CURR_WORD_INDX[7:0]
</td>
<td style="border: solid 1px black;" colspan=7 class="td_field">
RX_STAT_CURR_WORD_INDX[6:0]
<td >
</td>
<td >
......
python/regs/masterfip_csr.py
View file @ 30c3283c
......@@ -2,7 +2,7 @@
#
# * File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/python/regs/masterfip_csr.py
# * Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/ip_cores/gw-masterfip/rtl/wbgen/masterfip_csr.wb
# * Created : Mon Apr 3 13:15:22 2017
# * Created : Mon Apr 24 10:20:15 2017
#
# THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/ip_cores/gw-masterfip/rtl/wbgen/masterfip_csr.wb
# DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
......@@ -21,9 +21,8 @@ addr = {
'led.rx_err' : [ 0x2, 0x2, "rw"],
'led.tx_act' : [ 0x2, 0x4, "rw"],
'led.tx_err' : [ 0x2, 0x8, "rw"],
'led.ext_sync_used' : [ 0x2, 0x10, "rw"],
'led.ext_sync_act' : [ 0x2, 0x20, "rw"],
'led.ext_sync_err' : [ 0x2, 0x40, "rw"],
'led.ext_sync_act' : [ 0x2, 0x10, "rw"],
'led.ext_sync_err' : [ 0x2, 0x20, "rw"],
'led.dbg' : [ 0x2, 0xFFFFFF00, "rw"],
'ds1820_temper' : [ 0x3, 0xffffffff, "r"],
......@@ -37,6 +36,8 @@ addr = {
'ext_sync_ctrl.dir' : [ 0x6, 0x2, "rw"],
'ext_sync_ctrl.oe_n' : [ 0x6, 0x4, "rw"],
'ext_sync_ctrl.p_cnt_rst' : [ 0x6, 0x100, "rw"],
'ext_sync_ctrl.opt' : [ 0x6, 0x10000, "rw"],
'ext_sync_ctrl.safe_wind' : [ 0x6, 0x1000000, "rw"],
'ext_sync_p_cnt' : [ 0x7, 0xffffffff, "r"],
......@@ -65,12 +66,12 @@ addr = {
'tx_ctrl' : [ 0x10, 0xffffffff, "rw"],
'tx_ctrl.rst' : [ 0x10, 0x1, "rw"],
'tx_ctrl.start' : [ 0x10, 0x2, "rw"],
'tx_ctrl.bytes_num' : [ 0x10, 0x1FF00, "rw"],
'tx_ctrl.bytes_num' : [ 0x10, 0xFFFF00, "rw"],
'tx_stat' : [ 0x11, 0xffffffff, "r"],
'tx_stat.stop' : [ 0x11, 0x1, "r"],
'tx_stat.ena' : [ 0x11, 0x100, "r"],
'tx_stat.curr_byte_indx' : [ 0x11, 0x3FE00, "r"],
'tx_stat.curr_byte_indx' : [ 0x11, 0xFFFF0000, "r"],
'fd' : [ 0x12, 0xffffffff, "r"],
'fd.wdg' : [ 0x12, 0x1, "r"],
......@@ -88,7 +89,7 @@ addr = {
'rx_stat.pream_ok' : [ 0x17, 0x1, "r"],
'rx_stat.frame_ok' : [ 0x17, 0x2, "r"],
'rx_stat.frame_crc_err' : [ 0x17, 0x4, "r"],
'rx_stat.bytes_num' : [ 0x17, 0x1FF00, "r"],
'rx_stat.bytes_num' : [ 0x17, 0xFFFF00, "r"],
'rx_stat_curr_word_indx' : [ 0x18, 0xffffffff, "r"],
......
python/regs/masterfip_pts_csr.py
View file @ 30c3283c
......@@ -2,7 +2,7 @@
#
# * File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/python/regs/masterfip_pts_csr.py
# * Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.wb
# * Created : Mon Apr 3 13:15:24 2017
# * Created : Mon Apr 24 10:20:17 2017
#
# THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.wb
# DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
......
python/test01.py
View file @ 30c3283c
......@@ -118,7 +118,7 @@ def main (card=None, default_directory='.',suite=None, serial=""):
# test_results['All leds'] = test_led_all( dut )
test_results['Running led'] = test_running_led( dut )
dut.fipcore.write_regname( 'led.ext_sync_used', 1 )
dut.fipcore.write_regname( 'ext_sync_ctrl.oe_n', 0 )
for led in ledlist:
# if there was an error in test of all LEDs
......
python/test02.py
View file @ 30c3283c
......@@ -77,7 +77,7 @@ def verify_rx_status( stat ):
def verify_presence( carrier ):
util.info_msg("Bus transmission: checking presence")
util.info_msg("Bus transmission: sending presence variable 0x147F to nanoFIPdiag.")
# Send ID_DAT for presence variable (0x14)
# nanoFIPdiag address (common to all such modules in CERN): 7F
......@@ -101,7 +101,7 @@ def verify_presence( carrier ):
# presence variable data is always the same
if util.bitvector(data, 0, 8*6) == 0x00f00003800550 :
util.info_msg ("Presence variable OK!")
util.info_msg ("Presence variable OK (%x)!" % util.bitvector(data, 0, 8*6) )
test_result['Data field'] = 1
elif (data == 0x0):
......@@ -194,7 +194,7 @@ def test_txerr( dut, box, maxtries = 50 ):
time.sleep(0.5)
########################################################################
util.section_msg("Checking if TX_ERR is not going active during normal transmission")
util.info_msg("\nChecking if TX_ERR is not going active during normal transmission")
dut.rst_core()
util.info_msg("TX_ERR counter before transmission: %d" % dut.fippts.read_regname('fd_txerr_cnt') )
......@@ -222,7 +222,7 @@ def test_txerr( dut, box, maxtries = 50 ):
util.section_msg("Checking if TX_ERR IS going active during corrupted transmission (serial output is constant 1)")
dut.rst_core()
util.info_msg("TX_ERR counter before transmission: %d" % dut.fippts.read_regname('fd_txerr_cnt') )
util.info_msg("\nTX_ERR counter before transmission: %d" % dut.fippts.read_regname('fd_txerr_cnt') )
# corrupting serial output!!!!!
dut.fippts.write_regname('tx_corrupt',1)
......@@ -277,7 +277,7 @@ def test_wdgn( dut ):
###################### test ##################################################
########################################################################
util.section_msg("Checking if WDG_N becomes active during normal transmission")
util.info_msg("\nChecking if WDG_N becomes active during normal transmission")
dut.rst_core()
dut.fipcore.write_regname('tx_ctrl', 1)
......@@ -296,7 +296,7 @@ def test_wdgn( dut ):
result['WDG_N during correct transmission'] = tmp
###################### test ##################################################
util.section_msg("Checking if WDG_N becomes active during very long transmission")
util.info_msg("\nChecking if WDG_N becomes active during very long transmission")
dut.rst_core()
dut.fipcore.write_regname('tx_ctrl', 1)
......@@ -329,7 +329,7 @@ def test_wdgn( dut ):
util.info_msg( "WDG_N was active after corrupted transmission finished" )
result['WDG_N latch in FieldDrive'] = 1
util.section_msg("Checking FieldDrive RST_N line")
util.info_msg("\nTesting FieldDrive RST_N line")
util.info_msg("Reseting FieldDrive chip")
dut.rst_fd()
......
python/test04.py
View file @ 30c3283c
......@@ -69,17 +69,17 @@ def main (card=None, default_directory='.',suite=None, serial=""):
temperature = dut.get_temp()
if (temperature >= util.mintemp) and (temperature <= util.maxtemp):
util.info_msg("Read correct board temperature: %d" % temperature)
util.info_msg("Read correct board temperature: %d oC" % temperature)
test_results['Temperature value'] = 1
break
else:
test_results['Temperature value'] = 0
if temperature > util.maxtemp:
util.err_msg( "Temperature exceeds %d C" % util.maxtemp )
util.err_msg( "Temperature exceeds %d oC" % util.maxtemp )
else :
util.err_msg( "Temperature is lower then %d C" % util.mintemp )
util.err_msg( "Temperature is lower then %d oC" % util.mintemp )
###############################################################################
......
python/test05.py
View file @ 30c3283c
......@@ -126,16 +126,26 @@ def main (card=None, default_directory='.',suite=None, serial=None):
# create FRU information
util.section_msg("Creating IPMI-FRU information")
ipmi_vendor = "CERN"
ipmi_name = "fmc-masterfip"
ipmi_part = "EDA-03098-V3-%d" % speed
util.info_msg("Vendor: %s" % ipmi_vendor )
util.info_msg("Name: %s" % ipmi_name )
util.info_msg("Part: %s" % ipmi_part )
util.info_msg("Serial: %s" % serial )
subprocess.call(
[fru_gen_path,
# vendor
"-v", "CERN",
"-v %s" % ipmi_vendor,
# name
"-n", "fmc-masterfip",
"-n %s" % ipmi_name,
# serial
"-s", serial,
# part
"-p", "EDA-03098-V3-%d" % speed,
"-p %s" % ipmi_part,
# output
"-o", sdbfs_path+"/IPMI-FRU" ]
)
......@@ -155,7 +165,7 @@ def main (card=None, default_directory='.',suite=None, serial=None):
# write generated file to EEPROM
util.info_msg("Writing EEPROM")
util.section_msg("Writing EEPROM")
cnt = 0
with open(output_file, "rb") as f:
byte = f.read(1)
......
python/test06.py
View file @ 30c3283c
......@@ -126,7 +126,7 @@ def test_oen( dut, box ):
result = {}
util.section_msg("Testing output enable")
util.section_msg("Testing buffer output enable")
###############################################################################
......@@ -187,8 +187,9 @@ def test_dir( dut, box ):
result = {}
util.section_msg("Testing direction selection")
util.section_msg("Hack: Synchronisation input test will be repeated, with external buffer set to output")
util.section_msg("Hack: Value read on FPGA input shouldn't change, although synchronisation input changes")
util.info_msg("Hack: Synchronisation input test will be repeated, with external buffer set to output")
util.info_msg("Hack: Value read on FPGA input shouldn't change, although synchronisation input changes")
util.section_msg("Testing direction selection")
###############################################################################
......
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