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MasterFIP - Testing
Commit 30c3283c authored by Marek Gumiński's avatar Marek Gumiński
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Small fixes in python scripts. 

Output binary not included!!!!
Removed one of CPU cores from mockturtle.
Fixed path bug in pts/fmcmasterfip.py
Update csr interfaces for updated gw-masterfip.
parent ca15afbd
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Showing with 470 additions and 53355 deletions
gateware/rtl/masterFIP_pkg.vhd 0 → 100644
View file @ 30c3283c
--_________________________________________________________________________________________________
-- |
-- |masterFIP core| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- masterFIP_pkg |
-- |
---------------------------------------------------------------------------------------------------
-- File masterFIP_pkg.vhd |
-- |
-- Description Definitions of constants, types, entities related to the interface between the |
-- fmc_masterfip_core and the Mock Turtle. |
-- Note that a different package, the wf_package, is used for the WorldFIP specific |
-- constant, types, entities and for the clock constants. |
-- |
-- Author Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
use work.wf_package.all; -- WorldFIP specifics package
use work.masterfip_wbgen2_pkg.all; -- for the masterfip_wbgen2_csr records
--=================================================================================================
-- Package declaration for masterFIP_pkg
--=================================================================================================
package masterFIP_pkg is
---------------------------------------------------------------------------------------------------
-- Interface with MT --
-- Array of words with the WorldFIP produced/consumed PAYLOAD bytes --
---------------------------------------------------------------------------------------------------
constant C_BYTE_WIDTH : integer := 8;
constant C_WORD_WIDTH : integer := 32;
-- Declaration of a structure with 67 words of 32-bit each = 268 bytes which represent the max
-- length of a frame, including
-- FSS (2 bytes),
-- CTRL (1 byte),
-- Data (up to 262 for a message),
-- CRC (2 bytes) and
-- FES (1 byte).
-- Note that the deserializer, is registering bytes one by one as they arrive, after the FSS and
-- until the FES detection; therefore the max amount of bytes expected to be counted by the
-- deserializer is 266. Upon the rx_fss_crc_fes_ok_p_o the processor needs to read the rx_ctrl_byte
-- (separate register, not included in the rx_frame structure) and rx_byte_index_o-4 bytes from the
-- rx_frame structure (minus the CTRL, CRC and FES bytes).
-- Note that the serializer, is counting one by one the bytes that are serialized, after the FSS and
-- before the CRC; therefore the max amount of bytes expected to be counted by the serializer is
-- 263.
constant C_MAX_FRAME_WORDS : integer := 255;
constant C_FRAME_WORDS_CNT_LGTH : integer := 8; -- ((std_logic_vector(C_MAX_FRAME_WORDS))'left)
constant C_FRAME_BYTES_CNT_LGTH : integer := 10; -- (((std_logic_vector(C_MAX_FRAME_WORDS) srl 2))'left)
subtype data_word is std_logic_vector(C_WORD_WIDTH-1 downto 0);
type rx_frame_t is array (C_MAX_FRAME_WORDS-1 downto 0) of data_word;
-- Note that the serializer is not provided with the CRC and FES; the processor needs to provide
-- the CTRL byte (in a separate register, not included in the rx_frame structure) and up to
-- 262 Data bytes. In principle 66 data_words would be sufficient, but for symmetry with rx we kept 67.
type tx_frame_t is array (C_MAX_FRAME_WORDS-1 downto 0) of data_word;
---------------------------------------------------------------------------------------------------
-- Constants regarding the One-Wire interface --
---------------------------------------------------------------------------------------------------
-- constant c_FMC_ONEWIRE_NB : integer := 1;
---------------------------------------------------------------------------------------------------
-- Constant regarding the deglitch filters --
---------------------------------------------------------------------------------------------------
-- constant c_DEGLITCH_THRESHOLD : natural := 10; -- declared in the wf_package
---------------------------------------------------------------------------------------------------
-- Components Declarations: --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
component fmc_masterFIP_core is
generic
(g_span : integer := 32;
g_width : integer := 32;
values_for_simul : boolean := FALSE);
port
(clk_i : in std_logic;
rst_n_i : in std_logic;
speed_b0_i : in std_logic;
speed_b1_i : in std_logic;
onewire_b : inout std_logic;
fd_rxcdn_a_i : in std_logic;
fd_rxd_a_i : in std_logic;
fd_txer_a_i : in std_logic;
fd_wdgn_a_i : in std_logic;
fd_rstn_o : out std_logic;
fd_txck_o : out std_logic;
fd_txd_o : out std_logic;
fd_txena_o : out std_logic;
ext_sync_term_en_o : out std_logic;
ext_sync_dir_o : out std_logic;
ext_sync_oe_n_o : out std_logic;
ext_sync_a_i : in std_logic;
leds_o : out std_logic_vector(g_width-1 downto 0);
wb_adr_i : in std_logic_vector(g_span-1 downto 0);
wb_dat_i : in std_logic_vector(g_width-1 downto 0);
wb_stb_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_we_i : in std_logic;
wb_cyc_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_dat_o : out std_logic_vector(g_width-1 downto 0));
end component;
---------------------------------------------------------------------------------------------------
component masterfip_wbgen2_csr is
port
(rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(7 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
regs_i : in t_masterfip_in_registers;
regs_o : out t_masterfip_out_registers);
end component;
----------------------------------------------------------------------------------------------------
component masterfip_rx is
port
(clk_i : in std_logic;
speed_i : in std_logic_vector(1 downto 0);
rx_d_a_i : in std_logic;
rst_i : in std_logic;
rx_rst_i : in std_logic;
rx_byte_index_o : out std_logic_vector(C_FRAME_BYTES_CNT_LGTH-1 downto 0);
rx_word_index_o : out std_logic_vector(C_FRAME_WORDS_CNT_LGTH-1 downto 0);
rx_ctrl_byte_o : out std_logic_vector(C_BYTE_WIDTH-1 downto 0);
rx_frame_o : out rx_frame_t;
rx_byte_o : out std_logic_vector(C_BYTE_WIDTH-1 downto 0);
rx_byte_ready_p_o : out std_logic;
rx_fss_crc_fes_ok_p_o : out std_logic;
rx_fss_received_p_o : out std_logic;
rx_crc_wrong_p_o : out std_logic );
end component masterfip_rx;
---------------------------------------------------------------------------------------------------
component masterfip_tx is
port
(clk_i : in std_logic;
speed_i : in std_logic_vector(1 downto 0);
rst_i : in std_logic;
tx_start_p_i : in std_logic;
tx_bytes_num_i : in std_logic_vector(C_FRAME_BYTES_CNT_LGTH-1 downto 0);
tx_frame_i : in tx_frame_t;
tx_ctrl_byte_i : in std_logic_vector(C_BYTE_WIDTH-1 downto 0);
tx_byte_index_o : out std_logic_vector(C_FRAME_BYTES_CNT_LGTH-1 downto 0);
tx_end_p_o : out std_logic;
tx_d_o : out std_logic;
tx_ena_o : out std_logic;
tx_clk_o : out std_logic);
end component masterfip_tx;
---------------------------------------------------------------------------------------------------
component decr_counter
generic
(width : integer := 32);
port
(clk_i : in std_logic;
rst_i : in std_logic;
counter_load_i : in std_logic;
counter_top_i : in std_logic_vector(width-1 downto 0);
counter_is_zero_o : out std_logic;
counter_o : out std_logic_vector(width-1 downto 0));
end component;
---------------------------------------------------------------------------------------------------
component incr_counter is
generic
(g_counter_lgth : natural := 4);
port
(clk_i : in std_logic;
counter_incr_i : in std_logic;
counter_reinit_i : in std_logic;
counter_o : out std_logic_vector(g_counter_lgth-1 downto 0);
counter_is_full_o : out std_logic);
end component incr_counter;
--=================================================================================================
-- package end
--=================================================================================================
end masterFIP_pkg;
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
gateware/rtl/wbgen/masterfip_csr.vhd
View file @ 30c3283c
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_csr.vhd
-- Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/ip_cores/gw-masterfip/rtl/wbgen/masterfip_csr.wb
-- Created : Mon Apr 3 13:15:22 2017
-- Created : Mon Apr 24 10:20:14 2017
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/ip_cores/gw-masterfip/rtl/wbgen/masterfip_csr.wb
......@@ -39,8 +39,6 @@ entity masterfip_wbgen2_csr is
masterfip_led_tx_act_o : out std_logic;
-- Port for BIT field: 'tx err red led' in reg: 'leds and debug'
masterfip_led_tx_err_o : out std_logic;
-- Port for BIT field: 'write 1 to indicate that the ext sync is used' in reg: 'leds and debug'
masterfip_led_ext_sync_used_o : out std_logic;
-- Port for BIT field: 'ext sync act green led' in reg: 'leds and debug'
masterfip_led_ext_sync_act_o : out std_logic;
-- Port for BIT field: 'ext sync err red led' in reg: 'leds and debug'
......@@ -61,6 +59,10 @@ entity masterfip_wbgen2_csr is
masterfip_ext_sync_ctrl_oe_n_o : out std_logic;
-- Port for BIT field: 'pulses counter reset' in reg: 'ext sync ctrl'
masterfip_ext_sync_ctrl_p_cnt_rst_o : out std_logic;
-- Port for BIT field: 'counting options' in reg: 'ext sync ctrl'
masterfip_ext_sync_ctrl_opt_o : out std_logic;
-- Port for BIT field: 'safe window' in reg: 'ext sync ctrl'
masterfip_ext_sync_ctrl_safe_wind_o : out std_logic;
-- Port for std_logic_vector field: 'ext_sync_p_cnt' in reg: 'ext sync pulses cnt'
masterfip_ext_sync_p_cnt_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'WorldFIP speed, hard-wired on the FMC' in reg: 'bus speed'
......@@ -90,13 +92,13 @@ entity masterfip_wbgen2_csr is
-- Port for MONOSTABLE field: 'tx strt' in reg: 'tx ctrl'
masterfip_tx_ctrl_start_o : out std_logic;
-- Port for std_logic_vector field: 'tx number of bytes' in reg: 'tx ctrl'
masterfip_tx_ctrl_bytes_num_o : out std_logic_vector(8 downto 0);
masterfip_tx_ctrl_bytes_num_o : out std_logic_vector(15 downto 0);
-- Port for BIT field: 'tx ended' in reg: 'tx status'
masterfip_tx_stat_stop_i : in std_logic;
-- Port for BIT field: 'tx enable' in reg: 'tx status'
masterfip_tx_stat_ena_i : in std_logic;
-- Port for std_logic_vector field: 'tx status current byte index' in reg: 'tx status'
masterfip_tx_stat_curr_byte_indx_i : in std_logic_vector(8 downto 0);
masterfip_tx_stat_curr_byte_indx_i : in std_logic_vector(15 downto 0);
-- Port for BIT field: 'FielDrive watchdog' in reg: 'FielDrive wdgn, cdn'
masterfip_fd_wdg_i : in std_logic;
-- Port for BIT field: 'FielDrive carrier detect' in reg: 'FielDrive wdgn, cdn'
......@@ -116,9 +118,9 @@ entity masterfip_wbgen2_csr is
-- Port for BIT field: 'rx frame crc error' in reg: 'rx status'
masterfip_rx_stat_frame_crc_err_i : in std_logic;
-- Port for std_logic_vector field: 'rx number of payload bytes' in reg: 'rx status'
masterfip_rx_stat_bytes_num_i : in std_logic_vector(8 downto 0);
masterfip_rx_stat_bytes_num_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'current word index' in reg: 'rx current word index'
masterfip_rx_stat_curr_word_indx_i : in std_logic_vector(6 downto 0);
masterfip_rx_stat_curr_word_indx_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'rx number of frames with CRC error' in reg: 'rx num of frames with CRC error'
masterfip_rx_stat_crc_err_cnt_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'rx payload ctrl byte' in reg: 'rx payload ctrl byte'
......@@ -406,7 +408,6 @@ signal masterfip_led_rx_act_int : std_logic ;
signal masterfip_led_rx_err_int : std_logic ;
signal masterfip_led_tx_act_int : std_logic ;
signal masterfip_led_tx_err_int : std_logic ;
signal masterfip_led_ext_sync_used_int : std_logic ;
signal masterfip_led_ext_sync_act_int : std_logic ;
signal masterfip_led_ext_sync_err_int : std_logic ;
signal masterfip_led_dbg_int : std_logic_vector(23 downto 0);
......@@ -414,6 +415,8 @@ signal masterfip_ext_sync_ctrl_term_en_int : std_logic ;
signal masterfip_ext_sync_ctrl_dir_int : std_logic ;
signal masterfip_ext_sync_ctrl_oe_n_int : std_logic ;
signal masterfip_ext_sync_ctrl_p_cnt_rst_int : std_logic ;
signal masterfip_ext_sync_ctrl_opt_int : std_logic ;
signal masterfip_ext_sync_ctrl_safe_wind_int : std_logic ;
signal masterfip_macrocyc_lgth_int : std_logic_vector(30 downto 0);
signal masterfip_macrocyc_start_dly0 : std_logic ;
signal masterfip_macrocyc_start_int : std_logic ;
......@@ -427,7 +430,7 @@ signal masterfip_tx_ctrl_rst_dly0 : std_logic ;
signal masterfip_tx_ctrl_rst_int : std_logic ;
signal masterfip_tx_ctrl_start_dly0 : std_logic ;
signal masterfip_tx_ctrl_start_int : std_logic ;
signal masterfip_tx_ctrl_bytes_num_int : std_logic_vector(8 downto 0);
signal masterfip_tx_ctrl_bytes_num_int : std_logic_vector(15 downto 0);
signal masterfip_rx_ctrl_rst_dly0 : std_logic ;
signal masterfip_rx_ctrl_rst_int : std_logic ;
signal masterfip_tx_payld_ctrl_int : std_logic_vector(7 downto 0);
......@@ -531,7 +534,6 @@ begin
masterfip_led_rx_err_int <= '0';
masterfip_led_tx_act_int <= '0';
masterfip_led_tx_err_int <= '0';
masterfip_led_ext_sync_used_int <= '0';
masterfip_led_ext_sync_act_int <= '0';
masterfip_led_ext_sync_err_int <= '0';
masterfip_led_dbg_int <= "000000000000000000000000";
......@@ -539,6 +541,8 @@ begin
masterfip_ext_sync_ctrl_dir_int <= '0';
masterfip_ext_sync_ctrl_oe_n_int <= '0';
masterfip_ext_sync_ctrl_p_cnt_rst_int <= '0';
masterfip_ext_sync_ctrl_opt_int <= '0';
masterfip_ext_sync_ctrl_safe_wind_int <= '0';
masterfip_macrocyc_lgth_int <= "0000000000000000000000000000000";
masterfip_macrocyc_start_int <= '0';
masterfip_turnar_lgth_int <= "0000000000000000000000000000000";
......@@ -547,7 +551,7 @@ begin
masterfip_silen_start_int <= '0';
masterfip_tx_ctrl_rst_int <= '0';
masterfip_tx_ctrl_start_int <= '0';
masterfip_tx_ctrl_bytes_num_int <= "000000000";
masterfip_tx_ctrl_bytes_num_int <= "0000000000000000";
masterfip_rx_ctrl_rst_int <= '0';
masterfip_tx_payld_ctrl_int <= "00000000";
masterfip_tx_payld_reg1_int <= "00000000000000000000000000000000";
......@@ -690,19 +694,18 @@ begin
masterfip_led_rx_err_int <= wrdata_reg(1);
masterfip_led_tx_act_int <= wrdata_reg(2);
masterfip_led_tx_err_int <= wrdata_reg(3);
masterfip_led_ext_sync_used_int <= wrdata_reg(4);
masterfip_led_ext_sync_act_int <= wrdata_reg(5);
masterfip_led_ext_sync_err_int <= wrdata_reg(6);
masterfip_led_ext_sync_act_int <= wrdata_reg(4);
masterfip_led_ext_sync_err_int <= wrdata_reg(5);
masterfip_led_dbg_int <= wrdata_reg(31 downto 8);
end if;
rddata_reg(0) <= masterfip_led_rx_act_int;
rddata_reg(1) <= masterfip_led_rx_err_int;
rddata_reg(2) <= masterfip_led_tx_act_int;
rddata_reg(3) <= masterfip_led_tx_err_int;
rddata_reg(4) <= masterfip_led_ext_sync_used_int;
rddata_reg(5) <= masterfip_led_ext_sync_act_int;
rddata_reg(6) <= masterfip_led_ext_sync_err_int;
rddata_reg(4) <= masterfip_led_ext_sync_act_int;
rddata_reg(5) <= masterfip_led_ext_sync_err_int;
rddata_reg(31 downto 8) <= masterfip_led_dbg_int;
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
......@@ -746,11 +749,15 @@ begin
masterfip_ext_sync_ctrl_dir_int <= wrdata_reg(1);
masterfip_ext_sync_ctrl_oe_n_int <= wrdata_reg(2);
masterfip_ext_sync_ctrl_p_cnt_rst_int <= wrdata_reg(8);
masterfip_ext_sync_ctrl_opt_int <= wrdata_reg(16);
masterfip_ext_sync_ctrl_safe_wind_int <= wrdata_reg(24);
end if;
rddata_reg(0) <= masterfip_ext_sync_ctrl_term_en_int;
rddata_reg(1) <= masterfip_ext_sync_ctrl_dir_int;
rddata_reg(2) <= masterfip_ext_sync_ctrl_oe_n_int;
rddata_reg(8) <= masterfip_ext_sync_ctrl_p_cnt_rst_int;
rddata_reg(16) <= masterfip_ext_sync_ctrl_opt_int;
rddata_reg(24) <= masterfip_ext_sync_ctrl_safe_wind_int;
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
......@@ -763,7 +770,6 @@ begin
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
......@@ -771,7 +777,6 @@ begin
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
......@@ -881,24 +886,17 @@ begin
if (wb_we_i = '1') then
masterfip_tx_ctrl_rst_int <= wrdata_reg(0);
masterfip_tx_ctrl_start_int <= wrdata_reg(1);
masterfip_tx_ctrl_bytes_num_int <= wrdata_reg(16 downto 8);
masterfip_tx_ctrl_bytes_num_int <= wrdata_reg(23 downto 8);
end if;
rddata_reg(0) <= '0';
rddata_reg(1) <= '0';
rddata_reg(16 downto 8) <= masterfip_tx_ctrl_bytes_num_int;
rddata_reg(23 downto 8) <= masterfip_tx_ctrl_bytes_num_int;
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
......@@ -914,7 +912,7 @@ begin
end if;
rddata_reg(0) <= masterfip_tx_stat_stop_i;
rddata_reg(8) <= masterfip_tx_stat_ena_i;
rddata_reg(17 downto 9) <= masterfip_tx_stat_curr_byte_indx_i;
rddata_reg(31 downto 16) <= masterfip_tx_stat_curr_byte_indx_i;
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
......@@ -922,20 +920,13 @@ begin
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010010" =>
......@@ -1037,19 +1028,12 @@ begin
rddata_reg(0) <= masterfip_rx_stat_pream_ok_i;
rddata_reg(1) <= masterfip_rx_stat_frame_ok_i;
rddata_reg(2) <= masterfip_rx_stat_frame_crc_err_i;
rddata_reg(16 downto 8) <= masterfip_rx_stat_bytes_num_i;
rddata_reg(23 downto 8) <= masterfip_rx_stat_bytes_num_i;
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
......@@ -1063,8 +1047,7 @@ begin
when "00011000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(6 downto 0) <= masterfip_rx_stat_curr_word_indx_i;
rddata_reg(7) <= 'X';
rddata_reg(7 downto 0) <= masterfip_rx_stat_curr_word_indx_i;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
......@@ -2076,8 +2059,6 @@ begin
masterfip_led_tx_act_o <= masterfip_led_tx_act_int;
-- tx err red led
masterfip_led_tx_err_o <= masterfip_led_tx_err_int;
-- write 1 to indicate that the ext sync is used
masterfip_led_ext_sync_used_o <= masterfip_led_ext_sync_used_int;
-- ext sync act green led
masterfip_led_ext_sync_act_o <= masterfip_led_ext_sync_act_int;
-- ext sync err red led
......@@ -2095,6 +2076,10 @@ begin
masterfip_ext_sync_ctrl_oe_n_o <= masterfip_ext_sync_ctrl_oe_n_int;
-- pulses counter reset
masterfip_ext_sync_ctrl_p_cnt_rst_o <= masterfip_ext_sync_ctrl_p_cnt_rst_int;
-- counting options
masterfip_ext_sync_ctrl_opt_o <= masterfip_ext_sync_ctrl_opt_int;
-- safe window
masterfip_ext_sync_ctrl_safe_wind_o <= masterfip_ext_sync_ctrl_safe_wind_int;
-- ext_sync_p_cnt
-- WorldFIP speed, hard-wired on the FMC
-- macrocycle lgth
......
gateware/rtl/wbgen/masterfip_pts_csr.vhd
View file @ 30c3283c
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.vhd
-- Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.wb
-- Created : Mon Apr 3 13:15:24 2017
-- Created : Mon Apr 24 10:20:17 2017
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.wb
......
gateware/top/spec/spec_masterfip_pts.ucf
View file @ 30c3283c
......@@ -286,7 +286,7 @@ TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk" TNM_NET = U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk;
TIMESPEC TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_P_clk = PERIOD "U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback" TNM_NET = U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback;
TIMESPEC TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_feedback = PERIOD "U_Node_Template/U_GN4124_Core/cmp_clk_in/feedback" 5 ns HIGH 50%;
TIMESPEC TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_feedback = PERIOD "U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback" 5 ns HIGH 50%;
NET "l_rst_n_i" TIG;
NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/rst_*" TIG;
\ No newline at end of file
gateware/top/spec/spec_masterfip_pts.vhd
View file @ 30c3283c
......@@ -319,8 +319,8 @@ architecture rtl of spec_masterfip_pts is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
constant C_NODE_CONFIG : t_wr_node_config :=
(app_id => x"0f1dc03e",
cpu_count => 2,
cpu_memsizes => (98304, 8192, 0, 0, 0, 0, 0, 0), -- in bytes; for CPU0 the size should be enough
cpu_count => 1,
cpu_memsizes => (98304, 0, 0, 0, 0, 0, 0, 0), -- in bytes; for CPU0 the size should be enough
-- for the storage of the RT sw running on CPU0
-- and for the macrocycle configuration
hmq_config => C_HMQ_CONFIG,
......@@ -362,8 +362,8 @@ architecture rtl of spec_masterfip_pts is
signal clk_100m_sys : std_logic;
signal rst_n_sys : std_logic;
-- Mock Turtle
signal wbmain_masters_ms : t_wishbone_master_out_array(2 downto 0);
signal wbmain_masters_sm : t_wishbone_master_in_array(2 downto 0);
signal wbmain_masters_ms : t_wishbone_master_out_array(1 downto 0);
signal wbmain_masters_sm : t_wishbone_master_in_array(1 downto 0);
signal wbmain_slaves_ms : t_wishbone_master_out_array(c_NUM_WB_SLAVES-1 downto 0);
signal wbmain_slaves_sm : t_wishbone_master_in_array(c_NUM_WB_SLAVES-1 downto 0);
-- SPEC LEDs
......@@ -453,12 +453,12 @@ begin
fmc_prsnt_m2c_l_i => fmc_prsnt_m2c_n_i,
-- WISHBONE connection of the fmc_masterFIP_core to the MT CPUs
dp_master_o(0) => wbmain_masters_ms(0), -- access from MT CPU0 at base address 0x100000
dp_master_o(1) => wbmain_masters_ms(1),
-- dp_master_o(1) => wbmain_masters_ms(1),
dp_master_i(0) => wbmain_masters_sm(0), -- access from MT CPU1 at base address 0x100000
dp_master_i(1) => wbmain_masters_sm(1),
-- dp_master_i(1) => wbmain_masters_sm(1),
-- WISHBONE connection of the fmc_masterFIP_core to the host
fmc0_host_wb_o => wbmain_masters_ms(2), -- access from PCIe host at base address 0x10000
fmc0_host_wb_i => wbmain_masters_sm(2),
fmc0_host_wb_o => wbmain_masters_ms(1), -- access from PCIe host at base address 0x10000
fmc0_host_wb_i => wbmain_masters_sm(1),
fmc0_host_irq_i => '0',
-- not used
clk_20m_vcxo_i => '0',
......@@ -477,7 +477,7 @@ begin
-- purposes. The PCIe host is accessing the core directly only for testing purposes.
cmp_wb_crossbar : xwb_crossbar
generic map
(g_num_masters => 3,
(g_num_masters => 2,
g_num_slaves => c_NUM_WB_SLAVES,
g_registered => true,
g_address => C_SLAVE_ADDR,
......
pts/fmcmasterfip.sh
View file @ 30c3283c
......@@ -141,7 +141,7 @@ do
echo " "
# run tests
sudo ${top}/pts/ptsFip.py -b FmcMasterFip -s $serial -e $extra_serial -t../python -l $LOGDIR 00 01 02 04 05 06
sudo ${top}/pts/ptsFip.py -b FmcMasterFip -s $serial -e $extra_serial "-t${top}/python -l $LOGDIR 00 01 02 04 05 06
# backup eeprom image
......
python/regs/carrier_addrtable.py
View file @ 30c3283c
......@@ -2,7 +2,7 @@
#
# * File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/python/regs/carrier_addrtable.py
# * Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/carrier_csr.wb
# * Created : Mon Apr 3 13:15:22 2017
# * Created : Mon Apr 24 10:20:14 2017
#
# THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/carrier_csr.wb
# DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
......
python/regs/masterfip_addrtable.htm deleted 100644 → 0
View file @ ca15afbd
This source diff could not be displayed because it is too large. You can view the blob instead.
python/regs/masterfip_addrtable.py deleted 100644 → 0
View file @ ca15afbd
# Register definitions for slave core: FMC masterFIP core registers
#
# * File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/python/regs/masterfip_addrtable.py
# * Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/fmc_masterfip_csr.wb
# * Created : Thu Mar 30 13:56:49 2017
#
# THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/fmc_masterfip_csr.wb
# DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
#
addr = {
'rstn' : [ 0x0, 0xffffffff, "rw"],
'rstn.core' : [ 0x0, 0x1, "rw"],
'rstn.fd' : [ 0x0, 0x2, "rw"],
'rstn.lock' : [ 0x0, 0xFFFF0000, "rw"],
'led' : [ 0x1, 0xffffffff, "rw"],
'led.out_of_sync' : [ 0x1, 0x1, "rw"],
'led.rx_err' : [ 0x1, 0x2, "rw"],
'led.rx_act' : [ 0x1, 0x4, "rw"],
'led.sync' : [ 0x1, 0x8, "rw"],
'led.tx_act' : [ 0x1, 0x10, "rw"],
'led.tx_err' : [ 0x1, 0x20, "rw"],
'id' : [ 0x2, 0xffffffff, "r"],
'dbg' : [ 0x3, 0xffffffff, "rw"],
'adc' : [ 0x4, 0xffffffff, "rw"],
'adc.1v8_shdn_n' : [ 0x4, 0x1, "rw"],
'adc.m5v_shdn_n' : [ 0x4, 0x2, "rw"],
'adc.5v_en' : [ 0x4, 0x4, "rw"],
'adc.prim_conn' : [ 0x4, 0x100, "rw"],
'adc.sec_conn' : [ 0x4, 0x200, "rw"],
'ext_sync' : [ 0x5, 0xffffffff, "rw"],
'ext_sync.term_en' : [ 0x5, 0x1, "rw"],
'ext_sync.dir' : [ 0x5, 0x2, "rw"],
'ext_sync.oe' : [ 0x5, 0x4, "rw"],
'ext_sync.tst' : [ 0x5, 0x8, "rw"],
'ext_sync.output_value' : [ 0x5, 0x10, "rw"],
'ext_sync.p_cnt_rst' : [ 0x5, 0x100, "rw"],
'ext_sync.fpga_io_dir' : [ 0x5, 0x200, "rw"],
'ext_sync_raw_input' : [ 0x6, 0xffffffff, "r"],
'ext_sync_p_cnt' : [ 0x7, 0xffffffff, "r"],
'test' : [ 0x8, 0xffffffff, "rw"],
'speed' : [ 0x9, 0xffffffff, "r"],
'macrocyc' : [ 0xA, 0xffffffff, "rw"],
'macrocyc.lgth' : [ 0xA, 0x7FFFFFFF, "rw"],
'macrocyc.start' : [ 0xA, 0x80000000, "rw"],
'turnar' : [ 0xB, 0xffffffff, "rw"],
'turnar.lgth' : [ 0xB, 0x7FFFFFFF, "rw"],
'turnar.start' : [ 0xB, 0x80000000, "rw"],
'silen' : [ 0xC, 0xffffffff, "rw"],
'silen.lgth' : [ 0xC, 0x7FFFFFFF, "rw"],
'silen.start' : [ 0xC, 0x80000000, "rw"],
'macrocyc_time_cnt' : [ 0xD, 0xffffffff, "r"],
'macrocyc_num_cnt' : [ 0xE, 0xffffffff, "r"],
'turnar_time_cnt' : [ 0xF, 0xffffffff, "r"],
'silen_time_cnt' : [ 0x10, 0xffffffff, "r"],
'tx_ctrl' : [ 0x11, 0xffffffff, "rw"],
'tx_ctrl.rst' : [ 0x11, 0x1, "rw"],
'tx_ctrl.start' : [ 0x11, 0x2, "rw"],
'tx_ctrl.bytes_num' : [ 0x11, 0xFFFF00, "rw"],
'tx_stat' : [ 0x12, 0xffffffff, "r"],
'tx_stat.stop' : [ 0x12, 0x1, "r"],
'tx_stat.byte_index' : [ 0x12, 0xFFFF00, "r"],
'tx_stat.ena' : [ 0x12, 0x1000000, "r"],
'fd' : [ 0x13, 0xffffffff, "r"],
'fd.wdgn' : [ 0x13, 0x1, "r"],
'fd.wdgn_latch' : [ 0x13, 0x2, "r"],
'fd.cd_n' : [ 0x13, 0x4, "r"],
'fd.txer' : [ 0x13, 0x8, "r"],
'fd_txerr_cnt' : [ 0x14, 0xffffffff, "r"],
'rx_ctrl' : [ 0x15, 0xffffffff, "rw"],
'rx_stat' : [ 0x16, 0xffffffff, "r"],
'rx_stat.pream_ok' : [ 0x16, 0x1, "r"],
'rx_stat.frame_ok' : [ 0x16, 0x2, "r"],
'rx_stat.frame_err' : [ 0x16, 0x4, "r"],
'rx_stat.frame_err_code' : [ 0x16, 0x38, "r"],
'rx_stat.bytes_num' : [ 0x16, 0xFFFF00, "r"],
'fd_rxcdn_cnt' : [ 0x17, 0xffffffff, "r"],
'rx_data_ctrl' : [ 0x18, 0xffffffff, "r"],
'rx_data_reg1' : [ 0x19, 0xffffffff, "r"],
'rx_data_reg2' : [ 0x1A, 0xffffffff, "r"],
'rx_data_reg3' : [ 0x1B, 0xffffffff, "r"],
'rx_data_reg4' : [ 0x1C, 0xffffffff, "r"],
'rx_data_reg5' : [ 0x1D, 0xffffffff, "r"],
'rx_data_reg6' : [ 0x1E, 0xffffffff, "r"],
'rx_data_reg7' : [ 0x1F, 0xffffffff, "r"],
'rx_data_reg8' : [ 0x20, 0xffffffff, "r"],
'rx_data_reg9' : [ 0x21, 0xffffffff, "r"],
'rx_data_reg10' : [ 0x22, 0xffffffff, "r"],
'rx_data_reg11' : [ 0x23, 0xffffffff, "r"],
'rx_data_reg12' : [ 0x24, 0xffffffff, "r"],
'rx_data_reg13' : [ 0x25, 0xffffffff, "r"],
'rx_data_reg14' : [ 0x26, 0xffffffff, "r"],
'rx_data_reg15' : [ 0x27, 0xffffffff, "r"],
'rx_data_reg16' : [ 0x28, 0xffffffff, "r"],
'rx_data_reg17' : [ 0x29, 0xffffffff, "r"],
'rx_data_reg18' : [ 0x2A, 0xffffffff, "r"],
'rx_data_reg19' : [ 0x2B, 0xffffffff, "r"],
'rx_data_reg20' : [ 0x2C, 0xffffffff, "r"],
'rx_data_reg21' : [ 0x2D, 0xffffffff, "r"],
'rx_data_reg22' : [ 0x2E, 0xffffffff, "r"],
'rx_data_reg23' : [ 0x2F, 0xffffffff, "r"],
'rx_data_reg24' : [ 0x30, 0xffffffff, "r"],
'rx_data_reg25' : [ 0x31, 0xffffffff, "r"],
'rx_data_reg26' : [ 0x32, 0xffffffff, "r"],
'rx_data_reg27' : [ 0x33, 0xffffffff, "r"],
'rx_data_reg28' : [ 0x34, 0xffffffff, "r"],
'rx_data_reg29' : [ 0x35, 0xffffffff, "r"],
'rx_data_reg30' : [ 0x36, 0xffffffff, "r"],
'rx_data_reg31' : [ 0x37, 0xffffffff, "r"],
'rx_data_reg32' : [ 0x38, 0xffffffff, "r"],
'rx_data_reg33' : [ 0x39, 0xffffffff, "r"],
'rx_data_reg34' : [ 0x3A, 0xffffffff, "r"],
'rx_data_reg35' : [ 0x3B, 0xffffffff, "r"],
'rx_data_reg36' : [ 0x3C, 0xffffffff, "r"],
'rx_data_reg37' : [ 0x3D, 0xffffffff, "r"],
'rx_data_reg38' : [ 0x3E, 0xffffffff, "r"],
'rx_data_reg39' : [ 0x3F, 0xffffffff, "r"],
'rx_data_reg40' : [ 0x40, 0xffffffff, "r"],
'rx_data_reg41' : [ 0x41, 0xffffffff, "r"],
'rx_data_reg42' : [ 0x42, 0xffffffff, "r"],
'rx_data_reg43' : [ 0x43, 0xffffffff, "r"],
'rx_data_reg44' : [ 0x44, 0xffffffff, "r"],
'rx_data_reg45' : [ 0x45, 0xffffffff, "r"],
'rx_data_reg46' : [ 0x46, 0xffffffff, "r"],
'rx_data_reg47' : [ 0x47, 0xffffffff, "r"],
'rx_data_reg48' : [ 0x48, 0xffffffff, "r"],
'rx_data_reg49' : [ 0x49, 0xffffffff, "r"],
'rx_data_reg50' : [ 0x4A, 0xffffffff, "r"],
'rx_data_reg51' : [ 0x4B, 0xffffffff, "r"],
'rx_data_reg52' : [ 0x4C, 0xffffffff, "r"],
'rx_data_reg53' : [ 0x4D, 0xffffffff, "r"],
'rx_data_reg54' : [ 0x4E, 0xffffffff, "r"],
'rx_data_reg55' : [ 0x4F, 0xffffffff, "r"],
'rx_data_reg56' : [ 0x50, 0xffffffff, "r"],
'rx_data_reg57' : [ 0x51, 0xffffffff, "r"],
'rx_data_reg58' : [ 0x52, 0xffffffff, "r"],
'rx_data_reg59' : [ 0x53, 0xffffffff, "r"],
'rx_data_reg60' : [ 0x54, 0xffffffff, "r"],
'rx_data_reg61' : [ 0x55, 0xffffffff, "r"],
'rx_data_reg62' : [ 0x56, 0xffffffff, "r"],
'rx_data_reg63' : [ 0x57, 0xffffffff, "r"],
'rx_data_reg64' : [ 0x58, 0xffffffff, "r"],
'rx_data_reg65' : [ 0x59, 0xffffffff, "r"],
'rx_data_reg66' : [ 0x5A, 0xffffffff, "r"],
'tx_data_ctrl' : [ 0x5B, 0xffffffff, "rw"],
'tx_data_reg1' : [ 0x5C, 0xffffffff, "rw"],
'tx_data_reg2' : [ 0x5D, 0xffffffff, "rw"],
'tx_data_reg3' : [ 0x5E, 0xffffffff, "rw"],
'tx_data_reg4' : [ 0x5F, 0xffffffff, "rw"],
'tx_data_reg5' : [ 0x60, 0xffffffff, "rw"],
'tx_data_reg6' : [ 0x61, 0xffffffff, "rw"],
'tx_data_reg7' : [ 0x62, 0xffffffff, "rw"],
'tx_data_reg8' : [ 0x63, 0xffffffff, "rw"],
'tx_data_reg9' : [ 0x64, 0xffffffff, "rw"],
'tx_data_reg10' : [ 0x65, 0xffffffff, "rw"],
'tx_data_reg11' : [ 0x66, 0xffffffff, "rw"],
'tx_data_reg12' : [ 0x67, 0xffffffff, "rw"],
'tx_data_reg13' : [ 0x68, 0xffffffff, "rw"],
'tx_data_reg14' : [ 0x69, 0xffffffff, "rw"],
'tx_data_reg15' : [ 0x6A, 0xffffffff, "rw"],
'tx_data_reg16' : [ 0x6B, 0xffffffff, "rw"],
'tx_data_reg17' : [ 0x6C, 0xffffffff, "rw"],
'tx_data_reg18' : [ 0x6D, 0xffffffff, "rw"],
'tx_data_reg19' : [ 0x6E, 0xffffffff, "rw"],
'tx_data_reg20' : [ 0x6F, 0xffffffff, "rw"],
'tx_data_reg21' : [ 0x70, 0xffffffff, "rw"],
'tx_data_reg22' : [ 0x71, 0xffffffff, "rw"],
'tx_data_reg23' : [ 0x72, 0xffffffff, "rw"],
'tx_data_reg24' : [ 0x73, 0xffffffff, "rw"],
'tx_data_reg25' : [ 0x74, 0xffffffff, "rw"],
'tx_data_reg26' : [ 0x75, 0xffffffff, "rw"],
'tx_data_reg27' : [ 0x76, 0xffffffff, "rw"],
'tx_data_reg28' : [ 0x77, 0xffffffff, "rw"],
'tx_data_reg29' : [ 0x78, 0xffffffff, "rw"],
'tx_data_reg30' : [ 0x79, 0xffffffff, "rw"],
'tx_data_reg31' : [ 0x7A, 0xffffffff, "rw"],
'tx_data_reg32' : [ 0x7B, 0xffffffff, "rw"],
'tx_data_reg33' : [ 0x7C, 0xffffffff, "rw"],
'tx_data_reg34' : [ 0x7D, 0xffffffff, "rw"],
'tx_data_reg35' : [ 0x7E, 0xffffffff, "rw"],
'tx_data_reg36' : [ 0x7F, 0xffffffff, "rw"],
'tx_data_reg37' : [ 0x80, 0xffffffff, "rw"],
'tx_data_reg38' : [ 0x81, 0xffffffff, "rw"],
'tx_data_reg39' : [ 0x82, 0xffffffff, "rw"],
'tx_data_reg40' : [ 0x83, 0xffffffff, "rw"],
'tx_data_reg41' : [ 0x84, 0xffffffff, "rw"],
'tx_data_reg42' : [ 0x85, 0xffffffff, "rw"],
'tx_data_reg43' : [ 0x86, 0xffffffff, "rw"],
'tx_data_reg44' : [ 0x87, 0xffffffff, "rw"],
'tx_data_reg45' : [ 0x88, 0xffffffff, "rw"],
'tx_data_reg46' : [ 0x89, 0xffffffff, "rw"],
'tx_data_reg47' : [ 0x8A, 0xffffffff, "rw"],
'tx_data_reg48' : [ 0x8B, 0xffffffff, "rw"],
'tx_data_reg49' : [ 0x8C, 0xffffffff, "rw"],
'tx_data_reg50' : [ 0x8D, 0xffffffff, "rw"],
'tx_data_reg51' : [ 0x8E, 0xffffffff, "rw"],
'tx_data_reg52' : [ 0x8F, 0xffffffff, "rw"],
'tx_data_reg53' : [ 0x90, 0xffffffff, "rw"],
'tx_data_reg54' : [ 0x91, 0xffffffff, "rw"],
'tx_data_reg55' : [ 0x92, 0xffffffff, "rw"],
'tx_data_reg56' : [ 0x93, 0xffffffff, "rw"],
'tx_data_reg57' : [ 0x94, 0xffffffff, "rw"],
'tx_data_reg58' : [ 0x95, 0xffffffff, "rw"],
'tx_data_reg59' : [ 0x96, 0xffffffff, "rw"],
'tx_data_reg60' : [ 0x97, 0xffffffff, "rw"],
'tx_data_reg61' : [ 0x98, 0xffffffff, "rw"],
'tx_data_reg62' : [ 0x99, 0xffffffff, "rw"],
'tx_data_reg63' : [ 0x9A, 0xffffffff, "rw"],
'tx_data_reg64' : [ 0x9B, 0xffffffff, "rw"],
'tx_data_reg65' : [ 0x9C, 0xffffffff, "rw"],
'tx_data_reg66' : [ 0x9D, 0xffffffff, "rw"],
'':[0,0]
}
python/regs/masterfip_csr.htm
View file @ 30c3283c
......@@ -3169,23 +3169,6 @@ masterfip_led_tx_err_o
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
masterfip_led_ext_sync_used_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
masterfip_led_ext_sync_act_o
......@@ -3489,6 +3472,40 @@ masterfip_ext_sync_ctrl_p_cnt_rst_o
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
masterfip_ext_sync_ctrl_opt_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
masterfip_ext_sync_ctrl_safe_wind_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
......@@ -4072,7 +4089,7 @@ masterfip_tx_ctrl_start_o
</td>
<td class="td_pblock_right">
masterfip_tx_ctrl_bytes_num_o[8:0]
masterfip_tx_ctrl_bytes_num_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -4157,7 +4174,7 @@ masterfip_tx_stat_ena_i
</td>
<td class="td_pblock_right">
masterfip_tx_stat_curr_byte_indx_i[8:0]
masterfip_tx_stat_curr_byte_indx_i[15:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -4531,7 +4548,7 @@ masterfip_rx_stat_frame_crc_err_i
</td>
<td class="td_pblock_right">
masterfip_rx_stat_bytes_num_i[8:0]
masterfip_rx_stat_bytes_num_i[15:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -4582,7 +4599,7 @@ masterfip_rx_stat_bytes_num_i[8:0]
</td>
<td class="td_pblock_right">
masterfip_rx_stat_curr_word_indx_i[6:0]
masterfip_rx_stat_curr_word_indx_i[7:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -12336,6 +12353,9 @@ DBG[7:0]
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
EXT_SYNC_ERR
</td>
......@@ -12343,9 +12363,6 @@ EXT_SYNC_ERR
EXT_SYNC_ACT
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
EXT_SYNC_USED
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
TX_ERR
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
......@@ -12373,9 +12390,6 @@ TX_ACT
TX_ERR
</b>[<i>read/write</i>]: tx err red led
<li><b>
EXT_SYNC_USED
</b>[<i>read/write</i>]: write 1 to indicate that the ext sync is used
<li><b>
EXT_SYNC_ACT
</b>[<i>read/write</i>]: ext sync act green led
<li><b>
......@@ -12384,6 +12398,7 @@ EXT_SYNC_ERR
<li><b>
DBG
</b>[<i>read/write</i>]: dbg
<br>bit 8 is connected to TP3; bit 9 is connected to TP4
</ul>
<a name="DS1820_TEMPER"></a>
<h3><a name="sect_3_4">3.4. fmc temperature</a></h3>
......@@ -13250,8 +13265,8 @@ EXT_SYNC_CTRL
<td class="td_unused">
-
</td>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=1 class="td_field">
SAFE_WIND
</td>
</tr>
</table>
......@@ -13304,8 +13319,8 @@ EXT_SYNC_CTRL
<td class="td_unused">
-
</td>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=1 class="td_field">
OPT
</td>
</tr>
</table>
......@@ -13429,11 +13444,19 @@ DIR
<li><b>
OE_N
</b>[<i>read/write</i>]: transceiver output enable negative logic
<br>write 0: normal operation, the external sync pulse arrives to the FPGA<br> write 1: the external sync pulse does not arrive to the FPGA<br> WARNING: this bit is hard-wired in the HDL top to 0
<br>write 0: normal operation, the external sync pulse arrives to the FPGA and controls the macrocycle counter<br> write 1: the external sync pulse is disabled; the macrocycle counting is based on internal counters
<li><b>
P_CNT_RST
</b>[<i>read/write</i>]: pulses counter reset
<br>resets the pulses counter
<li><b>
OPT
</b>[<i>read/write</i>]: counting options
<br>0: external pulse resets the macrocycle counter whenever it arrives<br> 1: external pulse resets the macrocycle counter, only when it arrives in a window as expected by the<br> processor and the macrocycle configuration. In this option for example if a macrocycle is set at 20 ms<br> but a pulse arrives every 10 ms by mistake, then one every 2 pulses will be ignored.<br> Note that the ext_sync_p_cnt will be counting in any case all the incoming pulses, so the error will<br> be reported, but the macrocycle will run smoothly at 20 ms
<li><b>
SAFE_WIND
</b>[<i>read/write</i>]: safe window
<br>0: processor busy with periodic traffic; reception of a new external pulse is NOT safe<br> 1: processor ready for a new external pulse; macrocycle periodic part has been played
</ul>
<a name="EXT_SYNC_P_CNT"></a>
<h3><a name="sect_3_8">3.8. ext sync pulses cnt</a></h3>
......@@ -13691,7 +13714,7 @@ EXT_SYNC_P_CNT[7:0]
<li><b>
EXT_SYNC_P_CNT
</b>[<i>read-only</i>]: ext_sync_p_cnt
<br>number of ext sync pulses since the application startup OR a rst_core OR a ext_sync_p_cnt_rst;<br> for the fastest macrocycle of 20ms, the counter can keep counting for up to >2.5 years.
<br>number of ext sync pulses since the application startup OR a rst_core OR a ext_sync_p_cnt_rst;<br> for the fastest macrocycle of 20ms, the counter can keep counting for up to 2.7 years.
</ul>
<a name="SPEED"></a>
<h3><a name="sect_3_9">3.9. bus speed</a></h3>
......@@ -14727,7 +14750,7 @@ MACROCYC_NUM_CNT[7:0]
<li><b>
MACROCYC_NUM_CNT
</b>[<i>read-only</i>]: number of macrocycles
<br>amount of macrocycles that have been counted since the application startup OR a rst_core;<br> for the fastest macrocycle of 20ms, the counter can keep counting for up to >2.5 years.
<br>amount of macrocycles that have been counted since the application startup OR a rst_core;<br> for the fastest macrocycle of 20ms, the counter can keep counting for up to 2.7 years.
</ul>
<a name="TURNAR"></a>
<h3><a name="sect_3_13">3.13. turnaround lgth</a></h3>
......@@ -15887,29 +15910,29 @@ TX_CTRL
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
BYTES_NUM[15:8]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
BYTES_NUM[8:8]
<td >
</td>
</tr>
</table>
......@@ -16099,29 +16122,29 @@ TX_STAT
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
CURR_BYTE_INDX[15:8]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -16153,26 +16176,26 @@ TX_STAT
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
CURR_BYTE_INDX[7:0]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td style="border: solid 1px black;" colspan=2 class="td_field">
CURR_BYTE_INDX[8:7]
<td >
</td>
<td >
......@@ -16207,29 +16230,29 @@ CURR_BYTE_INDX[8:7]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=7 class="td_field">
CURR_BYTE_INDX[6:0]
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
ENA
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td style="border: solid 1px black;" colspan=1 class="td_field">
ENA
</td>
</tr>
</table>
......@@ -17716,29 +17739,29 @@ RX_STAT
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
BYTES_NUM[15:8]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
BYTES_NUM[8:8]
<td >
</td>
</tr>
</table>
......@@ -18094,11 +18117,11 @@ RX_STAT_CURR_WORD_INDX
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
RX_STAT_CURR_WORD_INDX[7:0]
</td>
<td style="border: solid 1px black;" colspan=7 class="td_field">
RX_STAT_CURR_WORD_INDX[6:0]
<td >
</td>
<td >
......
python/regs/masterfip_csr.py
View file @ 30c3283c
......@@ -2,7 +2,7 @@
#
# * File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/python/regs/masterfip_csr.py
# * Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/ip_cores/gw-masterfip/rtl/wbgen/masterfip_csr.wb
# * Created : Mon Apr 3 13:15:22 2017
# * Created : Mon Apr 24 10:20:15 2017
#
# THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/ip_cores/gw-masterfip/rtl/wbgen/masterfip_csr.wb
# DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
......@@ -21,9 +21,8 @@ addr = {
'led.rx_err' : [ 0x2, 0x2, "rw"],
'led.tx_act' : [ 0x2, 0x4, "rw"],
'led.tx_err' : [ 0x2, 0x8, "rw"],
'led.ext_sync_used' : [ 0x2, 0x10, "rw"],
'led.ext_sync_act' : [ 0x2, 0x20, "rw"],
'led.ext_sync_err' : [ 0x2, 0x40, "rw"],
'led.ext_sync_act' : [ 0x2, 0x10, "rw"],
'led.ext_sync_err' : [ 0x2, 0x20, "rw"],
'led.dbg' : [ 0x2, 0xFFFFFF00, "rw"],
'ds1820_temper' : [ 0x3, 0xffffffff, "r"],
......@@ -37,6 +36,8 @@ addr = {
'ext_sync_ctrl.dir' : [ 0x6, 0x2, "rw"],
'ext_sync_ctrl.oe_n' : [ 0x6, 0x4, "rw"],
'ext_sync_ctrl.p_cnt_rst' : [ 0x6, 0x100, "rw"],
'ext_sync_ctrl.opt' : [ 0x6, 0x10000, "rw"],
'ext_sync_ctrl.safe_wind' : [ 0x6, 0x1000000, "rw"],
'ext_sync_p_cnt' : [ 0x7, 0xffffffff, "r"],
......@@ -65,12 +66,12 @@ addr = {
'tx_ctrl' : [ 0x10, 0xffffffff, "rw"],
'tx_ctrl.rst' : [ 0x10, 0x1, "rw"],
'tx_ctrl.start' : [ 0x10, 0x2, "rw"],
'tx_ctrl.bytes_num' : [ 0x10, 0x1FF00, "rw"],
'tx_ctrl.bytes_num' : [ 0x10, 0xFFFF00, "rw"],
'tx_stat' : [ 0x11, 0xffffffff, "r"],
'tx_stat.stop' : [ 0x11, 0x1, "r"],
'tx_stat.ena' : [ 0x11, 0x100, "r"],
'tx_stat.curr_byte_indx' : [ 0x11, 0x3FE00, "r"],
'tx_stat.curr_byte_indx' : [ 0x11, 0xFFFF0000, "r"],
'fd' : [ 0x12, 0xffffffff, "r"],
'fd.wdg' : [ 0x12, 0x1, "r"],
......@@ -88,7 +89,7 @@ addr = {
'rx_stat.pream_ok' : [ 0x17, 0x1, "r"],
'rx_stat.frame_ok' : [ 0x17, 0x2, "r"],
'rx_stat.frame_crc_err' : [ 0x17, 0x4, "r"],
'rx_stat.bytes_num' : [ 0x17, 0x1FF00, "r"],
'rx_stat.bytes_num' : [ 0x17, 0xFFFF00, "r"],
'rx_stat_curr_word_indx' : [ 0x18, 0xffffffff, "r"],
......
python/regs/masterfip_pts_csr.py
View file @ 30c3283c
......@@ -2,7 +2,7 @@
#
# * File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/python/regs/masterfip_pts_csr.py
# * Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.wb
# * Created : Mon Apr 3 13:15:24 2017
# * Created : Mon Apr 24 10:20:17 2017
#
# THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.wb
# DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
......
python/test01.py
View file @ 30c3283c
......@@ -118,7 +118,7 @@ def main (card=None, default_directory='.',suite=None, serial=""):
# test_results['All leds'] = test_led_all( dut )
test_results['Running led'] = test_running_led( dut )
dut.fipcore.write_regname( 'led.ext_sync_used', 1 )
dut.fipcore.write_regname( 'ext_sync_ctrl.oe_n', 0 )
for led in ledlist:
# if there was an error in test of all LEDs
......
python/test02.py
View file @ 30c3283c
......@@ -77,7 +77,7 @@ def verify_rx_status( stat ):
def verify_presence( carrier ):
util.info_msg("Bus transmission: checking presence")
util.info_msg("Bus transmission: sending presence variable 0x147F to nanoFIPdiag.")
# Send ID_DAT for presence variable (0x14)
# nanoFIPdiag address (common to all such modules in CERN): 7F
......@@ -101,7 +101,7 @@ def verify_presence( carrier ):
# presence variable data is always the same
if util.bitvector(data, 0, 8*6) == 0x00f00003800550 :
util.info_msg ("Presence variable OK!")
util.info_msg ("Presence variable OK (%x)!" % util.bitvector(data, 0, 8*6) )
test_result['Data field'] = 1
elif (data == 0x0):
......@@ -194,7 +194,7 @@ def test_txerr( dut, box, maxtries = 50 ):
time.sleep(0.5)
########################################################################
util.section_msg("Checking if TX_ERR is not going active during normal transmission")
util.info_msg("\nChecking if TX_ERR is not going active during normal transmission")
dut.rst_core()
util.info_msg("TX_ERR counter before transmission: %d" % dut.fippts.read_regname('fd_txerr_cnt') )
......@@ -222,7 +222,7 @@ def test_txerr( dut, box, maxtries = 50 ):
util.section_msg("Checking if TX_ERR IS going active during corrupted transmission (serial output is constant 1)")
dut.rst_core()
util.info_msg("TX_ERR counter before transmission: %d" % dut.fippts.read_regname('fd_txerr_cnt') )
util.info_msg("\nTX_ERR counter before transmission: %d" % dut.fippts.read_regname('fd_txerr_cnt') )
# corrupting serial output!!!!!
dut.fippts.write_regname('tx_corrupt',1)
......@@ -277,7 +277,7 @@ def test_wdgn( dut ):
###################### test ##################################################
########################################################################
util.section_msg("Checking if WDG_N becomes active during normal transmission")
util.info_msg("\nChecking if WDG_N becomes active during normal transmission")
dut.rst_core()
dut.fipcore.write_regname('tx_ctrl', 1)
......@@ -296,7 +296,7 @@ def test_wdgn( dut ):
result['WDG_N during correct transmission'] = tmp
###################### test ##################################################
util.section_msg("Checking if WDG_N becomes active during very long transmission")
util.info_msg("\nChecking if WDG_N becomes active during very long transmission")
dut.rst_core()
dut.fipcore.write_regname('tx_ctrl', 1)
......@@ -329,7 +329,7 @@ def test_wdgn( dut ):
util.info_msg( "WDG_N was active after corrupted transmission finished" )
result['WDG_N latch in FieldDrive'] = 1
util.section_msg("Checking FieldDrive RST_N line")
util.info_msg("\nTesting FieldDrive RST_N line")
util.info_msg("Reseting FieldDrive chip")
dut.rst_fd()
......
python/test04.py
View file @ 30c3283c
......@@ -69,17 +69,17 @@ def main (card=None, default_directory='.',suite=None, serial=""):
temperature = dut.get_temp()
if (temperature >= util.mintemp) and (temperature <= util.maxtemp):
util.info_msg("Read correct board temperature: %d" % temperature)
util.info_msg("Read correct board temperature: %d oC" % temperature)
test_results['Temperature value'] = 1
break
else:
test_results['Temperature value'] = 0
if temperature > util.maxtemp:
util.err_msg( "Temperature exceeds %d C" % util.maxtemp )
util.err_msg( "Temperature exceeds %d oC" % util.maxtemp )
else :
util.err_msg( "Temperature is lower then %d C" % util.mintemp )
util.err_msg( "Temperature is lower then %d oC" % util.mintemp )
###############################################################################
......
python/test05.py
View file @ 30c3283c
......@@ -126,16 +126,26 @@ def main (card=None, default_directory='.',suite=None, serial=None):
# create FRU information
util.section_msg("Creating IPMI-FRU information")
ipmi_vendor = "CERN"
ipmi_name = "fmc-masterfip"
ipmi_part = "EDA-03098-V3-%d" % speed
util.info_msg("Vendor: %s" % ipmi_vendor )
util.info_msg("Name: %s" % ipmi_name )
util.info_msg("Part: %s" % ipmi_part )
util.info_msg("Serial: %s" % serial )
subprocess.call(
[fru_gen_path,
# vendor
"-v", "CERN",
"-v %s" % ipmi_vendor,
# name
"-n", "fmc-masterfip",
"-n %s" % ipmi_name,
# serial
"-s", serial,
# part
"-p", "EDA-03098-V3-%d" % speed,
"-p %s" % ipmi_part,
# output
"-o", sdbfs_path+"/IPMI-FRU" ]
)
......@@ -155,7 +165,7 @@ def main (card=None, default_directory='.',suite=None, serial=None):
# write generated file to EEPROM
util.info_msg("Writing EEPROM")
util.section_msg("Writing EEPROM")
cnt = 0
with open(output_file, "rb") as f:
byte = f.read(1)
......
python/test06.py
View file @ 30c3283c
......@@ -126,7 +126,7 @@ def test_oen( dut, box ):
result = {}
util.section_msg("Testing output enable")
util.section_msg("Testing buffer output enable")
###############################################################################
......@@ -187,8 +187,9 @@ def test_dir( dut, box ):
result = {}
util.section_msg("Testing direction selection")
util.section_msg("Hack: Synchronisation input test will be repeated, with external buffer set to output")
util.section_msg("Hack: Value read on FPGA input shouldn't change, although synchronisation input changes")
util.info_msg("Hack: Synchronisation input test will be repeated, with external buffer set to output")
util.info_msg("Hack: Value read on FPGA input shouldn't change, although synchronisation input changes")
util.section_msg("Testing direction selection")
###############################################################################
......
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