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MasterFIP - Testing
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MasterFIP - Testing
Commits
23fb3e82
Commit
23fb3e82
authored
Apr 03, 2017
by
Marek Gumiński
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Renamed top module
parent
fe9ccb82
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4 changed files
with
5 additions
and
9 deletions
+5
-9
spec_masterfip_mt.bin
gateware/syn/spec/spec_masterfip_mt.bin
+0
-0
spec_masterfip_mt.xise
gateware/syn/spec/spec_masterfip_mt.xise
+5
-9
spec_masterfip_pts.bin
gateware/syn/spec/spec_masterfip_pts.bin
+0
-0
spec_masterfip_pts.ucf
gateware/top/spec/spec_masterfip_pts.ucf
+0
-0
No files found.
gateware/syn/spec/spec_masterfip_mt.bin
deleted
100644 → 0
View file @
fe9ccb82
File deleted
gateware/syn/spec/spec_masterfip_mt.xise
View file @
23fb3e82
...
...
@@ -90,7 +90,7 @@
<property
xil_pn:name=
"Enable Message Filtering"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Enable Multi-Pin Wake-Up Suspend Mode spartan6"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Enable Multi-Threading"
xil_pn:value=
"2"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Enable Multi-Threading par spartan6"
xil_pn:value=
"
3"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"Enable Multi-Threading par spartan6"
xil_pn:value=
"
Off"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"Enable Outputs (Output Events)"
xil_pn:value=
"Default (5)"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Enable Suspend/Wake Global Set/Reset spartan6"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Encrypt Bitstream spartan6"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
...
...
@@ -994,9 +994,6 @@
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"54"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"54"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/gw-masterfip/top/spec/spec_masterfip_mt.ucf"
xil_pn:type=
"FILE_UCF"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/gw-masterfip/top/spec/spec_masterfip_mt.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"208"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0"
/>
...
...
@@ -1763,9 +1760,6 @@
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"433"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"180"
/>
</file>
<file
xil_pn:name=
"../../top/spec/spec_top_fmc_masterfip.ucf"
xil_pn:type=
"FILE_UCF"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0"
/>
</file>
<file
xil_pn:name=
"../../rtl/masterfip_pts.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"474"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"176"
/>
...
...
@@ -1774,6 +1768,9 @@
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"475"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"158"
/>
</file>
<file
xil_pn:name=
"../../top/spec/spec_masterfip_pts.ucf"
xil_pn:type=
"FILE_UCF"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"525"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/gn4124-core/hdl/spec/ip_cores/fifo_32x512.xise"
xil_pn:type=
"FILE_COREGENISE"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0"
/>
</file>
...
...
@@ -1783,8 +1780,7 @@
</files>
<bindings>
<binding
xil_pn:location=
"/spec_masterfip_mt"
xil_pn:name=
"../../ip_cores/gw-masterfip/top/spec/spec_masterfip_mt.ucf"
/>
<binding
xil_pn:location=
"/spec_masterfip_pts2"
xil_pn:name=
"../../top/spec/spec_top_fmc_masterfip.ucf"
/>
<binding
xil_pn:location=
"/spec_masterfip_pts"
xil_pn:name=
"../../top/spec/spec_masterfip_pts.ucf"
/>
</bindings>
<version
xil_pn:ise_version=
"14.7"
xil_pn:schema_version=
"2"
/>
...
...
gateware/syn/spec/spec_masterfip_pts.bin
View file @
23fb3e82
No preview for this file type
gateware/top/spec/spec_masterfip_pts.u
s
f
→
gateware/top/spec/spec_masterfip_pts.u
c
f
View file @
23fb3e82
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