Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
M
MasterFIP - Testing
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
MasterFIP - Testing
Commits
1fa47406
Commit
1fa47406
authored
Jun 02, 2017
by
Marek Gumiński
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Increased timeout for worldfip
parent
e7e2e657
Expand all
Hide whitespace changes
Inline
Side-by-side
Showing
3 changed files
with
444 additions
and
15 deletions
+444
-15
wf_package.vhd
gateware/rtl/wf_package.vhd
+429
-0
spec_masterfip_pts.bin
gateware/syn/spec/spec_masterfip_pts.bin
+0
-0
spec_masterfip_pts.xise
gateware/syn/spec/spec_masterfip_pts.xise
+15
-15
No files found.
gateware/rtl/wf_package.vhd
0 → 100644
View file @
1fa47406
This diff is collapsed.
Click to expand it.
gateware/syn/spec/spec_masterfip_pts.bin
View file @
1fa47406
No preview for this file type
gateware/syn/spec/spec_masterfip_pts.xise
View file @
1fa47406
...
...
@@ -388,7 +388,7 @@
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/rtl/wrnc/mqueue/wrn_mqueue_wishbone_slave.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"93"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9
2
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9
3
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"0"
/>
...
...
@@ -434,10 +434,6 @@
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"147"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"141"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/gw-masterfip/rtl/wf_package.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"92"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"103"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"0"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0"
/>
...
...
@@ -464,7 +460,7 @@
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/rtl/wrnc/mqueue/wrn_mqueue_etherbone_output.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"95"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9
4
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9
5
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"132"
/>
...
...
@@ -648,7 +644,7 @@
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/rtl/wrnc/mqueue/wrn_mqueue_slot.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"94"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9
3
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9
4
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/rtl/wrnc/smem/wrn_shared_mem.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"112"
/>
...
...
@@ -852,7 +848,7 @@
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/rtl/wrnc/cpu/wrn_cpu_lr_wb.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"97"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9
6
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9
7
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"56"
/>
...
...
@@ -896,7 +892,7 @@
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/rtl/wrnc/cpu/wrn_lm32_wrapper.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"96"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9
5
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9
6
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_reset.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"0"
/>
...
...
@@ -1323,7 +1319,7 @@
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"103"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"10
2
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"10
3
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"77"
/>
...
...
@@ -1573,7 +1569,7 @@
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_endpoint/wr_endpoint.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"101"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"10
0
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"10
1
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"120"
/>
...
...
@@ -1593,7 +1589,7 @@
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"100"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
99
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
100
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"119"
/>
...
...
@@ -1605,7 +1601,7 @@
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"99"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9
8
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9
9
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"118"
/>
...
...
@@ -1645,7 +1641,7 @@
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_softpll_ng/wr_softpll_ng.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"98"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9
7
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9
8
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wr_softpll_ng/xwr_softpll_ng.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"117"
/>
...
...
@@ -1693,7 +1689,7 @@
</file>
<file
xil_pn:name=
"../../ip_cores/wr-cores/modules/wrc_core/xwr_syscon_wb.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"102"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"10
1
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"10
2
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_dyn_extend_pulse.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"189"
/>
...
...
@@ -1767,6 +1763,10 @@
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"435"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"137"
/>
</file>
<file
xil_pn:name=
"../../rtl/wf_package.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"394"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"92"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/gn4124-core/hdl/spec/ip_cores/fifo_32x512.xise"
xil_pn:type=
"FILE_COREGENISE"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0"
/>
</file>
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment