Commit 143fcf35 authored by Marek Gumiński's avatar Marek Gumiński

Fixed tests 0 1 5

Verified communication on bus (first sutest of test02)
parent cbc84788
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
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-- File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/fmc_masterfip_csr_pts.vhd -- File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/fmc_masterfip_csr_pts.vhd
-- Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/fmc_masterfip_csr.wb -- Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/fmc_masterfip_csr.wb
-- Created : Wed Mar 15 14:47:49 2017 -- Created : Wed Mar 29 15:35:06 2017
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/fmc_masterfip_csr.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/fmc_masterfip_csr.wb
......
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_csr.vhd -- File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_csr.vhd
-- Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/ip_cores/gw-masterfip/rtl/wbgen/masterfip_csr.wb -- Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/ip_cores/gw-masterfip/rtl/wbgen/masterfip_csr.wb
-- Created : Wed Mar 15 14:47:52 2017 -- Created : Wed Mar 29 15:35:08 2017
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/ip_cores/gw-masterfip/rtl/wbgen/masterfip_csr.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/ip_cores/gw-masterfip/rtl/wbgen/masterfip_csr.wb
......
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.vhd -- File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.vhd
-- Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.wb -- Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.wb
-- Created : Mon Mar 20 16:55:05 2017 -- Created : Wed Mar 29 15:35:11 2017
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.wb
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This diff is collapsed.
...@@ -190,10 +190,10 @@ NET "fmc_onewire_b" LOC = "C18"; ...@@ -190,10 +190,10 @@ NET "fmc_onewire_b" LOC = "C18";
NET "fmc_onewire_b" IOSTANDARD = "LVCMOS25"; NET "fmc_onewire_b" IOSTANDARD = "LVCMOS25";
# NET "fmc_scl_io" LOC = F7; NET "fmc_scl_io" LOC = F7;
# NET "fmc_sda_io" LOC = F8; NET "fmc_sda_io" LOC = F8;
# NET "fmc_scl_io" IOSTANDARD = LVCMOS25; NET "fmc_scl_io" IOSTANDARD = LVCMOS25;
# NET "fmc_sda_io" IOSTANDARD = LVCMOS25; NET "fmc_sda_io" IOSTANDARD = LVCMOS25;
NET "fd_rstn_o" LOC = "Y18"; NET "fd_rstn_o" LOC = "Y18";
NET "fd_rstn_o" IOSTANDARD = "LVCMOS25"; NET "fd_rstn_o" IOSTANDARD = "LVCMOS25";
......
This diff is collapsed.
...@@ -39,7 +39,7 @@ import i2c ...@@ -39,7 +39,7 @@ import i2c
# addressing # addressing
import masterfip_addrtable; import masterfip_csr;
import carrier_addrtable; import carrier_addrtable;
...@@ -72,14 +72,14 @@ class fmcmasterfip: ...@@ -72,14 +72,14 @@ class fmcmasterfip:
# Masterfip core registers # Masterfip core registers
MASTERFIP_CORE_ADDR = 0x00010000 MASTERFIP_CORE_ADDR = 0x00010000
# Masterfip PTS core registers # # Masterfip PTS core registers
MASTERFIP_CORE_PTS = 0x00011000 # MASTERFIP_CORE_PTS = 0x00011000
# Carrier CSR address # Carrier CSR address
CARRIER_CSR_ADDR = 0x00012000 CARRIER_CSR_ADDR = 0x00011000
# MasterFIP FMC eeprom # MasterFIP FMC eeprom
MASTERFIP_I2C_EEPROM = 0x00013000 MASTERFIP_I2C_EEPROM = 0x00012000
freq_options = [ 31250, 1e6, 25e5, 5e6 ] freq_options = [ 31250, 1e6, 25e5, 5e6 ]
...@@ -110,7 +110,7 @@ class fmcmasterfip: ...@@ -110,7 +110,7 @@ class fmcmasterfip:
self.fmc_eeprom_24aa64 = eeprom_24aa64.C24AA64(self.fmc_sys_i2c, self.EEPROM_ADDR) self.fmc_eeprom_24aa64 = eeprom_24aa64.C24AA64(self.fmc_sys_i2c, self.EEPROM_ADDR)
# creation of interfaces to modules controlling main functionality # creation of interfaces to modules controlling main functionality
self.fipcore = wbslave.wbslave(carrier, self.MASTERFIP_CORE_ADDR, masterfip_addrtable.addr) self.fipcore = wbslave.wbslave(carrier, self.MASTERFIP_CORE_ADDR, masterfip_csr.addr)
self.carrier_csr = wbslave.wbslave(carrier, self.CARRIER_CSR_ADDR, carrier_addrtable.addr) self.carrier_csr = wbslave.wbslave(carrier, self.CARRIER_CSR_ADDR, carrier_addrtable.addr)
################################################################### ###################################################################
......
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
# #
# * File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/python/regs/carrier_addrtable.py # * File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/python/regs/carrier_addrtable.py
# * Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/carrier_csr.wb # * Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/carrier_csr.wb
# * Created : Wed Mar 15 14:47:52 2017 # * Created : Wed Mar 29 15:35:08 2017
# #
# THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/carrier_csr.wb # THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/carrier_csr.wb
# DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY! # DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
......
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
# #
# * File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/python/regs/masterfip_addrtable.py # * File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/python/regs/masterfip_addrtable.py
# * Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/fmc_masterfip_csr.wb # * Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/fmc_masterfip_csr.wb
# * Created : Wed Mar 15 14:47:50 2017 # * Created : Wed Mar 29 15:35:06 2017
# #
# THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/fmc_masterfip_csr.wb # THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/fmc_masterfip_csr.wb
# DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY! # DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
......
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
# #
# * File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/python/regs/masterfip_csr.py # * File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/python/regs/masterfip_csr.py
# * Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/ip_cores/gw-masterfip/rtl/wbgen/masterfip_csr.wb # * Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/ip_cores/gw-masterfip/rtl/wbgen/masterfip_csr.wb
# * Created : Wed Mar 15 14:47:52 2017 # * Created : Wed Mar 29 15:35:09 2017
# #
# THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/ip_cores/gw-masterfip/rtl/wbgen/masterfip_csr.wb # THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/ip_cores/gw-masterfip/rtl/wbgen/masterfip_csr.wb
# DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY! # DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
......
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
# #
# * File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/python/regs/masterfip_pts_csr.py # * File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/python/regs/masterfip_pts_csr.py
# * Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.wb # * Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.wb
# * Created : Mon Mar 20 16:55:05 2017 # * Created : Wed Mar 29 15:35:11 2017
# #
# THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.wb # THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.wb
# DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY! # DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
......
...@@ -13,7 +13,8 @@ import ptsexcept ...@@ -13,7 +13,8 @@ import ptsexcept
import time import time
ledlist = ['out_of_sync', 'rx_err', 'rx_act', 'sync', 'tx_act', 'tx_err' ] # ledlist = ['out_of_sync', 'rx_err', 'rx_act', 'sync', 'tx_act', 'tx_err' ]
ledlist = [ 'rx_act', 'rx_err', 'tx_act', 'tx_err', 'ext_sync_act', 'ext_sync_err' ]
def test_led_all( board ): def test_led_all( board ):
...@@ -69,26 +70,20 @@ def test_running_led( dut ): ...@@ -69,26 +70,20 @@ def test_running_led( dut ):
util.user_msg("Please observe the FMC masterFIP front panel") util.user_msg("Please observe the FMC masterFIP front panel")
util.user_msg("Please make sure that no more than one LED is enabled at a time") util.user_msg("Please make sure that no more than one LED is enabled at a time")
util.ask_user("Are you ready to start a test?" ) util.ask_user("Are you ready to start a test?" )
for j in xrange(2): dut.fipcore.write_regname( 'led.ext_sync_used', 1 )
dut.fipcore.write_regname( 'led', 1 << 1 ) time.sleep(0.7)
time.sleep(0.7)
dut.fipcore.write_regname( 'led', 1 << 2 ) for led in ledlist:
time.sleep(0.7) regname = ( 'led.%s' % led )
dut.fipcore.write_regname( 'led', 1 << 4 ) dut.fipcore.write_regname( regname, 1 )
time.sleep(0.7)
dut.fipcore.write_regname( 'led', 1 << 5 )
time.sleep(0.7)
dut.fipcore.write_regname( 'led', 1 << 0 )
time.sleep(0.7)
dut.fipcore.write_regname( 'led', 1 << 3 )
time.sleep(0.7) time.sleep(0.7)
dut.fipcore.write_regname( regname, 0 )
#for i in xrange(6):
# dut.fipcore.write_regname( 'led', 1 << i )
# time.sleep(0.7)
dut.fipcore.write_regname( 'led', 0 ) dut.fipcore.write_regname( 'led', 0 )
time.sleep(0.7)
dut.fipcore.write_regname( 'led.ext_sync_used', 1 )
time.sleep(0.7)
if not util.ask_user("Was there no more than one led enabled at a time?"): if not util.ask_user("Was there no more than one led enabled at a time?"):
util.err_msg("LED's verification failed!") util.err_msg("LED's verification failed!")
...@@ -126,6 +121,8 @@ def main (card=None, default_directory='.',suite=None, serial=""): ...@@ -126,6 +121,8 @@ def main (card=None, default_directory='.',suite=None, serial=""):
# negative return value means error # negative return value means error
# test_results['All leds'] = test_led_all( dut ) # test_results['All leds'] = test_led_all( dut )
test_results['Running led'] = test_running_led( dut ) test_results['Running led'] = test_running_led( dut )
dut.fipcore.write_regname( 'led.ext_sync_used', 1 )
for led in ledlist: for led in ledlist:
# if there was an error in test of all LEDs # if there was an error in test of all LEDs
......
...@@ -56,16 +56,11 @@ def verify_rx_status( stat ): ...@@ -56,16 +56,11 @@ def verify_rx_status( stat ):
else: else:
test_result['Number of bytes'] = 1 test_result['Number of bytes'] = 1
if ( util.bitvector(stat, 3, 5) == 0x1 ) and ( util.bitvector(stat, 2, 2) == 1 ): if ( util.bitvector(stat, 2, 2) == 1 ):
util.info_msg("CRC error") util.info_msg("CRC error")
else : else :
test_result['CRC'] = 1 test_result['CRC'] = 1
if ( util.bitvector(stat, 3, 5) == 0x2 ) and ( util.bitvector(stat, 2, 2) == 1 ):
util.info_msg("Unexpected frame size")
else :
test_result['Frame size'] = 1
if util.bitvector(stat, 1, 1) == 0 : if util.bitvector(stat, 1, 1) == 0 :
util.info_msg("Not complete frame received") util.info_msg("Not complete frame received")
else : else :
......
...@@ -13,7 +13,7 @@ INFO = True ...@@ -13,7 +13,7 @@ INFO = True
WARRNING = True WARRNING = True
CRITICAL = True CRITICAL = True
FIRMWARE_PATH ='gateware/syn/spec/spec_masterfip_pts.bin' FIRMWARE_PATH ='gateware/syn/spec/spec_masterfip_pts2.bin'
TOPDIRNAME ="fmcmasterfip" TOPDIRNAME ="fmcmasterfip"
test03_outputpath ='/tmp/' test03_outputpath ='/tmp/'
......
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