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MasterFIP - Testing
Commit 0e2e9c99 authored by Marek Gumiński's avatar Marek Gumiński
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Changed python tests to match new FMC_worldFIP v3

parent 790f6bf9
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python/fmcmasterfip.py
View file @ 0e2e9c99
......@@ -422,6 +422,7 @@ class fmcmasterfip:
util.info_msg("Speed : 0x%08X"%(self.fipcore.read_regname('speed')) )
def get_bus_freq(self):
print self.fipcore.read_regname('speed')
return self.freq_options[ self.fipcore.read_regname('speed') ]
......
python/regs/carrier_addrtable.py
View file @ 0e2e9c99
# Register definitions for slave core: Carrier control and status registers
#
# * File : /home/gumas/projects/cti/fmcmasterfip/python/regs/carrier_addrtable.py
# * Author : auto-generated by wbgen2 from /home/gumas/projects/cti/fmcmasterfip/gateware/rtl/wbgen/carrier_csr.wb
# * Created : Tue Jun 7 16:15:19 2016
# * File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/python/regs/carrier_addrtable.py
# * Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/carrier_csr.wb
# * Created : Tue Mar 7 12:59:04 2017
#
# THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/fmcmasterfip/gateware/rtl/wbgen/carrier_csr.wb
# THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/carrier_csr.wb
# DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
#
......
python/regs/masterfip_addrtable.htm
View file @ 0e2e9c99
......@@ -3468,6 +3468,23 @@ mf_ext_sync_p_cnt_rst_o
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
mf_ext_sync_fpga_io_dir_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
......@@ -12981,8 +12998,8 @@ EXT_SYNC
<td class="td_unused">
-
</td>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=1 class="td_field">
FPGA_IO_DIR
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
P_CNT_RST
......@@ -13068,6 +13085,10 @@ OUTPUT_VALUE
P_CNT_RST
</b>[<i>read/write</i>]: pulses counter reset
<br>resets the pulses counter
<li><b>
FPGA_IO_DIR
</b>[<i>read/write</i>]: FPGA IO direction
<br>Direction of FPGA IO
</ul>
<a name="EXT_SYNC_RAW_INPUT"></a>
<h3><a name="sect_3_7">3.7. ext sync raw input</a></h3>
......
python/regs/masterfip_addrtable.py
View file @ 0e2e9c99
# Register definitions for slave core: FMC masterFIP core registers
#
# * File : /home/gumas/projects/cti/fmcmasterfip/python/regs/masterfip_addrtable.py
# * Author : auto-generated by wbgen2 from /home/gumas/projects/cti/fmcmasterfip/gateware/rtl/wbgen/fmc_masterfip_csr.wb
# * Created : Tue Jun 7 16:15:16 2016
# * File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/python/regs/masterfip_addrtable.py
# * Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/fmc_masterfip_csr.wb
# * Created : Tue Mar 7 12:59:02 2017
#
# THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/fmcmasterfip/gateware/rtl/wbgen/fmc_masterfip_csr.wb
# THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/fmc_masterfip_csr.wb
# DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
#
......@@ -41,6 +41,7 @@ addr = {
'ext_sync.tst' : [ 0x5, 0x8, "rw"],
'ext_sync.output_value' : [ 0x5, 0x10, "rw"],
'ext_sync.p_cnt_rst' : [ 0x5, 0x100, "rw"],
'ext_sync.fpga_io_dir' : [ 0x5, 0x200, "rw"],
'ext_sync_raw_input' : [ 0x6, 0xffffffff, "r"],
......
python/test.c 0 → 100644
View file @ 0e2e9c99
void main(){
printf( "Hello word");
printf( "sdf asdkfds ")
}
python/test03.py deleted 100644 → 0
View file @ 790f6bf9
#! /usr/bin/env python
# Copyright Creotech SA, 2016
# Author: Marek Guminski <marek.guminski@creotech.pl>
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org
import spec
import fmcmasterfip
import utilities as util
import time
import decode_masterfip as decmf
import ptsexcept
import numpy
import string
import matplotlib.pyplot as plt
PLOT=True
def get_message_edges( data, samplesperbit, threshold ):
edges=[]
idle = True
cnt = 0
for i in xrange(len(data)):
if data[i] > threshold :
cnt = 2*samplesperbit
if idle:
idle = False
edges.append(i)
elif cnt > 0:
cnt -= 1
elif not idle:
idle = True
edges.append(i)
return edges
def adc_spi_communication( dut ):
# software reset should be given first
# its self cleaning, so there is no point in reading this register back
dut.write_adc_reg_spi(0,0x80)
time.sleep(0.1)
# register 0x4 is used to set test pattern
# so anything may be written and read without make any harm
# read default register content
reg_default = dut.read_adc_reg_spi(0x4) & 0xff
# write some data
dut.write_adc_reg_spi(0x4,0xaa)
reg_aa = dut.read_adc_reg_spi(0x4) & 0xff
# set other bits
dut.write_adc_reg_spi(0x4,0x55)
reg_55 = dut.read_adc_reg_spi(0x4) & 0xff
return [reg_default, reg_aa, reg_55 ]
def test_adc_spi( dut ):
# disable ADC power and try to talk to it
# should fail
dut.adc_power(0)
[off_reg_default, off_reg_aa, off_reg_55 ] = adc_spi_communication(dut)
# power up device
dut.adc_power(1)
# wait a little
time.sleep(0.5)
# power up device
dut.adc_power(1)
# wait a little
time.sleep(0.5)
# repeat SPI test
# this time it should succeed
[on_reg_default, on_reg_aa, on_reg_55 ] = adc_spi_communication(dut)
# process test results
result ={}
# default values are not specified
# so I'm just saving them in log
util.info_msg("Value read from ADC register 0x4 during power down: %x" % off_reg_default )
util.info_msg("Value read from ADC register 0x4 during after power up: %x" % on_reg_default )
# log other read values
util.info_err_msg("Value read from ADC register 0x4 during power down, after writing 0xaa: %x" % off_reg_aa, off_reg_aa == 0xaa )
util.info_err_msg("Value read from ADC register 0x4 during power down, after writing 0x55: %x" % off_reg_55 , off_reg_55 == 0x55 )
util.info_err_msg("Value read from ADC register 0x4 during power up, after writing 0xaa: %x" % on_reg_aa, on_reg_aa != 0xaa )
util.info_err_msg("Value read from ADC register 0x4 during power up, after writing 0x55: %x" % on_reg_55, on_reg_55 != 0x55 )
# verify test results
result['Writing value 0xAA to disabled ADC over SPI'] = 1 if off_reg_aa != 0xaa else 0;
result['Writing value 0x55 to disabled ADC over SPI'] = 1 if off_reg_55 != 0x55 else 0;
result['Writing value 0xAA to enabled ADC over SPI'] = 1 if on_reg_aa == 0xaa else 0;
result['Writing value 0x55 to enabled ADC over SPI'] = 1 if on_reg_55 == 0x55 else 0;
return result
def verify_rx_status( stat ):
# assume test failure
test_result = {
'Number of bytes' : 0,
'CRC' : 0,
'Frame size' : 0,
'Frame format' : 0,
'Preamble' : 0
}
if util.bitvector(stat, 8, 16) != 10:
util.info_msg("Wrong number of bytes received")
else:
test_result['Number of bytes'] = 1
if ( util.bitvector(stat, 3, 5) == 0x1 ) and ( util.bitvector(stat, 2, 2) == 1 ):
util.info_msg("CRC error")
else :
test_result['CRC'] = 1
if ( util.bitvector(stat, 3, 5) == 0x2 ) and ( util.bitvector(stat, 2, 2) == 1 ):
util.info_msg("Unexpected frame size")
else :
test_result['Frame size'] = 1
if util.bitvector(stat, 1, 1) == 0 :
util.info_msg("Not complete frame received")
else :
test_result['Frame format'] = 1
if util.bitvector(stat, 0, 0) == 0 :
util.info_msg("Preamble not detected")
else :
test_result['Preamble'] = 1
return test_result
def verify_presence( carrier ):
util.info_msg("Bus transmission: checking presence")
# Send ID_DAT for presence variable (0x14)
# nanoFIPdiag address (common to all such modules in CERN): 7F
carrier.send_id_dat(0x7F14)
# wait for response
time.sleep(1)
# Read RP_DAT reply from nanoFIPdiag
[stat, ctrl, data ] = carrier.read_rp_dat()
test_result = verify_rx_status( stat )
util.info_msg("Control field in bus response: 0x%x" % ctrl)
# replay should have ctrl value equal to 2
if ctrl == 2:
test_result['Data control field'] = 1
else :
test_result['Data control field'] = 0
# presence variable data is always the same
if util.bitvector(data, 0, 8*6) == 0x00f00003800550 :
util.info_msg ("Presence variable OK!")
test_result['Data field'] = 1
elif (data == 0x0):
util.info_msg("No WorldFIP traffic")
test_result['Data field'] = 0
else:
util.info_msg("Data errors")
test_result['Data field'] = 0
util.info_msg ("")
return test_result
def wait_acquisition( proc, shouldsucced=True, maxdel = 20 ):
retval = True
for i in xrange(maxdel):
# wait a while
time.sleep(0.01)
# check if process terminated
if proc.poll() != None :
util.info_err_msg("Acquisition finished after %d ms" % ((i+1)*10), not shouldsucced )
break
# if acquisition didn't start
# after maxdel tries something is wrong
# kill process and report error
if i == maxdel-1:
util.info_err_msg("Acquisition did NOT finish during %d ms" % ( maxdel *10 ), shouldsucced )
util.info_msg("Killing the process")
retval = False
proc.kill()
break
# communicate with terminated process
# in order to catch it's output
[serr, sout] = proc.communicate()
serr = string.replace(serr, "\n", "\n\t")
sout = string.replace(sout, "\n", "\n\t")
# report output
util.info_msg("Acquisition process returned:")
util.info_msg("\t%s" % serr)
util.info_msg("\t%s" % sout)
return retval
def init(topdir = util.TOPDIRNAME, firmpath = util.FIRMWARE_PATH):
abspath = util.find_prj_topdir(topdir);
carrier = spec.spec( abspath );
# FPGA bitstream and FMC presence are verified during initialization
dut = fmcmasterfip.fmcmasterfip(carrier, abspath, firmpath)
return [carrier, dut, abspath ]
def test_transmission( dut, transmission, should_succed = True, primary = True ):
result={}
samplesperbit = 20
customconf = dut.customize_adc_settings(9+13, samplesperbit)
# set up ADC acquisition
proc = dut.setup_acquisition( customconf );
# send presence variable request
# echo box should replay
if transmission:
result = util.merge_dictionaries( result, verify_presence( dut ) )
# wait for acquisition
# it acquisition doesn't start in some time
# waiting will be terminated
wait_acquisition( proc, should_succed )
dut.save_sampling_freq( numpy.int32( dut.adc_sampling_freq / customconf.undersampling ) )
# read file with ADC samples
# make lists of positive, negative and differential transmission samples
[diff, pos, neg, time ] = dut.read_adc_samples( )
if isinstance(diff, int):
result['Captured ADC transmission' ] = 0
result['Number of frames captured by ADC' ] = 0
result['Request message captured by ADC' ] = 0
result['Response message captured by ADC' ] = 0
else:
result[ 'Captured ADC transmission' ] = 1
# ADC sampling freq is constant, but undersampling is changed depending on bus speed
# result sampling frequency is lower
# 1e6 to get [us]
sampleperiod = 1e6/ (dut.adc_sampling_freq / customconf.undersampling)
# make plot
plt.plot( time, 1000.0*diff/ 2.0**16)
#make is look good
plt.title("Differential WordFIP signal (ADC CH1-CH2)")
plt.ylabel("Signal [mV]")
plt.xlabel("Time [us]")
# plt.show()
plt.savefig("/tmp/image.png")
plt.close()
###############################################
util.section_msg("Decoding acquired data")
util.info_msg("___________Please node that if an error occur in this section raw data should be examined.")
util.info_msg("___________Error might be caused by data processing errors!")
# make sure that both channels exceed threshold
result['Captured data exceed threshold on positive channel'] = 1 if max(pos) > customconf.trigger_threshold else 0
result['Captured data exceed threshold on negative channel'] = 1 if max(neg) > customconf.trigger_threshold else 0
# would be good to analyze request and response separately
# in order do do that i'm looking for samples exceeding trigger threshold
edges = get_message_edges(pos, samplesperbit, customconf.trigger_threshold)
# algorithm might not be very robust
if len(edges) != 4:
util.err_msg("Could not distinct start and of messages based on samples.")
else:
# if it succeeded i should get 4 samples marking start and end of transmission
# pairs of these samples create message boundaries
txpos = pos[edges[0]:edges[1]]
rxpos = pos[edges[2]:edges[3]]
txneg = neg[edges[0]:edges[1]]
rxneg = neg[edges[2]:edges[3]]
# request frame acquired on primary transformer side has some positive offset
# detecting this offset should enable to determine whether primary or secondary side was sampled
# since offset is not well defined it is important to make sure that mean values will be logged
util.info_msg("\nMean values of acquired frames:")
util.info_msg("\tRequest frame - Positive Channel: %d" % numpy.mean(txpos) )
util.info_msg("\tRequest frame - Positive Channel: %d" % numpy.mean(txneg) )
util.info_msg("\tResponse frame - Positive Channel: %d" % numpy.mean(rxpos))
util.info_msg("\tResponse frame - Positive Channel: %d" % numpy.mean(rxneg))
util.info_msg("")
# checking if mean value of a message exceed threshold
# it should be true only for request message sampled on primary side
# all other messages should have mean value close to 0
TX_MEAN_THD= 5e3
if primary:
result['ADC relays identification based on request message'] = 1 if ( numpy.mean(txpos) > TX_MEAN_THD ) and ( numpy.mean(txneg) > TX_MEAN_THD ) else 0
else:
result['ADC relays identification based on request message'] = 1 if ( numpy.mean(txpos) < TX_MEAN_THD ) and ( numpy.mean(txneg) < TX_MEAN_THD ) else 0
result['ADC relays identification based on response message'] = 1 if ( numpy.mean(rxpos) < TX_MEAN_THD ) and ( numpy.mean(rxneg) < TX_MEAN_THD ) else 0
try:
decoded = decmf.decode(diff, 5e3, samplesperbit )
#################################
util.section_msg("Verifying decoded data content")
# verify number of captured frames
if len(decoded) == 2:
result['Number of frames captured by ADC' ] = 1
util.info_msg("Captured two frames with ADC")
else:
util.err_msg("Data captured by ADC doesn't contain two frames")
result['Number of frames captured by ADC' ] = 0
if decoded[0][0:3] == [ 0x3, 0x14, 0x7f]:
result['Request message captured by ADC' ] = 1
util.info_msg("Found request message")
else:
tmp = ""
for b in decoded[0][0:3]:
tmp += " %x" % b
util.err_msg("Unsuspected request frame found: %s" % tmp)
result['Request message captured by ADC' ] = 0
if decoded[1][0:8] == [ 0x02, 0x50, 0x05, 0x80, 0x03, 0x00, 0xF0, 0x00 ]:
result['Response message captured by ADC' ] = 1
util.info_msg("Found response message")
else:
tmp = ""
for b in decoded[1][0:8]:
tmp += " %x" % b
util.err_msg("Unsuspected response frame found: %s"% tmp)
result['Response message captured by ADC' ] = 0
util.info_msg("Decoding messages captured by ADC finished successful")
result['Decoding of messages captured by ADC' ] = 1
except:
util.err_msg("Failed to decode wordfip message")
result['Decoding of messages captured by ADC' ] = 0
result['Request message captured by ADC' ] = 0
result['Number of frames captured by ADC' ] = 0
result['Response message captured by ADC' ] = 0
if (result[ 'Captured ADC transmission' ] + result['Number of frames captured by ADC' ] + result['Request message captured by ADC' ] + result['Response message captured by ADC' ]) == 4:
if should_succed:
util.info_msg("Test succeeded")
else:
util.info_msg("Test failed")
else:
if not should_succed:
util.info_msg("Test succeeded")
else:
util.info_msg("Test failed")
return result
def main (card=None, default_directory='.',suite=None, serial=""):
testname= "Test03: Power switching, ADC, Relays"
util.header_msg( testname, [ "ADC powering",
"ADC communication",
"ADC data acquisition",
"ADC relays switching",
"ADC front end"] )
box = util.calibration_box_init()
util.section_msg("Hardware initialization")
[carrier, dut, abspath ] = init();
# starttime=datetime.datetime.now().strftime("%Y_%m_%d_%H_%M_%S")
prefix="mfdata_"
starttime=""
outputpath = util.test03_outputpath
# make sure that bus communication is possible
util.section_msg("Bus communication test")
result = verify_presence( dut );
#####################################################
# should be called before powering ADC on
util.section_msg("ADC serial interface test")
result = util.merge_dictionaries(result, test_adc_spi(dut) )
#####################################################
dut.adc_init();
time.sleep(1)
#####################################################
# close primary side relay
dut.close_relay(1);
time.sleep(1)
#####################################################
util.section_msg("Sampling WorldFIP bus during normal traffic. Sampling transformer pins connected to LOCAL bus driver.")
result = util.merge_dictionaries_prefix(result, test_transmission( dut, True, True, True ), "", "Primary transformer side. " )
dut.save_transmission(outputpath+prefix+starttime+"_primary")
util.section_msg("Sampling WorldFIP bus WITHOUT traffic. Sampling transformer pins connected to LOCAL bus driver.")
tmp = test_transmission( dut, False, False, True );
result["Captured ADC transmission on primary transformer side without without generating any traffic"] = 1 if tmp[ 'Captured ADC transmission'] == 0 else 0
dut.save_transmission(outputpath+prefix+starttime+"_primary_notraffic")
#####################################################
# close primary side relay
dut.close_relay(2);
time.sleep(1)
#####################################################
util.section_msg("Sampling WorldFIP bus during normal traffic. Sampling transformer pins connected to EXTERNAL bus.")
result = util.merge_dictionaries_prefix(result, test_transmission( dut, True, True, False ), "", "Secondary transformer side. " )
dut.save_transmission(outputpath+prefix+starttime+"_secondary")
util.section_msg("Sampling WorldFIP bus WITHOUT traffic. Sampling transformer pins connected to EXTERNAL bus driver.")
tmp = test_transmission( dut, False, False, False );
result["Captured ADC transmission on secondary transformer side without generating any traffic"] = 1 if tmp['Captured ADC transmission'] == 0 else 0
dut.save_transmission(outputpath+prefix+starttime+"_secondary_notraffic")
#####################################################
# disconnect both relays
dut.close_relay(0);
time.sleep(1)
#####################################################
util.section_msg("Sampling WorldFIP bus during normal traffic. ADC is disconnected from transformer!")
tmp = test_transmission( dut, True, False, False );
result["Captured ADC transmission when ADC should be disconnected"] = 1 if tmp[ 'Captured ADC transmission'] == 0 else 0
dut.save_transmission(outputpath+prefix+starttime+"_disconnected")
util.section_msg("Sampling WorldFIP bus without traffic. ADC is disconnected from transformer!")
tmp = test_transmission( dut, False, False, False );
result["Captured ADC transmission when ADC should be disconnected and no traffic is generated"] = 1 if tmp[ 'Captured ADC transmission'] == 0 else 0
dut.save_transmission(outputpath+prefix+starttime+"_disconnected_notraffic")
#####################################################
errors = util.summarise_test_results( testname, result)
util.info_msg("Please note that data acquired by ADC was backed up in log/adcdata directory")
return 0
if __name__ == '__main__' :
main()
python/test05.py
View file @ 0e2e9c99
......@@ -135,7 +135,7 @@ def main (card=None, default_directory='.',suite=None, serial=None):
# serial
"-s", serial,
# part
"-p", "EDA-03098-V1-%d" % speed,
"-p", "EDA-03098-V3-%d" % speed,
# output
"-o", sdbfs_path+"/IPMI-FRU" ]
)
......
python/test06.py
View file @ 0e2e9c99
......@@ -9,258 +9,251 @@
import spec
import fmcmasterfip as fmc
import utilities as util
import ptsexcept
import time
DEL = 0.5
NRSAMPLES = 10
def test_sync_output( dut, box ):
###############################################################################
def test_sync_input( dut, box ):
util.section_msg("Testing trigger in output mode")
result = {}
# enable output
dut.fipcore.write_regname('ext_sync.oe', 1)
# disable termination
dut.fipcore.write_regname('ext_sync.term_en', 0)
# set output value
dut.fipcore.write_regname('ext_sync.output_value', 0)
# set trigger to output direction
dut.fipcore.write_regname('ext_sync.dir', 1)
util.info_msg("Setting trigger to output")
# connect trigger to channel 2 of ADC
box.trigger_output_to_awg()
util.section_msg("Testing synchronisation input")
util.info_msg("Connecting ADC to channel 1 of secondary transformer side ")
# connect ADC to secondary transformer side (connected to trigger)
dut.close_relay( 2 )
# wait
time.sleep(DEL)
###############################################################################
util.info_msg("")
util.info_msg("Generating low output")
result['Trigger output verified to go low'] = 1
for i in xrange(NRSAMPLES):
adc_samples = dut.adc_single_sample()
if adc_samples[1] < util.test06_thd:
# util.info_msg("Value read by ADC: CH1=%d, CH2=%d" %( adc_samples[0], adc_samples[1] ) )
util.info_msg("Value read by ADC: %d" %( adc_samples[1] ) )
else:
# util.err_msg("Value read by ADC: CH1=%d, CH2=%d" %( adc_samples[0], adc_samples[1] ) )
util.err_msg("Value read by ADC: %d" %( adc_samples[1] ) )
result['Trigger output verified to go low'] = 0
time.sleep(0.1)
#######################
util.info_msg("")
util.info_msg("Generating high output")
dut.fipcore.write_regname('ext_sync.output_value', 1)
result['Trigger output verified to go high'] = 1
time.sleep(DEL)
util.info_msg("Setting synchronisation line to input")
dut.fipcore.write_regname('ext_sync.dir', 0)
dut.fipcore.write_regname('ext_sync.fpga_io_dir', 0)
# sample "1" output generated by sync buffer
# do that for termination enabled and disabled
# with termination enabled registered voltage should about 2x lower
sampled = [0, 0]
for t in xrange(2):
# set termination (0 or 1)
util.info_msg("")
util.info_msg( "Termination : %d" % t)
dut.fipcore.write_regname('ext_sync.term_en', t)
for i in xrange(NRSAMPLES):
adc_samples = dut.adc_single_sample()
sampled[t] += adc_samples[1];
if adc_samples[1] >= util.test06_thd:
util.info_msg("Value read by ADC: %d" % adc_samples[1] )
else:
util.err_msg("Value read by ADC: %d" % adc_samples[1] )
result['Trigger output verified to go high'] = 0
time.sleep(0.1)
time.sleep(DEL)
util.info_msg("")
util.info_msg("Mean value sampled without termination : %d" % (sampled[0]/NRSAMPLES) )
util.info_msg("Mean value sampled with termination : %d" % (sampled[1]/NRSAMPLES) )
util.info_msg("Enabling buffer")
dut.fipcore.write_regname('ext_sync.oe', 1)
output_ratio_term = float(sampled[0])/float(sampled[1])
util.info_msg("Disabling termination")
dut.fipcore.write_regname('ext_sync.term_en', 0)
util.info_msg("Connecting synchronisation line to low voltage in relay box")
box.trigger_input_low()
if output_ratio_term < util.test06_thdratio :
util.err_msg("Ratio of output value with and without termination is %f. Should be over %f." % ( output_ratio_term, util.test06_thdratio ) )
result['External sync termination'] = 0
else :
util.info_msg("Ratio of output value with and without termination is %f. Should be over %f." % ( output_ratio_term, util.test06_thdratio ) )
result['External sync termination'] = 1
time.sleep(DEL)
if dut.fipcore.read_regname('ext_sync_raw_input') == 0:
result['Input low'] = 1
util.info_msg("Read low input value")
else :
result['Input low'] = 0
util.err_msg("Read high input value, even though low value is generated in relay box")
###############################################################################
#######################
util.info_msg("\nDisabling bidir buffer output:")
# disable output
dut.fipcore.write_regname('ext_sync.oe', 0)
time.sleep(DEL)
util.info_msg("Connecting synchronisation line to high voltage in relay box")
box.trigger_input_high()
for i in xrange(NRSAMPLES):
adc_samples = dut.adc_single_sample()
sampled[t] += adc_samples[1];
if adc_samples[1] <= util.test06_thd:
util.info_msg("Value read by ADC: %d" % adc_samples[1] )
result['Read low value with bidir buffer OE disabled'] = 1
else:
util.err_msg("Output remains high when the bidir buffer OE is disabled. Value read by ADC: %d" % adc_samples[1])
result['Read low value with bidir buffer OE disabled'] = 0
time.sleep(0.1)
time.sleep(DEL)
util.info_msg("")
util.info_msg("Output verified to go low when the bidir buffer OE is disabled.")
if dut.fipcore.read_regname('ext_sync_raw_input') == 1:
result['Input high'] = 1
util.info_msg("Read high input value")
else :
result['Termination disabled'] = 0
util.err_msg("Read low input value, even though high value is generated by relay box")
box.trigger_input_low()
return result
#######################
def test_termination( dut, box ):
result = {}
util.section_msg("Testing termination circuit")
util.info_msg("\nEnabling bidir buffer output:")
# disable output
###############################################################################
util.info_msg("Setting synchronisation line to input")
dut.fipcore.write_regname('ext_sync.dir', 0)
dut.fipcore.write_regname('ext_sync.fpga_io_dir', 0)
util.info_msg("Enabling buffer")
dut.fipcore.write_regname('ext_sync.oe', 1)
for i in xrange(NRSAMPLES):
adc_samples = dut.adc_single_sample()
sampled[t] += adc_samples[1];
if adc_samples[1] >= util.test06_thd:
util.info_msg("Value read by ADC: %d" % adc_samples[1] )
result['Read high value with bidir buffer OE enabled'] = 1
else:
util.err_msg("Output is high when the bidir buffer OE is enabled. Value read by ADC: %d" % adc_samples[1])
result['Read high value with bidir buffer OE enabled'] = 0
time.sleep(0.1)
util.info_msg("Disabling termination")
dut.fipcore.write_regname('ext_sync.term_en', 0)
util.info_msg("Connecting synchronisation line to high voltage in relay box")
box.trigger_input_high()
time.sleep(DEL)
if dut.fipcore.read_regname('ext_sync_raw_input') == 1:
result['Termination disabled'] = 1
util.info_msg("Read high input value")
else :
result['Termination disabled'] = 0
util.err_msg("Read low input value, even though high value is generated by relay box")
util.info_msg("")
util.info_msg("Output verified to go high when the bidir buffer OE is enabled.")
###############################################################################
util.info_msg("Enabling termination (pulldown)")
dut.fipcore.write_regname('ext_sync.term_en', 0)
time.sleep(DEL)
if dut.fipcore.read_regname('ext_sync_raw_input') == 0:
result['Termination enabled'] = 1
util.info_msg("Read low input value")
else :
result['Termination enabled'] = 0
util.err_msg("Read high input value, even though pulldown circuit is enabled")
#######################
###############################################################################
# set output value low
dut.fipcore.write_regname('ext_sync.output_value', 0)
time.sleep(DEL)
util.info_msg("")
util.info_msg("Generating low output again")
result['Trigger output verified to go low for the second time'] = 1
for i in xrange(NRSAMPLES):
adc_samples = dut.adc_single_sample()
util.dbg_msg("Read ADC value: CH1=%d, CH2=%d low trigger output" %( adc_samples[0], adc_samples[1] ) )
if adc_samples[1] < util.test06_thd:
util.info_msg("Value read by ADC: %d" % adc_samples[1] )
else:
util.err_msg("Value read by ADC: %d" % adc_samples[1] )
result['Trigger output verified to go low for the second time'] = 0
time.sleep(0.1)
dut.fipcore.write_regname('ext_sync.term_en', 0)
box.trigger_input_low()
return result
def test_oen( dut, box ):
result = {}
util.section_msg("Testing output enable")
###############################################################################
def test_sync_input( dut, box ):
result = {}
util.info_msg("Setting synchronisation line to input")
dut.fipcore.write_regname('ext_sync.dir', 0)
dut.fipcore.write_regname('ext_sync.fpga_io_dir', 0)
util.section_msg("Testing trigger in input mode")
util.info_msg("Disabling buffer")
dut.fipcore.write_regname('ext_sync.oe', 0)
util.info_msg("Disabling termination")
dut.fipcore.write_regname('ext_sync.term_en', 0)
util.info_msg("Connecting synchronisation line to low voltage in relay box")
box.trigger_input_low()
time.sleep(DEL)
util.info_msg("Setting trigger to input")
# set trigger to input direction
dut.fipcore.write_regname('ext_sync.dir', 0)
lowinput = dut.fipcore.read_regname('ext_sync_raw_input')
# enable tranceiver output
dut.fipcore.write_regname('ext_sync.oe', 1)
if lowinput == 0:
util.info_msg("Read low input value")
else :
util.err_msg("Read high input value" )
###############################################################################
# enable termination (should bring input to gnd via resistors)
dut.fipcore.write_regname('ext_sync.term_en', 1)
util.info_msg("Connecting synchronisation line to high voltage in relay box")
box.trigger_input_high()
time.sleep(DEL);
time.sleep(DEL)
if dut.fipcore.read_regname('ext_sync_raw_input') == 0 :
util.info_msg("Value read from trigger input is 0")
result['Read low value on trigger input with pulldown resistor enabled'] = 1
else:
util.err_msg("Value read from trigger input is 1")
result['Read low value on trigger input with pulldown resistor enabled'] = 0
highinput = dut.fipcore.read_regname('ext_sync_raw_input')
if highinput == 0:
util.info_msg("Read low input value")
else :
util.err_msg("Read high input value" )
time.sleep(DEL);
box.trigger_input_low()
time.sleep(DEL)
###############################################################################
if lowinput = highinput :
result['Output enable'] = 1
util.info_msg("Value read from disabled buffer didn't change no matter buffer input")
else :
util.info_err_msg("Value read from buffer changed, although output should be disabled")
result['Output enable'] = 0
return result
def test_dir( dut, box ):
#######################
result = {}
util.info_msg("")
util.info_msg("Connecting input to reference voltage in calibration box")
util.info_msg("Setting low input voltage")
box.trigger_input_low()
util.section_msg("Testing direction selection")
util.section_msg("Hack: Synchronisation input test will be repeated, with external buffer set to output")
util.section_msg("Hack: Value read on FPGA input shouldn't change, although synchronisation input changes")
# set trigger to input direction
dut.fipcore.write_regname('ext_sync.dir', 0)
# enable output
###############################################################################
util.info_msg("Setting synchronisation line buffer to OUTPUT")
dut.fipcore.write_regname('ext_sync.dir', 1)
util.info_msg("Setting synchronisation IO in FPGA to INPUT")
dut.fipcore.write_regname('ext_sync.fpga_io_dir', 0)
util.info_msg("Enabling buffer")
dut.fipcore.write_regname('ext_sync.oe', 1)
# disable termination
util.info_msg("Disabling termination")
dut.fipcore.write_regname('ext_sync.term_en', 0)
util.info_msg("Connecting synchronisation line to low voltage in relay box")
box.trigger_input_low()
time.sleep(DEL)
if dut.fipcore.read_regname('ext_sync_raw_input') == 0:
result['Trigger input read low'] = 1
util.info_msg("Read low input value")
lowinput = dut.fipcore.read_regname('ext_sync_raw_input')
if lowinput == 0:
util.info_msg("Read low input value")
else :
util.err_msg("Read high input value")
result['Trigger input read low'] = 0
util.info_msg("")
util.info_msg("Setting high input voltage")
util.err_msg("Read high input value" )
###############################################################################
util.info_msg("Connecting synchronisation line to high voltage in relay box")
box.trigger_input_high()
time.sleep(DEL)
if dut.fipcore.read_regname('ext_sync_raw_input') == 1 :
result['Trigger input read high'] = 1
util.info_msg("Read high input value")
highinput = dut.fipcore.read_regname('ext_sync_raw_input')
if highinput == 0:
util.info_msg("Read low input value")
else :
util.err_msg("Read low input value")
result['Trigger input read high'] = 0
util.err_msg("Read high input value" )
box.trigger_input_low()
dut.fipcore.write_regname('ext_sync.dir', 0)
time.sleep(DEL)
###############################################################################
if lowinput = highinput :
result['Direction selection'] = 1
util.info_msg("Value read from buffer set to output didn't change no matter buffer input")
else :
result['Direction selection'] = 0
util.info_err_msg("Value read from buffer changed, although buffer should be set to output")
return result
def main (card=None, default_directory='.',suite=None, serial=""):
testname= "Test06: Trigger Input/Output"
util.header_msg( testname, [ "Bidirectional Buffer communication",
"Termination switching",
"Test pullup resistor switching",
"Reading trigger input",
"Generating trigger output" ] )
"Reading trigger input" ] )
###############################################################################
############################ initialization ###################################
......@@ -285,8 +278,12 @@ def main (card=None, default_directory='.',suite=None, serial=""):
test_results = util.merge_dictionaries( test_results, test_sync_input( dut, box ) )
test_results = util.merge_dictionaries( test_results, test_termination( dut, box ) )
test_results = util.merge_dictionaries( test_results, test_oen( dut, box ) )
test_results = util.merge_dictionaries( test_results, test_sync_output( dut, box ) )
test_results = util.merge_dictionaries( test_results, test_dir( dut, box ) )
###############################################################################
......
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