--_________________________________________________________________________________________________
--                                                                                                |
--                                         |The nanoFIP|                                          |
--                                                                                                |
--                                         CERN,BE/CO-HT                                          |
--________________________________________________________________________________________________|

---------------------------------------------------------------------------------------------------
--                                                                                                |
--                                         masterFIP_pkg                                          |
--                                                                                                |
---------------------------------------------------------------------------------------------------
-- File         masterFIP_pkg.vhd                                                                 |
--                                                                                                |
-- Description  Definitions of constants, types, entities, functions                              |
-- Author       Evangelia Gousiou     (Evangelia.Gousiou@cern.ch)                                 |
-- Date         30/09/2015                                                                        |
-- Version      v0.01                                                                             |
--                                                                                                |
----------------                                                                                  |
-- Last changes                                                                                   |
--     09/2015  v0.01  EG  First version                                                          |
---------------------------------------------------------------------------------------------------

---------------------------------------------------------------------------------------------------
--                               GNU LESSER GENERAL PUBLIC LICENSE                                |
--                              ------------------------------------                              |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either     |
-- version 2.1 of the License, or (at your option) any later version.                             |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;       |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.      |
-- See the GNU Lesser General Public License for more details.                                    |
-- You should have received a copy of the GNU Lesser General Public License along with this       |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html                     |
---------------------------------------------------------------------------------------------------



--=================================================================================================
--                                      Libraries & Packages
--=================================================================================================

-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all;    -- conversion functions
use work.wishbone_pkg.all;
use work.gencores_pkg.all;
use work.wf_package.all;


--=================================================================================================
--                              Package declaration for masterFIP_pkg
--=================================================================================================
package masterFIP_pkg is


---------------------------------------------------------------------------------------------------
--                        Constants regarding the SDB Devices Definitions                        --
---------------------------------------------------------------------------------------------------
-- Note: All address in sdb and crossbar are BYTE addresses!

  -- Devices sdb description
  constant c_ONEWIRE_SDB_DEVICE : t_sdb_device :=
    (abi_class     => x"0000",               -- undocumented device
     abi_ver_major => x"01",
     abi_ver_minor => x"01",
     wbd_endian    => c_sdb_endian_big,
     wbd_width     => x"4",                  -- 32-bit port granularity
     sdb_component =>
       (addr_first  => x"0000000000000000",
        addr_last   => x"0000000000000007",
        product     =>
          (vendor_id => x"000000000000CE42", -- CERN
           device_id => x"00000602",         -- "WB-Onewire.Control " | md5sum | cut -c1-8
           version   => x"00000001",
           date      => x"20121116",
           name      => "WB-Onewire.Control ")));

  constant c_SPEC_INFO_SDB_DEVICE : t_sdb_device :=
    (abi_class     => x"0000",               -- undocumented device
     abi_ver_major => x"01",
     abi_ver_minor => x"01",
     wbd_endian    => c_sdb_endian_big,
     wbd_width     => x"4",                  -- 32-bit port granularity
     sdb_component =>
       (addr_first  => x"0000000000000000",
        addr_last   => x"000000000000001F",
        product     =>
          (vendor_id => x"000000000000CE42", -- CERN
           device_id => x"00000603",         -- "WB-SPEC.CSR        " | md5sum | cut -c1-8
           version   => x"00000001",
           date      => x"20121116",
           name      => "WB-SPEC.CSR        ")));

  constant c_I2C_SDB_DEVICE : t_sdb_device :=
    (abi_class     => x"0000",               -- undocumented device
     abi_ver_major => x"01",
     abi_ver_minor => x"01",
     wbd_endian    => c_sdb_endian_big,
     wbd_width     => x"4",                  -- 32-bit port granularity
     sdb_component =>
       (addr_first  => x"0000000000000000",
        addr_last   => x"000000000000001F",
        product     =>
          (vendor_id => x"000000000000CE42", -- CERN
           device_id => x"00000606",         -- "WB-I2C.Control     " | md5sum | cut -c1-8
           version   => x"00000001",
           date      => x"20121116",
           name      => "WB-I2C.Control     ")));

  constant c_MASTERFIP_SDB_DEVICE : t_sdb_device :=
    (abi_class     => x"0000",               -- undocumented device
     abi_ver_major => x"01",
     abi_ver_minor => x"01",
     wbd_endian    => c_sdb_endian_big,
     wbd_width     => x"4",                  -- 32-bit port granularity
     sdb_component =>
       (addr_first  => x"0000000000000000",
--        addr_last   => x"000000000000FFFF",
        addr_last   => x"00000000000003FF",
--        addr_last   => x"00000000000000FF",
        product     =>
          (vendor_id => x"000000000000CE42", -- CERN
           device_id => x"00000AAA",         -- ...
           version   => x"00000001",
           date      => x"20151006",
           name      => "WB-MASTERFIP.CSR   ")));


---------------------------------------------------------------------------------------------------
--                                Vector with the data Registers                                 --
---------------------------------------------------------------------------------------------------
  subtype data_word is std_logic_vector(31 downto 0);
  type rx_frame_t   is array (65 downto 0) of data_word;
  type tx_frame_t   is array (65 downto 0) of data_word;



---------------------------------------------------------------------------------------------------
--                 Constants regarding the position of bytes in the frame structure              --
---------------------------------------------------------------------------------------------------

  constant c_SUBS_BYTE_INDEX     : std_logic_vector (7 downto 0) := "00000010"; -- 2
  constant c_1st_DATA_BYTE_INDEX : std_logic_vector (7 downto 0) := "00000011"; -- 3


---------------------------------------------------------------------------------------------------
--                           Constants regarding the One-Wire interface                          --
---------------------------------------------------------------------------------------------------
  constant c_FMC_ONEWIRE_NB   : integer := 1;


---------------------------------------------------------------------------------------------------
--                            Constants regarding the Carrier CSR info                           --
---------------------------------------------------------------------------------------------------
  constant c_CARRIER_TYPE   : std_logic_vector(15 downto 0) := X"0001";



---------------------------------------------------------------------------------------------------
--                                      Components Declarations:                                 --
---------------------------------------------------------------------------------------------------
  
  component fmc_masterfip_csr is
  port (
    rst_n_i                     : in     std_logic;
    clk_sys_i                   : in     std_logic;
    wb_adr_i                    : in     std_logic_vector(7 downto 0);
    wb_dat_i                    : in     std_logic_vector(31 downto 0);
    wb_dat_o                    : out    std_logic_vector(31 downto 0);
    wb_cyc_i                    : in     std_logic;
    wb_sel_i                    : in     std_logic_vector(3 downto 0);
    wb_stb_i                    : in     std_logic;
    wb_we_i                     : in     std_logic;
    wb_ack_o                    : out    std_logic;
    wb_stall_o                  : out    std_logic;

    mf_rstn_core_o              : out    std_logic;
    mf_rstn_fd_o                : out    std_logic;
    mf_rstn_lock_o              : out    std_logic_vector(15 downto 0);
    mf_rstn_lock_wr_o           : out    std_logic;
    
    mf_dbg_o                    : out    std_logic_vector(31 downto 0);    
    
    mf_adc_1v8_shdn_n_o         : out    std_logic;
    mf_adc_m5v_shdn_n_o         : out    std_logic;
    mf_adc_5v_en_n_o            : out    std_logic;
    mf_adc_prim_conn_n_o        : out    std_logic;
    mf_adc_sec_conn_n_o         : out    std_logic;

    mf_ext_sync_term_en_o       : out    std_logic;
    mf_ext_sync_dir_o           : out    std_logic;
    mf_ext_sync_oe_o            : out    std_logic;
    mf_ext_sync_tst_n_o         : out    std_logic;
    mf_ext_sync_p_cnt_rst_o     : out    std_logic;
    mf_ext_sync_p_cnt_i         : in     std_logic_vector(31 downto 0);
    
    mf_bus_term_en_n_o          : out    std_logic;
    mf_speed_i                  : in     std_logic_vector(1 downto 0);

    mf_macrocyc_lgth_o          : out    std_logic_vector(30 downto 0);
    mf_macrocyc_start_o         : out    std_logic;
    mf_macrocyc_num_cnt_i       : in     std_logic_vector(31 downto 0);
    mf_turnar_lgth_o            : out    std_logic_vector(30 downto 0);
    mf_turnar_start_o           : out    std_logic;
    mf_silen_lgth_o             : out    std_logic_vector(30 downto 0);
    mf_silen_start_o            : out    std_logic;
    mf_macrocyc_time_cnt_i      : in     std_logic_vector(30 downto 0);
    mf_turnar_time_cnt_i        : in     std_logic_vector(30 downto 0);
    mf_silen_time_cnt_i         : in     std_logic_vector(30 downto 0);

    mf_tx_ctrl_rst_o            : out    std_logic;
    mf_tx_ctrl_start_o          : out    std_logic;
    mf_tx_ctrl_bytes_num_o      : out    std_logic_vector(8 downto 0);
    mf_tx_stat_stop_i           : in     std_logic;
    mf_tx_stat_byte_index_i     : in     std_logic_vector(8 downto 0);
    mf_tx_stat_ena_i            : in     std_logic;
    
    mf_fd_wdgn_i                : in     std_logic;
    mf_fd_txer_i                : in     std_logic;
    
    mf_rx_ctrl_rst_o            : out    std_logic;
    mf_rx_stat_pream_ok_i       : in     std_logic;
    mf_rx_stat_frame_ok_i       : in     std_logic;
    mf_rx_stat_frame_err_i      : in     std_logic;
    mf_rx_stat_frame_err_code_i : in     std_logic_vector(2 downto 0);
    mf_rx_stat_bytes_num_i      : in     std_logic_vector(8 downto 0);
    
    mf_rx_data_ctrl_i           : in     std_logic_vector(7 downto 0);
    mf_rx_data_reg1_i           : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg2_i           : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg3_i           : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg4_i           : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg5_i           : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg6_i           : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg7_i           : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg8_i           : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg9_i           : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg10_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg11_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg12_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg13_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg14_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg15_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg16_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg17_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg18_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg19_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg20_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg21_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg22_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg23_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg24_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg25_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg26_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg27_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg28_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg29_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg30_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg31_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg32_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg33_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg34_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg35_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg36_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg37_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg38_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg39_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg40_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg41_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg42_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg43_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg44_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg45_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg46_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg47_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg48_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg49_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg50_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg51_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg52_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg53_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg54_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg55_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg56_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg57_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg58_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg59_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg60_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg61_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg62_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg63_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg64_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg65_i          : in     std_logic_vector(31 downto 0);
    mf_rx_data_reg66_i          : in     std_logic_vector(31 downto 0);
    
    mf_tx_data_ctrl_o                 : out    std_logic_vector(7 downto 0);
    mf_tx_data_reg1_o                 : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg2_o                 : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg3_o                 : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg4_o                 : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg5_o                 : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg6_o                 : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg7_o                 : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg8_o                 : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg9_o                 : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg10_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg11_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg12_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg13_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg14_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg15_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg16_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg17_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg18_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg19_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg20_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg21_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg22_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg23_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg24_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg25_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg26_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg27_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg28_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg29_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg30_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg31_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg32_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg33_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg34_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg35_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg36_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg37_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg38_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg39_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg40_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg41_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg42_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg43_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg44_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg45_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg46_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg47_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg48_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg49_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg50_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg51_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg52_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg53_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg54_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg55_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg56_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg57_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg58_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg59_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg60_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg61_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg62_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg63_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg64_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg65_o                : out    std_logic_vector(31 downto 0);
    mf_tx_data_reg66_o                : out    std_logic_vector(31 downto 0));
  end component;
  
---------------------------------------------------------------------------------------------------
  component fmc_masterFIP_core is
  generic
    (g_span             : integer := 32;
     g_width            : integer := 32;
     values_for_simul   : boolean := FALSE);
  port
    (clk_i              : in    std_logic;
     rst_i              : in    std_logic;
     speed_b0_i         : in    std_logic;
     speed_b1_i         : in    std_logic;
     fd_rxcdn_i         : in    std_logic;
     fd_rxd_i           : in    std_logic;
     fd_txer_i          : in    std_logic;
     fd_wdgn_i          : in    std_logic;
     fd_rstn_o          : out   std_logic;
     fd_txck_o          : out   std_logic;
     fd_txd_o           : out   std_logic;
     fd_txena_o         : out   std_logic;
     bus_term_en_n_o    : out std_logic;
     ext_sync_term_en_o : out std_logic;
     ext_sync_dir_o     : out std_logic;
     ext_sync_oe_o      : out std_logic;
     ext_sync_tst_n_o   : out std_logic;
     ext_sync_i         : in std_logic;
     adc_1v8_shdn_n_o   : out std_logic;
     adc_m5v_shdn_n_o   : out std_logic;
     adc_5v_en_n_o      : out std_logic;
     adc_prim_conn_n_o  : out std_logic;
     adc_sec_conn_n_o   : out std_logic;
     aux_o              : out   std_logic_vector(7 downto 0);
     wb_adr_i           : in    std_logic_vector(g_span-1 downto 0);
     wb_dat_i           : in    std_logic_vector(g_width-1 downto 0);
     wb_stb_i           : in    std_logic;
     wb_sel_i           : in    std_logic_vector(3 downto 0);
     wb_we_i            : in    std_logic;
     wb_cyc_i           : in    std_logic;
     wb_ack_o           : out   std_logic;
     wb_stall_o         : out   std_logic;
     wb_dat_o           : out   std_logic_vector(g_width-1 downto 0));
  end component;


---------------------------------------------------------------------------------------------------
  component spec_reset_gen is
  port
    (clk_sys_i        : in std_logic;
     rst_pcie_n_a_i   : in std_logic;
     rst_button_n_a_i : in std_logic;
     rst_n_o          : out std_logic);
  end component;


---------------------------------------------------------------------------------------------------
  component carrier_info
    port
      (rst_n_i                           : in  std_logic;
       clk_sys_i                         : in  std_logic;
       wb_adr_i                          : in  std_logic_vector(1 downto 0);
       wb_dat_i                          : in  std_logic_vector(31 downto 0);
       wb_dat_o                          : out std_logic_vector(31 downto 0);
       wb_cyc_i                          : in  std_logic;
       wb_sel_i                          : in  std_logic_vector(3 downto 0);
       wb_stb_i                          : in  std_logic;
       wb_we_i                           : in  std_logic;
       wb_ack_o                          : out std_logic;
       wb_stall_o                        : out std_logic;
       carrier_info_carrier_pcb_rev_i    : in  std_logic_vector(3 downto 0);
       carrier_info_carrier_reserved_i   : in  std_logic_vector(11 downto 0);
       carrier_info_carrier_type_i       : in  std_logic_vector(15 downto 0);
       carrier_info_stat_fmc_pres_i      : in  std_logic;
       carrier_info_stat_p2l_pll_lck_i   : in  std_logic;
       carrier_info_stat_sys_pll_lck_i   : in  std_logic;
       carrier_info_stat_ddr3_cal_done_i : in  std_logic;
       carrier_info_stat_reserved_i      : in  std_logic_vector(27 downto 0);
       carrier_info_ctrl_led_green_o     : out std_logic;
       carrier_info_ctrl_led_red_o       : out std_logic;
       carrier_info_ctrl_dac_clr_n_o     : out std_logic;
       carrier_info_ctrl_reserved_o      : out std_logic_vector(28 downto 0);
       carrier_info_rst_fmc0_n_o         : out std_logic;
       carrier_info_rst_fmc0_n_i         : in  std_logic;
       carrier_info_rst_fmc0_n_load_o    : out std_logic;
       carrier_info_rst_reserved_o       : out std_logic_vector(30 downto 0));
  end component carrier_info;
  

---------------------------------------------------------------------------------------------------
  component masterfip_rx is
  port (
    clk_i                 : in std_logic;
    speed_i               : in std_logic_vector (1 downto 0);
    fd_rxd_a_i            : in std_logic;
    rst_i                 : in std_logic;
    rx_rst_i              : in std_logic;
  -----------------------------------------------------------------
    rx_byte_index_o       : out std_logic_vector (8 downto 0);
    rx_ctrl_byte_o        : out std_logic_vector (7 downto 0);
    rx_frame_o            : out rx_frame_t; 
    rx_byte_o             : out std_logic_vector (7 downto 0);
    rx_byte_ready_p_o     : out std_logic;
    rx_fss_crc_fes_ok_p_o : out std_logic;
    rx_fss_received_p_o   : out std_logic;
    rx_crc_wrong_p_o      : out std_logic );
  -----------------------------------------------------------------
  end component masterfip_rx;


---------------------------------------------------------------------------------------------------
  component masterfip_tx is
  port (
    clk_i                 : in std_logic;
    speed_i               : in std_logic_vector (1 downto 0);
    rst_i                 : in std_logic;
    tx_start_p_i          : in std_logic;
    tx_bytes_num_i        : in std_logic_vector (8 downto 0);
    tx_frame_i            : in tx_frame_t;
    tx_ctrl_byte_i        : in std_logic_vector (7 downto 0);
  -----------------------------------------------------------------
    tx_byte_index_o       : out std_logic_vector (8 downto 0);
    tx_end_p_o            : out std_logic;
    tx_data_o             : out std_logic;
    tx_enable_o           : out std_logic;
    tx_clk_o              : out std_logic);
  -----------------------------------------------------------------
  end component masterfip_tx;

  
---------------------------------------------------------------------------------------------------
  component decr_counter
  generic
    (width             : integer := 32);
  port
    (clk_i             : in std_logic;
     rst_i             : in std_logic;
     counter_load_i    : in std_logic;
     counter_top_i     : in std_logic_vector(width-1 downto 0);
    -------------------------------------------------------------
     counter_is_zero_o : out std_logic;
     counter_o         : out std_logic_vector(width-1 downto 0));
    -------------------------------------------------------------
  end component;


---------------------------------------------------------------------------------------------------
  component incr_counter is
  generic
    (g_counter_lgth    : natural := 4);
  port
    (clk_i             : in std_logic;
     counter_incr_i    : in std_logic;
     counter_reinit_i  : in std_logic;
    -------------------------------------------------------------
     counter_o         : out std_logic_vector (g_counter_lgth-1 downto 0);
     counter_is_full_o : out std_logic);
  end component incr_counter;
    -------------------------------------------------------------
  
end masterFIP_pkg;

--=================================================================================================
--                                         package end
--=================================================================================================
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--                                      E N D   O F   F I L E
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