#===============================================================================
# The IO Location Constraints
#===============================================================================

#----------------------------------------
# Clock inputs
#----------------------------------------
# CLK25_VCXO
NET "clk20_vcxo_i" LOC = H12;
NET "clk20_vcxo_i" IOSTANDARD = LVCMOS25;

#NET "clk_125m_pllref_n_i" LOC = F10;
#NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
#NET "clk_125m_pllref_p_i" LOC = G9;
#NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";

#----------------------------------------
# SFP slot
# !! SFP_TX_DISABLE and SFP_MOD_DEF1 are swapped in V1.1 schematics for control signals
#----------------------------------------
#NET "SFPRX_123_N" LOC = C15;
#NET "SFPRX_123_N" IOSTANDARD = "LVCMOS25";
#NET "SFPRX_123_P" LOC = D15;
#NET "SFPRX_123_P" IOSTANDARD = "LVCMOS25";
#NET "SFPTX_123_N" LOC = A16;
#NET "SFPTX_123_N" IOSTANDARD = "LVCMOS25";
#NET "SFPTX_123_P" LOC = B16;
#NET "SFPTX_123_P" IOSTANDARD = "LVCMOS25";
#NET "SFP_TX_FAULT" LOC = B18;
#NET "SFP_TX_FAULT" IOSTANDARD = "LVCMOS25";
#NET "SFP_TX_DISABLE" LOC = F17;
#NET "SFP_TX_DISABLE" IOSTANDARD = "LVCMOS25";
#NET "SFP_LOS" LOC = D18;
#NET "SFP_LOS" IOSTANDARD = "LVCMOS25";
#NET "SFP_MOD_DEF1" LOC = C17;
#NET "SFP_MOD_DEF1" IOSTANDARD = "LVCMOS25";
#NET "SFP_MOD_DEF0" LOC = G15;
#NET "SFP_MOD_DEF0" IOSTANDARD = "LVCMOS25";
#NET "SFP_MOD_DEF2" LOC = G16;
#NET "SFP_MOD_DEF2" IOSTANDARD = "LVCMOS25";
#NET "SFP_RATE_SELECT" LOC = H14;
#NET "SFP_RATE_SELECT" IOSTANDARD = "LVCMOS25";

#----------------------------------------
# DAC interface (for VCXO)
#----------------------------------------
NET "pll25dac_sync_n_o" LOC = A3;
NET "pll25dac_sync_n_o" IOSTANDARD = LVCMOS25;
NET "pll20dac_sync_n_o" LOC = B3;
NET "pll20dac_sync_n_o" IOSTANDARD = LVCMOS25;
NET "plldac_din_o" LOC = C4;
NET "plldac_din_o" IOSTANDARD = LVCMOS25;
NET "plldac_sclk_o" LOC = A4;
NET "plldac_sclk_o" IOSTANDARD = LVCMOS25;

#----------------------------------------
# 1-wire thermometer w/ ID
#----------------------------------------
NET "carrier_one_wire_b" LOC = D4;
NET "carrier_one_wire_b" IOSTANDARD = LVCMOS25;

#----------------------------------------
# GN4124 interface
#----------------------------------------
NET "L_RST_N" LOC = N20;
NET "L_RST_N" IOSTANDARD = LVCMOS18;
NET "L2P_CLKn" LOC = K22;
NET "L2P_CLKn" IOSTANDARD = DIFF_SSTL18_I;
NET "L2P_CLKp" LOC = K21;
NET "L2P_CLKp" IOSTANDARD = DIFF_SSTL18_I;
NET "L2P_DFRAME" LOC = U22;
NET "L2P_DFRAME" IOSTANDARD = SSTL18_I;
NET "L2P_EDB" LOC = U20;
NET "L2P_EDB" IOSTANDARD = SSTL18_I;
NET "L2P_RDY" LOC = U19;
NET "L2P_RDY" IOSTANDARD = SSTL18_I;
NET "L2P_VALID" LOC = T18;
NET "L2P_VALID" IOSTANDARD = SSTL18_I;
NET "L_WR_RDY[0]" LOC = R20;
NET "L_WR_RDY[0]" IOSTANDARD = SSTL18_I;
NET "L_WR_RDY[1]" LOC = T22;
NET "L_WR_RDY[1]" IOSTANDARD = SSTL18_I;
NET "L_CLKn" LOC = N19;
NET "L_CLKn" IOSTANDARD = DIFF_SSTL18_I;
NET "L_CLKp" LOC = P20;
NET "L_CLKp" IOSTANDARD = DIFF_SSTL18_I;
NET "P2L_CLKn" LOC = M19;
NET "P2L_CLKn" IOSTANDARD = DIFF_SSTL18_I;
NET "P2L_CLKp" LOC = M20;
NET "P2L_CLKp" IOSTANDARD = DIFF_SSTL18_I;
NET "P2L_DFRAME" LOC = J22;
NET "P2L_DFRAME" IOSTANDARD = SSTL18_I;
NET "P2L_RDY" LOC = J16;
NET "P2L_RDY" IOSTANDARD = SSTL18_I;
NET "P2L_VALID" LOC = L19;
NET "P2L_VALID" IOSTANDARD = SSTL18_I;
NET "P_RD_D_RDY[0]" LOC = N16;
NET "P_RD_D_RDY[0]" IOSTANDARD = SSTL18_I;
NET "P_RD_D_RDY[1]" LOC = P19;
NET "P_RD_D_RDY[1]" IOSTANDARD = SSTL18_I;
NET "P_WR_RDY[0]" LOC = L15;
NET "P_WR_RDY[0]" IOSTANDARD = SSTL18_I;
NET "P_WR_RDY[1]" LOC = K16;
NET "P_WR_RDY[1]" IOSTANDARD = SSTL18_I;
NET "P_WR_REQ[0]" LOC = M22;
NET "P_WR_REQ[0]" IOSTANDARD = SSTL18_I;
NET "P_WR_REQ[1]" LOC = M21;
NET "P_WR_REQ[1]" IOSTANDARD = SSTL18_I;
NET "RX_ERROR" LOC = J17;
NET "RX_ERROR" IOSTANDARD = SSTL18_I;
NET "TX_ERROR" LOC = M17;
NET "TX_ERROR" IOSTANDARD = SSTL18_I;
NET "VC_RDY[0]" LOC = B21;
NET "VC_RDY[0]" IOSTANDARD = SSTL18_I;
NET "VC_RDY[1]" LOC = B22;
NET "VC_RDY[1]" IOSTANDARD = SSTL18_I;
NET "L2P_DATA[0]" LOC = P16;
NET "L2P_DATA[0]" IOSTANDARD = SSTL18_I;
NET "L2P_DATA[1]" LOC = P21;
NET "L2P_DATA[1]" IOSTANDARD = SSTL18_I;
NET "L2P_DATA[2]" LOC = P18;
NET "L2P_DATA[2]" IOSTANDARD = SSTL18_I;
NET "L2P_DATA[3]" LOC = T20;
NET "L2P_DATA[3]" IOSTANDARD = SSTL18_I;
NET "L2P_DATA[4]" LOC = V21;
NET "L2P_DATA[4]" IOSTANDARD = SSTL18_I;
NET "L2P_DATA[5]" LOC = V19;
NET "L2P_DATA[5]" IOSTANDARD = SSTL18_I;
NET "L2P_DATA[6]" LOC = W22;
NET "L2P_DATA[6]" IOSTANDARD = SSTL18_I;
NET "L2P_DATA[7]" LOC = Y22;
NET "L2P_DATA[7]" IOSTANDARD = SSTL18_I;
NET "L2P_DATA[8]" LOC = P22;
NET "L2P_DATA[8]" IOSTANDARD = SSTL18_I;
NET "L2P_DATA[9]" LOC = R22;
NET "L2P_DATA[9]" IOSTANDARD = SSTL18_I;
NET "L2P_DATA[10]" LOC = T21;
NET "L2P_DATA[10]" IOSTANDARD = SSTL18_I;
NET "L2P_DATA[11]" LOC = T19;
NET "L2P_DATA[11]" IOSTANDARD = SSTL18_I;
NET "L2P_DATA[12]" LOC = V22;
NET "L2P_DATA[12]" IOSTANDARD = SSTL18_I;
NET "L2P_DATA[13]" LOC = V20;
NET "L2P_DATA[13]" IOSTANDARD = SSTL18_I;
NET "L2P_DATA[14]" LOC = W20;
NET "L2P_DATA[14]" IOSTANDARD = SSTL18_I;
NET "L2P_DATA[15]" LOC = Y21;
NET "L2P_DATA[15]" IOSTANDARD = SSTL18_I;
NET "P2L_DATA[0]" LOC = K20;
NET "P2L_DATA[0]" IOSTANDARD = SSTL18_I;
NET "P2L_DATA[1]" LOC = H22;
NET "P2L_DATA[1]" IOSTANDARD = SSTL18_I;
NET "P2L_DATA[2]" LOC = H21;
NET "P2L_DATA[2]" IOSTANDARD = SSTL18_I;
NET "P2L_DATA[3]" LOC = L17;
NET "P2L_DATA[3]" IOSTANDARD = SSTL18_I;
NET "P2L_DATA[4]" LOC = K17;
NET "P2L_DATA[4]" IOSTANDARD = SSTL18_I;
NET "P2L_DATA[5]" LOC = G22;
NET "P2L_DATA[5]" IOSTANDARD = SSTL18_I;
NET "P2L_DATA[6]" LOC = G20;
NET "P2L_DATA[6]" IOSTANDARD = SSTL18_I;
NET "P2L_DATA[7]" LOC = K18;
NET "P2L_DATA[7]" IOSTANDARD = SSTL18_I;
NET "P2L_DATA[8]" LOC = K19;
NET "P2L_DATA[8]" IOSTANDARD = SSTL18_I;
NET "P2L_DATA[9]" LOC = H20;
NET "P2L_DATA[9]" IOSTANDARD = SSTL18_I;
NET "P2L_DATA[10]" LOC = J19;
NET "P2L_DATA[10]" IOSTANDARD = SSTL18_I;
NET "P2L_DATA[11]" LOC = E22;
NET "P2L_DATA[11]" IOSTANDARD = SSTL18_I;
NET "P2L_DATA[12]" LOC = E20;
NET "P2L_DATA[12]" IOSTANDARD = SSTL18_I;
NET "P2L_DATA[13]" LOC = F22;
NET "P2L_DATA[13]" IOSTANDARD = SSTL18_I;
NET "P2L_DATA[14]" LOC = F21;
NET "P2L_DATA[14]" IOSTANDARD = SSTL18_I;
NET "P2L_DATA[15]" LOC = H19;
NET "P2L_DATA[15]" IOSTANDARD = SSTL18_I;

NET "GPIO[0]" LOC = U16;
NET "GPIO[0]" IOSTANDARD = LVCMOS25;
NET "GPIO[1]" LOC = AB19;
NET "GPIO[1]" IOSTANDARD = LVCMOS25;

#----------------------------------------
# FMC slot
#----------------------------------------

NET "fmc0_prsnt_m2c_n_i" LOC = AB14;
NET "fmc0_prsnt_m2c_n_i" IOSTANDARD = LVCMOS25;

NET "fmc0_sys_scl_b" LOC = F7;
NET "fmc0_sys_sda_b" LOC = F8;
NET "fmc0_sys_scl_b" IOSTANDARD = LVCMOS25;
NET "fmc0_sys_sda_b" IOSTANDARD = LVCMOS25;

# double checked
NET "masterfip_speed_b[0]" LOC = Y5;
NET "masterfip_speed_b[0]" IOSTANDARD = LVCMOS25;
NET "masterfip_speed_b[1]" LOC = AB5;
NET "masterfip_speed_b[1]" IOSTANDARD = LVCMOS25;

NET "masterfip_adc_outa_p[*]" IOSTANDARD = LVDS_25;
NET "masterfip_adc_outa_n[*]" IOSTANDARD = LVDS_25;
NET "masterfip_adc_outb_p[*]" IOSTANDARD = LVDS_25;
NET "masterfip_adc_outb_n[*]" IOSTANDARD = LVDS_25;

# double checked
NET "masterfip_adc_outa_p[3]" LOC = U9;
NET "masterfip_adc_outa_n[3]" LOC = V9;

NET "masterfip_adc_outa_p[2]" LOC = AA8;
NET "masterfip_adc_outa_n[2]" LOC = AB8;

NET "masterfip_adc_outa_p[1]" LOC = W12;
NET "masterfip_adc_outa_n[1]" LOC = Y12;

NET "masterfip_adc_outa_p[0]" LOC = AA4;
NET "masterfip_adc_outa_n[0]" LOC = AB4;


NET "masterfip_adc_outb_p[3]" LOC = "AA6";
NET "masterfip_adc_outb_n[3]" LOC = "AB6";

NET "masterfip_adc_outb_n[2]" LOC = AB7;
NET "masterfip_adc_outb_p[2]" LOC = Y7;

NET "masterfip_adc_outb_p[1]" LOC = Y9;
NET "masterfip_adc_outb_n[1]" LOC = AB9;

NET "masterfip_adc_outb_n[0]" LOC = W11;
NET "masterfip_adc_outb_p[0]" LOC = V11;



# double checked
NET "masterfip_c2m_adc_clk_p" LOC = T12;
NET "masterfip_c2m_adc_clk_n" LOC = U12;

# double checked
# NET "masterfip_gbt_adc_clk_p" LOC = B6;
# NET "masterfip_gbt_adc_clk_n" LOC = A6;

# double checked
NET "masterfip_ext_sync_term_en" LOC = AB13;
NET "masterfip_ext_sync_term_en" IOSTANDARD = LVCMOS25;
NET "masterfip_ext_sync" LOC = T8;
NET "masterfip_ext_sync" IOSTANDARD = LVCMOS25;
NET "masterfip_ext_sync_tst_n" LOC = U8;
NET "masterfip_ext_sync_tst_n" IOSTANDARD = LVCMOS25;
NET "masterfip_ext_sync_oe_n" LOC = "W6";
NET "masterfip_ext_sync_oe_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_ext_sync_dir" LOC = Y6;
NET "masterfip_ext_sync_dir" IOSTANDARD = LVCMOS25;

# NET "masterfip_test_point[0]" LOC = AA16;
# NET "masterfip_test_point[0]" IOSTANDARD = LVCMOS25;
# NET "masterfip_test_point[1]" LOC = AB16;
# NET "masterfip_test_point[1]" IOSTANDARD = LVCMOS25;
# NET "masterfip_test_point[2]" LOC = Y17;
# NET "masterfip_test_point[2]" IOSTANDARD = LVCMOS25;
# NET "masterfip_test_point[3]" LOC = "AB17";
# NET "masterfip_test_point[3]" IOSTANDARD = "LVCMOS25";

# double checked
NET "masterfip_adc_fr_p" LOC = "AA12";
NET "masterfip_adc_fr_n" IOSTANDARD = LVDS_25;
NET "masterfip_adc_fr_n" LOC = "AB12";
NET "masterfip_adc_fr_p" IOSTANDARD = LVDS_25;
NET "masterfip_adc_dco_p" LOC = "Y11";
NET "masterfip_adc_dco_n" IOSTANDARD = LVDS_25;
NET "masterfip_adc_dco_n" LOC = "AB11";
NET "masterfip_adc_dco_p" IOSTANDARD = LVDS_25;
NET "masterfip_adc_cs_n" LOC = W14;
NET "masterfip_adc_cs_n" IOSTANDARD = LVCMOS25;
NET "masterfip_adc_sck" LOC = Y14;
NET "masterfip_adc_sck" IOSTANDARD = LVCMOS25;
NET "masterfip_adc_sdi" LOC = W15;
NET "masterfip_adc_sdi" IOSTANDARD = LVCMOS25;
NET "masterfip_adc_sdo" LOC = Y16;
NET "masterfip_adc_sdo" IOSTANDARD = LVCMOS25;

# double checked
NET "masterfip_1v8_shdn_n" LOC = V17;
NET "masterfip_1v8_shdn_n" IOSTANDARD = LVCMOS25;
NET "masterfip_m5v_shdn_n" LOC = W18;
NET "masterfip_m5v_shdn_n" IOSTANDARD = LVCMOS25;
NET "masterfip_5v_en_n" LOC = R8;
NET "masterfip_5v_en_n" IOSTANDARD = LVCMOS25;
NET "masterfip_prim_conn_n" LOC = V7;
NET "masterfip_prim_conn_n" IOSTANDARD = LVCMOS25;
NET "masterfip_sec_conn_n" LOC = W8;
NET "masterfip_sec_conn_n" IOSTANDARD = LVCMOS25;

# double checked
NET "masterfip_tx_err_led_n" LOC = C19;
NET "masterfip_tx_err_led_n" IOSTANDARD = LVCMOS25;
NET "masterfip_tx_act_led_n" LOC = A19;
NET "masterfip_tx_act_led_n" IOSTANDARD = LVCMOS25;
NET "masterfip_rx_err_led_n" LOC = B20;
NET "masterfip_rx_err_led_n" IOSTANDARD = LVCMOS25;
NET "masterfip_sync_led_n" LOC = W10;
NET "masterfip_sync_led_n" IOSTANDARD = LVCMOS25;
NET "masterfip_out_of_sync_led_n" LOC = "Y10";
NET "masterfip_out_of_sync_led_n" IOSTANDARD = "LVCMOS25";
NET "masterfip_rx_act_led_n" LOC = A20;
NET "masterfip_rx_act_led_n" IOSTANDARD = LVCMOS25;

# double checked
NET "masterfip_fd_wdg_n" LOC = R11;
NET "masterfip_fd_wdg_n" IOSTANDARD = LVCMOS25;
NET "masterfip_fd_txer" LOC = T11;
NET "masterfip_fd_txer" IOSTANDARD = LVCMOS25;
NET "masterfip_fd_txena" LOC = R13;
NET "masterfip_fd_txena" IOSTANDARD = LVCMOS25;
NET "masterfip_fd_txd" LOC = T14;
NET "masterfip_fd_txd" IOSTANDARD = LVCMOS25;
NET "masterfip_fd_cd_n" LOC = T15;
NET "masterfip_fd_cd_n" IOSTANDARD = LVCMOS25;
NET "masterfip_fd_rxd" LOC = U15;
NET "masterfip_fd_rxd" IOSTANDARD = LVCMOS25;
NET "masterfip_fd_txck" LOC = W17;
NET "masterfip_fd_txck" IOSTANDARD = LVCMOS25;
NET "masterfip_fd_rst_n" LOC = Y18;
NET "masterfip_fd_rst_n" IOSTANDARD = LVCMOS25;

# double checked
NET "masterfip_one_wire" LOC = "C18";
NET "masterfip_one_wire" IOSTANDARD = LVCMOS25;

NET "masterfip_si570_oe" LOC = AB15;
NET "masterfip_si570_oe" IOSTANDARD = LVCMOS25;
NET "masterfip_si570_sda" LOC = V13;
NET "masterfip_si570_sda" IOSTANDARD = LVCMOS25;
NET "masterfip_si570_scl" LOC = W13;
NET "masterfip_si570_scl" IOSTANDARD = LVCMOS25;



#----------------------------------------
# Carrier front panel LEDs
#----------------------------------------
NET "led_red_o" LOC = D5;
NET "led_red_o" IOSTANDARD = LVCMOS25;
NET "led_green_o" LOC = E5;
NET "led_green_o" IOSTANDARD = LVCMOS25;

#----------------------------------------
# PCB version number (coded with resistors)
#----------------------------------------
NET "pcb_ver_i[0]" LOC = P5;
NET "pcb_ver_i[0]" IOSTANDARD = LVCMOS15;
NET "pcb_ver_i[1]" LOC = P4;
NET "pcb_ver_i[1]" IOSTANDARD = LVCMOS15;
NET "pcb_ver_i[2]" LOC = AA2;
NET "pcb_ver_i[2]" IOSTANDARD = LVCMOS15;
NET "pcb_ver_i[3]" LOC = AA1;
NET "pcb_ver_i[3]" IOSTANDARD = LVCMOS15;

#----------------------------------------
# DDR3 interface
#----------------------------------------
NET "DDR3_CAS_N" LOC = M4;
NET "DDR3_CAS_N" IOSTANDARD = SSTL15_II;
NET "DDR3_CK_N" LOC = K3;
NET "DDR3_CK_N" IOSTANDARD = DIFF_SSTL15_II;
NET "DDR3_CK_P" LOC = K4;
NET "DDR3_CK_P" IOSTANDARD = DIFF_SSTL15_II;
NET "DDR3_CKE" LOC = F2;
NET "DDR3_CKE" IOSTANDARD = SSTL15_II;
NET "DDR3_LDM" LOC = N4;
NET "DDR3_LDM" IOSTANDARD = SSTL15_II;
NET "DDR3_LDQS_N" LOC = N1;
NET "DDR3_LDQS_N" IOSTANDARD = DIFF_SSTL15_II;
NET "DDR3_LDQS_P" LOC = N3;
NET "DDR3_LDQS_P" IOSTANDARD = DIFF_SSTL15_II;
NET "DDR3_ODT" LOC = L6;
NET "DDR3_ODT" IOSTANDARD = SSTL15_II;
NET "DDR3_RAS_N" LOC = M5;
NET "DDR3_RAS_N" IOSTANDARD = SSTL15_II;
NET "DDR3_RESET_N" LOC = E3;
NET "DDR3_RESET_N" IOSTANDARD = SSTL15_II;
NET "DDR3_UDM" LOC = P3;
NET "DDR3_UDM" IOSTANDARD = SSTL15_II;
NET "DDR3_UDQS_N" LOC = V1;
NET "DDR3_UDQS_N" IOSTANDARD = DIFF_SSTL15_II;
NET "DDR3_UDQS_P" LOC = V2;
NET "DDR3_UDQS_P" IOSTANDARD = DIFF_SSTL15_II;
NET "DDR3_WE_N" LOC = H2;
NET "DDR3_WE_N" IOSTANDARD = SSTL15_II;
NET "DDR3_RZQ" LOC = K7;
NET "DDR3_RZQ" IOSTANDARD = SSTL15_II;
NET "DDR3_ZIO" LOC = M7;
NET "DDR3_ZIO" IOSTANDARD = SSTL15_II;

NET "DDR3_A[0]" LOC = K2;
NET "DDR3_A[0]" IOSTANDARD = SSTL15_II;
NET "DDR3_A[1]" LOC = K1;
NET "DDR3_A[1]" IOSTANDARD = SSTL15_II;
NET "DDR3_A[2]" LOC = K5;
NET "DDR3_A[2]" IOSTANDARD = SSTL15_II;
NET "DDR3_A[3]" LOC = M6;
NET "DDR3_A[3]" IOSTANDARD = SSTL15_II;
NET "DDR3_A[4]" LOC = H3;
NET "DDR3_A[4]" IOSTANDARD = SSTL15_II;
NET "DDR3_A[5]" LOC = M3;
NET "DDR3_A[5]" IOSTANDARD = SSTL15_II;
NET "DDR3_A[6]" LOC = L4;
NET "DDR3_A[6]" IOSTANDARD = SSTL15_II;
NET "DDR3_A[7]" LOC = K6;
NET "DDR3_A[7]" IOSTANDARD = SSTL15_II;
NET "DDR3_A[8]" LOC = G3;
NET "DDR3_A[8]" IOSTANDARD = SSTL15_II;
NET "DDR3_A[9]" LOC = G1;
NET "DDR3_A[9]" IOSTANDARD = SSTL15_II;
NET "DDR3_A[10]" LOC = J4;
NET "DDR3_A[10]" IOSTANDARD = SSTL15_II;
NET "DDR3_A[11]" LOC = E1;
NET "DDR3_A[11]" IOSTANDARD = SSTL15_II;
NET "DDR3_A[12]" LOC = F1;
NET "DDR3_A[12]" IOSTANDARD = SSTL15_II;
NET "DDR3_A[13]" LOC = J6;
NET "DDR3_A[13]" IOSTANDARD = SSTL15_II;
#NET "DDR3_A[14]" LOC = H5;
#NET "DDR3_A[14]" IOSTANDARD = "SSTL15_II";
NET "DDR3_BA[0]" LOC = J3;
NET "DDR3_BA[0]" IOSTANDARD = SSTL15_II;
NET "DDR3_BA[1]" LOC = J1;
NET "DDR3_BA[1]" IOSTANDARD = SSTL15_II;
NET "DDR3_BA[2]" LOC = H1;
NET "DDR3_BA[2]" IOSTANDARD = SSTL15_II;
NET "DDR3_DQ[0]" LOC = R3;
NET "DDR3_DQ[0]" IOSTANDARD = SSTL15_II;
NET "DDR3_DQ[1]" LOC = R1;
NET "DDR3_DQ[1]" IOSTANDARD = SSTL15_II;
NET "DDR3_DQ[2]" LOC = P2;
NET "DDR3_DQ[2]" IOSTANDARD = SSTL15_II;
NET "DDR3_DQ[3]" LOC = P1;
NET "DDR3_DQ[3]" IOSTANDARD = SSTL15_II;
NET "DDR3_DQ[4]" LOC = L3;
NET "DDR3_DQ[4]" IOSTANDARD = SSTL15_II;
NET "DDR3_DQ[5]" LOC = L1;
NET "DDR3_DQ[5]" IOSTANDARD = SSTL15_II;
NET "DDR3_DQ[6]" LOC = M2;
NET "DDR3_DQ[6]" IOSTANDARD = SSTL15_II;
NET "DDR3_DQ[7]" LOC = M1;
NET "DDR3_DQ[7]" IOSTANDARD = SSTL15_II;
NET "DDR3_DQ[8]" LOC = T2;
NET "DDR3_DQ[8]" IOSTANDARD = SSTL15_II;
NET "DDR3_DQ[9]" LOC = T1;
NET "DDR3_DQ[9]" IOSTANDARD = SSTL15_II;
NET "DDR3_DQ[10]" LOC = U3;
NET "DDR3_DQ[10]" IOSTANDARD = SSTL15_II;
NET "DDR3_DQ[11]" LOC = U1;
NET "DDR3_DQ[11]" IOSTANDARD = SSTL15_II;
NET "DDR3_DQ[12]" LOC = W3;
NET "DDR3_DQ[12]" IOSTANDARD = SSTL15_II;
NET "DDR3_DQ[13]" LOC = W1;
NET "DDR3_DQ[13]" IOSTANDARD = SSTL15_II;
NET "DDR3_DQ[14]" LOC = Y2;
NET "DDR3_DQ[14]" IOSTANDARD = SSTL15_II;
NET "DDR3_DQ[15]" LOC = Y1;
NET "DDR3_DQ[15]" IOSTANDARD = SSTL15_II;

#----------------------------------------
# UART
#----------------------------------------
#NET "UART_TXD" LOC = A2; # FPGA input
#NET "UART_TXD" IOSTANDARD = "LVCMOS25";
#NET "UART_RXD" LOC = B2; # FPGA output
#NET "UART_RXD" IOSTANDARD = "LVCMOS25";

#----------------------------------------
# Buttons and LEDs
#----------------------------------------
NET "aux_buttons_i[0]" LOC = C22;
NET "aux_buttons_i[0]" IOSTANDARD = LVCMOS18;
NET "aux_buttons_i[1]" LOC = D21;
NET "aux_buttons_i[1]" IOSTANDARD = LVCMOS18;
NET "aux_leds_o[0]" LOC = G19;
NET "aux_leds_o[0]" IOSTANDARD = LVCMOS18;
NET "aux_leds_o[1]" LOC = F20;
NET "aux_leds_o[1]" IOSTANDARD = LVCMOS18;
NET "aux_leds_o[2]" LOC = F18;
NET "aux_leds_o[2]" IOSTANDARD = LVCMOS18;
NET "aux_leds_o[3]" LOC = C20;
NET "aux_leds_o[3]" IOSTANDARD = LVCMOS18;


#===============================================================================
# IOBs
#===============================================================================
INST "cmp_gn4124_core/l2p_rdy_t" IOB =FALSE;
INST "cmp_gn4124_core/l_wr_rdy_t_1" IOB =FALSE;
INST "cmp_gn4124_core/l_wr_rdy_t_0" IOB =FALSE;
INST "cmp_gn4124_core/l_wr_rdy_t2_1" IOB =FALSE;
INST "cmp_gn4124_core/l_wr_rdy_t2_0" IOB =FALSE;


#===============================================================================
# Terminations
#===============================================================================

# DDR3

NET "DDR3_DQ[0]" IN_TERM = NONE;
NET "DDR3_DQ[10]" IN_TERM = NONE;
NET "DDR3_DQ[11]" IN_TERM = NONE;
NET "DDR3_DQ[12]" IN_TERM = NONE;
NET "DDR3_DQ[13]" IN_TERM = NONE;
NET "DDR3_DQ[14]" IN_TERM = NONE;
NET "DDR3_DQ[15]" IN_TERM = NONE;
NET "DDR3_DQ[1]" IN_TERM = NONE;
NET "DDR3_DQ[2]" IN_TERM = NONE;
NET "DDR3_DQ[3]" IN_TERM = NONE;
NET "DDR3_DQ[4]" IN_TERM = NONE;
NET "DDR3_DQ[5]" IN_TERM = NONE;
NET "DDR3_DQ[6]" IN_TERM = NONE;
NET "DDR3_DQ[7]" IN_TERM = NONE;
NET "DDR3_DQ[8]" IN_TERM = NONE;
NET "DDR3_DQ[9]" IN_TERM = NONE;
NET "DDR3_LDQS_P" IN_TERM = NONE;
NET "DDR3_LDQS_N" IN_TERM = NONE;
NET "DDR3_UDQS_P" IN_TERM = NONE;
NET "DDR3_UDQS_N" IN_TERM = NONE;


#===============================================================================
# Timing constraints
#===============================================================================

# GN4124

#NET "L_CLKp" TNM_NET = "l_clkp_grp";
#TIMESPEC TS_l_clkp = PERIOD "l_clkp_grp" 5 ns HIGH 50%;
NET "P2L_CLKp" TNM_NET = "p2l_clkp_grp";
TIMESPEC TS_p2l_clkp = PERIOD "p2l_clkp_grp" 5 ns HIGH 50 %;
NET "P2L_CLKn" TNM_NET = "p2l_clkn_grp";
TIMESPEC TS_p2l_clkn = PERIOD "p2l_clkn_grp" 5 ns HIGH 50 %;

NET "L2P_CLKN" TNM = "gn4124_data_bus_out";
NET "L2P_CLKP" TNM = "gn4124_data_bus_out";
NET "L2P_VALID" TNM = "gn4124_data_bus_out";
NET "L2P_DFRAME" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[0]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[1]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[2]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[3]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[4]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[5]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[6]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[7]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[8]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[9]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[10]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[11]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[12]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[13]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[14]" TNM = "gn4124_data_bus_out";
NET "L2P_DATA[15]" TNM = "gn4124_data_bus_out";

#TIMEGRP "gn4124_data_bus_out" OFFSET = OUT AFTER "cmp_gn4124_core/io_clk" REFERENCE_PIN "L2P_CLKP";

NET "P2L_CLKN" TNM = "gn4124_data_bus_in";
NET "P2L_CLKP" TNM = "gn4124_data_bus_in";
NET "P2L_DFRAME" TNM = "gn4124_data_bus_in";
NET "P2L_VALID" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[0]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[1]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[2]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[3]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[4]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[5]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[6]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[7]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[8]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[9]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[10]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[11]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[12]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[13]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[14]" TNM = "gn4124_data_bus_in";
NET "P2L_DATA[15]" TNM = "gn4124_data_bus_in";

#TIMEGRP "gn4124_data_bus_in" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE "cmp_gn4124_core/io_clk" RISING;
#TIMEGRP "gn4124_data_bus_in" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE "cmp_gn4124_core/io_clk" FALLING;


# System clock

NET "clk20_vcxo_i" TNM_NET = "clk20_vcxo_i_grp";
TIMESPEC TS_clk20_vcxo_i = PERIOD "clk20_vcxo_i_grp" 50 ns HIGH 50 %;

# DDR3

NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK5";
TIMESPEC TS_SYS_CLK5 = PERIOD "SYS_CLK5" 3 ns HIGH 50 %;

# ADC
NET "masterfip_adc_dco_p" TNM_NET = adc_dco_n_i;
TIMESPEC TS_adc_dco_n_i = PERIOD "masterfip_adc_dco_p" 2 ns HIGH 50 %;

#===============================================================================
# False Path
#===============================================================================

# GN4124

NET "l_rst_n" TIG;
NET "cmp_gn4124_core/rst_*" TIG;

# DDR3

NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/c3_pll_lock" TIG;
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/hard_done_cal" TIG;
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;

# Reset
NET "powerup_rst_n" TIG;
NET "sw_rst_fmc0_n" TIG;


# PlanAhead Generated IO constraints 


PIN "cmp_adc_clk_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; 