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-- Title          : Wishbone slave core for FMC masterFIP core registers
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-- File           : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_csr.vhd
-- Author         : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/ip_cores/gw-masterfip/rtl/wbgen/masterfip_csr.wb
-- Created        : Mon Apr 24 10:20:14 2017
-- Standard       : VHDL'87
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-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/ip_cores/gw-masterfip/rtl/wbgen/masterfip_csr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity masterfip_wbgen2_csr is
    port (
        rst_n_i                                  : in     std_logic;
        clk_sys_i                                : in     std_logic;
        wb_adr_i                                 : in     std_logic_vector(7 downto 0);
        wb_dat_i                                 : in     std_logic_vector(31 downto 0);
        wb_dat_o                                 : out    std_logic_vector(31 downto 0);
        wb_cyc_i                                 : in     std_logic;
        wb_sel_i                                 : in     std_logic_vector(3 downto 0);
        wb_stb_i                                 : in     std_logic;
        wb_we_i                                  : in     std_logic;
        wb_ack_o                                 : out    std_logic;
        wb_stall_o                               : out    std_logic;
-- Port for MONOSTABLE field: 'reset of the masterFIP core' in reg: 'rst'
        masterfip_rst_core_o                     : out    std_logic;
-- Port for MONOSTABLE field: 'reset of the FielDrive chip' in reg: 'rst'
        masterfip_rst_fd_o                       : out    std_logic;
-- Port for BIT field: 'rx act green led' in reg: 'leds and debug'
        masterfip_led_rx_act_o                   : out    std_logic;
-- Port for BIT field: 'rx err red led' in reg: 'leds and debug'
        masterfip_led_rx_err_o                   : out    std_logic;
-- Port for BIT field: 'tx act green led' in reg: 'leds and debug'
        masterfip_led_tx_act_o                   : out    std_logic;
-- Port for BIT field: 'tx err red led' in reg: 'leds and debug'
        masterfip_led_tx_err_o                   : out    std_logic;
-- Port for BIT field: 'ext sync act green led' in reg: 'leds and debug'
        masterfip_led_ext_sync_act_o             : out    std_logic;
-- Port for BIT field: 'ext sync err red led' in reg: 'leds and debug'
        masterfip_led_ext_sync_err_o             : out    std_logic;
-- Port for std_logic_vector field: 'dbg' in reg: 'leds and debug'
        masterfip_led_dbg_o                      : out    std_logic_vector(23 downto 0);
-- Port for std_logic_vector field: 'ds1820 temperature' in reg: 'fmc temperature'
        masterfip_ds1820_temper_i                : in     std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'ds1820 id lsb' in reg: 'fmc unique id lsb'
        masterfip_ds1820_id_lsb_i                : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'ds1820 id msb' in reg: 'fmc unique id msb'
        masterfip_ds1820_id_msb_i                : in     std_logic_vector(31 downto 0);
-- Port for BIT field: 'termination enable' in reg: 'ext sync ctrl'
        masterfip_ext_sync_ctrl_term_en_o        : out    std_logic;
-- Port for BIT field: 'transceiver direction' in reg: 'ext sync ctrl'
        masterfip_ext_sync_ctrl_dir_o            : out    std_logic;
-- Port for BIT field: 'transceiver output enable negative logic' in reg: 'ext sync ctrl'
        masterfip_ext_sync_ctrl_oe_n_o           : out    std_logic;
-- Port for BIT field: 'pulses counter reset' in reg: 'ext sync ctrl'
        masterfip_ext_sync_ctrl_p_cnt_rst_o      : out    std_logic;
-- Port for BIT field: 'counting options' in reg: 'ext sync ctrl'
        masterfip_ext_sync_ctrl_opt_o            : out    std_logic;
-- Port for BIT field: 'safe window' in reg: 'ext sync ctrl'
        masterfip_ext_sync_ctrl_safe_wind_o      : out    std_logic;
-- Port for std_logic_vector field: 'ext_sync_p_cnt' in reg: 'ext sync pulses cnt'
        masterfip_ext_sync_p_cnt_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'WorldFIP speed, hard-wired on the FMC' in reg: 'bus speed'
        masterfip_speed_i                        : in     std_logic_vector(1 downto 0);
-- Port for std_logic_vector field: 'macrocycle lgth' in reg: 'macrocycle lgth'
        masterfip_macrocyc_lgth_o                : out    std_logic_vector(30 downto 0);
-- Port for MONOSTABLE field: 'macrocycle cnt start' in reg: 'macrocycle lgth'
        masterfip_macrocyc_start_o               : out    std_logic;
-- Port for std_logic_vector field: 'macrocycle time counter' in reg: 'macrocycle time cnt'
        masterfip_macrocyc_time_cnt_i            : in     std_logic_vector(30 downto 0);
-- Port for std_logic_vector field: 'number of macrocycles' in reg: 'macrocycles number cnt'
        masterfip_macrocyc_num_cnt_i             : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'turnaround time' in reg: 'turnaround lgth'
        masterfip_turnar_lgth_o                  : out    std_logic_vector(30 downto 0);
-- Port for MONOSTABLE field: 'turnaround cnt start' in reg: 'turnaround lgth'
        masterfip_turnar_start_o                 : out    std_logic;
-- Port for std_logic_vector field: 'turnaround time counter' in reg: 'turnaround time cnt'
        masterfip_turnar_time_cnt_i              : in     std_logic_vector(30 downto 0);
-- Port for std_logic_vector field: 'silence time' in reg: 'silence lgth'
        masterfip_silen_lgth_o                   : out    std_logic_vector(30 downto 0);
-- Port for MONOSTABLE field: 'silence cnt start' in reg: 'silence lgth'
        masterfip_silen_start_o                  : out    std_logic;
-- Port for std_logic_vector field: 'silence time counter' in reg: 'silence time cnt'
        masterfip_silen_time_cnt_i               : in     std_logic_vector(30 downto 0);
-- Port for MONOSTABLE field: 'tx rst' in reg: 'tx ctrl'
        masterfip_tx_ctrl_rst_o                  : out    std_logic;
-- Port for MONOSTABLE field: 'tx strt' in reg: 'tx ctrl'
        masterfip_tx_ctrl_start_o                : out    std_logic;
-- Port for std_logic_vector field: 'tx number of bytes' in reg: 'tx ctrl'
        masterfip_tx_ctrl_bytes_num_o            : out    std_logic_vector(15 downto 0);
-- Port for BIT field: 'tx ended' in reg: 'tx status'
        masterfip_tx_stat_stop_i                 : in     std_logic;
-- Port for BIT field: 'tx enable' in reg: 'tx status'
        masterfip_tx_stat_ena_i                  : in     std_logic;
-- Port for std_logic_vector field: 'tx status current byte index' in reg: 'tx status'
        masterfip_tx_stat_curr_byte_indx_i       : in     std_logic_vector(15 downto 0);
-- Port for BIT field: 'FielDrive watchdog' in reg: 'FielDrive wdgn, cdn'
        masterfip_fd_wdg_i                       : in     std_logic;
-- Port for BIT field: 'FielDrive carrier detect' in reg: 'FielDrive wdgn, cdn'
        masterfip_fd_cd_i                        : in     std_logic;
-- Port for std_logic_vector field: 'fd_wdgn_tstamp' in reg: 'FielDrive wdg timestamp'
        masterfip_fd_wdg_tstamp_i                : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'fd_txer_cnt' in reg: 'FielDrive txer cnt'
        masterfip_fd_txer_cnt_i                  : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'fd_txer_tstamp' in reg: 'FielDrive txer tstamp'
        masterfip_fd_txer_tstamp_i               : in     std_logic_vector(31 downto 0);
-- Port for MONOSTABLE field: 'rx rst' in reg: 'rx ctrl'
        masterfip_rx_ctrl_rst_o                  : out    std_logic;
-- Port for BIT field: 'rx Preamble(FSS) detected' in reg: 'rx status'
        masterfip_rx_stat_pream_ok_i             : in     std_logic;
-- Port for BIT field: 'rx frame ok' in reg: 'rx status'
        masterfip_rx_stat_frame_ok_i             : in     std_logic;
-- Port for BIT field: 'rx frame crc error' in reg: 'rx status'
        masterfip_rx_stat_frame_crc_err_i        : in     std_logic;
-- Port for std_logic_vector field: 'rx number of payload bytes' in reg: 'rx status'
        masterfip_rx_stat_bytes_num_i            : in     std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'current word index' in reg: 'rx current word index'
        masterfip_rx_stat_curr_word_indx_i       : in     std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'rx number of frames with CRC error' in reg: 'rx num of frames with CRC error'
        masterfip_rx_stat_crc_err_cnt_i          : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'rx payload ctrl byte' in reg: 'rx payload ctrl byte'
        masterfip_rx_payld_ctrl_i                : in     std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'reg 1' in reg: 'rx payload reg1'
        masterfip_rx_payld_reg1_i                : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg2' in reg: 'rx payload reg2'
        masterfip_rx_payld_reg2_i                : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg3' in reg: 'rx payload reg3'
        masterfip_rx_payld_reg3_i                : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg4' in reg: 'rx payload reg4'
        masterfip_rx_payld_reg4_i                : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg5' in reg: 'rx payload reg5'
        masterfip_rx_payld_reg5_i                : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg6' in reg: 'rx payload reg6'
        masterfip_rx_payld_reg6_i                : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg7' in reg: 'rx payload reg7'
        masterfip_rx_payld_reg7_i                : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg8' in reg: 'rx payload reg8'
        masterfip_rx_payld_reg8_i                : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg9' in reg: 'rx payload reg9'
        masterfip_rx_payld_reg9_i                : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg10' in reg: 'rx payload reg10'
        masterfip_rx_payld_reg10_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg11' in reg: 'rx payload reg11'
        masterfip_rx_payld_reg11_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg12' in reg: 'rx payload reg12'
        masterfip_rx_payld_reg12_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg13' in reg: 'rx payload reg13'
        masterfip_rx_payld_reg13_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg14' in reg: 'rx payload reg14'
        masterfip_rx_payld_reg14_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg15' in reg: 'rx payload reg15'
        masterfip_rx_payld_reg15_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg16' in reg: 'rx payload reg16'
        masterfip_rx_payld_reg16_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg17' in reg: 'rx payload reg17'
        masterfip_rx_payld_reg17_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg18' in reg: 'rx payload reg18'
        masterfip_rx_payld_reg18_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg19' in reg: 'rx payload reg19'
        masterfip_rx_payld_reg19_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg20' in reg: 'rx payload reg20'
        masterfip_rx_payld_reg20_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg21' in reg: 'rx payload reg21'
        masterfip_rx_payld_reg21_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg22' in reg: 'rx payload reg22'
        masterfip_rx_payld_reg22_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg23' in reg: 'rx payload reg23'
        masterfip_rx_payld_reg23_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg24' in reg: 'rx payload reg24'
        masterfip_rx_payld_reg24_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg25' in reg: 'rx payload reg25'
        masterfip_rx_payld_reg25_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg26' in reg: 'rx payload reg26'
        masterfip_rx_payld_reg26_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg27' in reg: 'rx payload reg27'
        masterfip_rx_payld_reg27_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg28' in reg: 'rx payload reg28'
        masterfip_rx_payld_reg28_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg29' in reg: 'rx payload reg29'
        masterfip_rx_payld_reg29_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg30' in reg: 'rx payload reg30'
        masterfip_rx_payld_reg30_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg31' in reg: 'rx payload reg31'
        masterfip_rx_payld_reg31_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg32' in reg: 'rx payload reg32'
        masterfip_rx_payld_reg32_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg 33' in reg: 'rx payload reg33'
        masterfip_rx_payld_reg33_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg34' in reg: 'rx payload reg34'
        masterfip_rx_payld_reg34_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg35' in reg: 'rx payload reg35'
        masterfip_rx_payld_reg35_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg36' in reg: 'rx payload reg36'
        masterfip_rx_payld_reg36_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg37' in reg: 'rx payload reg37'
        masterfip_rx_payld_reg37_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg38' in reg: 'rx payload reg38'
        masterfip_rx_payld_reg38_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg39' in reg: 'rx payload reg39'
        masterfip_rx_payld_reg39_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg40' in reg: 'rx payload reg40'
        masterfip_rx_payld_reg40_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg41' in reg: 'rx payload reg41'
        masterfip_rx_payld_reg41_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg42' in reg: 'rx payload reg42'
        masterfip_rx_payld_reg42_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg43' in reg: 'rx payload reg43'
        masterfip_rx_payld_reg43_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg44' in reg: 'rx payload reg44'
        masterfip_rx_payld_reg44_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg45' in reg: 'rx payload reg45'
        masterfip_rx_payld_reg45_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg46' in reg: 'rx payload reg46'
        masterfip_rx_payld_reg46_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg47' in reg: 'rx payload reg47'
        masterfip_rx_payld_reg47_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg48' in reg: 'rx payload reg48'
        masterfip_rx_payld_reg48_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg49' in reg: 'rx payload reg49'
        masterfip_rx_payld_reg49_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg50' in reg: 'rx payload reg50'
        masterfip_rx_payld_reg50_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg51' in reg: 'rx payload reg51'
        masterfip_rx_payld_reg51_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg52' in reg: 'rx payload reg52'
        masterfip_rx_payld_reg52_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg53' in reg: 'rx payload reg53'
        masterfip_rx_payld_reg53_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg54' in reg: 'rx payload reg54'
        masterfip_rx_payld_reg54_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg55' in reg: 'rx payload reg55'
        masterfip_rx_payld_reg55_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg56' in reg: 'rx payload reg56'
        masterfip_rx_payld_reg56_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg57' in reg: 'rx payload reg57'
        masterfip_rx_payld_reg57_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg58' in reg: 'rx payload reg58'
        masterfip_rx_payld_reg58_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg59' in reg: 'rx payload reg59'
        masterfip_rx_payld_reg59_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg60' in reg: 'rx payload reg60'
        masterfip_rx_payld_reg60_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg61' in reg: 'rx payload reg61'
        masterfip_rx_payld_reg61_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg62' in reg: 'rx payload reg62'
        masterfip_rx_payld_reg62_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg63' in reg: 'rx payload reg63'
        masterfip_rx_payld_reg63_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg64' in reg: 'rx payload reg64'
        masterfip_rx_payld_reg64_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg65' in reg: 'rx payload reg65'
        masterfip_rx_payld_reg65_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg66' in reg: 'rx payload reg66'
        masterfip_rx_payld_reg66_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg67' in reg: 'rx payload reg67'
        masterfip_rx_payld_reg67_i               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'tx ctrl byte' in reg: 'tx ctrl byte'
        masterfip_tx_payld_ctrl_o                : out    std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'reg1' in reg: 'tx payload reg1'
        masterfip_tx_payld_reg1_o                : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg2' in reg: 'tx payload reg2'
        masterfip_tx_payld_reg2_o                : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg3' in reg: 'tx payload reg3'
        masterfip_tx_payld_reg3_o                : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg4' in reg: 'tx payload reg4'
        masterfip_tx_payld_reg4_o                : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg5' in reg: 'tx payload reg5'
        masterfip_tx_payld_reg5_o                : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg6' in reg: 'tx payload reg6'
        masterfip_tx_payld_reg6_o                : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg7' in reg: 'tx payload reg7'
        masterfip_tx_payld_reg7_o                : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg8' in reg: 'tx payload reg8'
        masterfip_tx_payld_reg8_o                : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg9' in reg: 'tx payload reg9'
        masterfip_tx_payld_reg9_o                : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg10' in reg: 'tx payload reg10'
        masterfip_tx_payld_reg10_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg11' in reg: 'tx payload reg11'
        masterfip_tx_payld_reg11_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg12' in reg: 'tx payload reg12'
        masterfip_tx_payld_reg12_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg13' in reg: 'tx payload reg13'
        masterfip_tx_payld_reg13_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg14' in reg: 'tx payload reg14'
        masterfip_tx_payld_reg14_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg15' in reg: 'tx payload reg15'
        masterfip_tx_payld_reg15_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg16' in reg: 'tx payload reg16'
        masterfip_tx_payld_reg16_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg17' in reg: 'tx payload reg17'
        masterfip_tx_payld_reg17_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg18' in reg: 'tx payload reg18'
        masterfip_tx_payld_reg18_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg19' in reg: 'tx payload reg19'
        masterfip_tx_payld_reg19_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg20' in reg: 'tx payload reg20'
        masterfip_tx_payld_reg20_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg21' in reg: 'tx payload reg21'
        masterfip_tx_payld_reg21_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg22' in reg: 'tx payload reg22'
        masterfip_tx_payld_reg22_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg23' in reg: 'tx payload reg23'
        masterfip_tx_payld_reg23_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg24' in reg: 'tx payload reg24'
        masterfip_tx_payld_reg24_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg25' in reg: 'tx payload reg25'
        masterfip_tx_payld_reg25_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg26' in reg: 'tx payload reg26'
        masterfip_tx_payld_reg26_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg27' in reg: 'tx payload reg27'
        masterfip_tx_payld_reg27_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg28' in reg: 'tx payload reg28'
        masterfip_tx_payld_reg28_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg29' in reg: 'tx payload reg29'
        masterfip_tx_payld_reg29_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg30' in reg: 'tx payload reg30'
        masterfip_tx_payld_reg30_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg31' in reg: 'tx payload reg31'
        masterfip_tx_payld_reg31_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg32' in reg: 'tx payload reg32'
        masterfip_tx_payld_reg32_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg 33' in reg: 'tx payload reg33'
        masterfip_tx_payld_reg33_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg34' in reg: 'tx payload reg34'
        masterfip_tx_payld_reg34_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg35' in reg: 'tx payload reg35'
        masterfip_tx_payld_reg35_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg36' in reg: 'tx payload reg36'
        masterfip_tx_payld_reg36_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg37' in reg: 'tx payload reg37'
        masterfip_tx_payld_reg37_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg38' in reg: 'tx payload reg38'
        masterfip_tx_payld_reg38_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg39' in reg: 'tx payload reg39'
        masterfip_tx_payld_reg39_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg40' in reg: 'tx payload reg40'
        masterfip_tx_payld_reg40_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg41' in reg: 'tx payload reg41'
        masterfip_tx_payld_reg41_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg42' in reg: 'tx payload reg42'
        masterfip_tx_payld_reg42_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg43' in reg: 'tx payload reg43'
        masterfip_tx_payld_reg43_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg44' in reg: 'tx payload reg44'
        masterfip_tx_payld_reg44_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg45' in reg: 'tx payload reg45'
        masterfip_tx_payld_reg45_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg46' in reg: 'tx payload reg46'
        masterfip_tx_payld_reg46_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg47' in reg: 'tx payload reg47'
        masterfip_tx_payld_reg47_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg48' in reg: 'tx payload reg48'
        masterfip_tx_payld_reg48_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg49' in reg: 'tx payload reg49'
        masterfip_tx_payld_reg49_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg50' in reg: 'tx payload reg50'
        masterfip_tx_payld_reg50_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg51' in reg: 'tx payload reg51'
        masterfip_tx_payld_reg51_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg52' in reg: 'tx payload reg52'
        masterfip_tx_payld_reg52_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg53' in reg: 'tx payload reg53'
        masterfip_tx_payld_reg53_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg54' in reg: 'tx payload reg54'
        masterfip_tx_payld_reg54_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg55' in reg: 'tx payload reg55'
        masterfip_tx_payld_reg55_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg56' in reg: 'tx payload reg56'
        masterfip_tx_payld_reg56_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg57' in reg: 'tx payload reg57'
        masterfip_tx_payld_reg57_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg58' in reg: 'tx payload reg58'
        masterfip_tx_payld_reg58_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg59' in reg: 'tx payload reg59'
        masterfip_tx_payld_reg59_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg60' in reg: 'tx payload reg60'
        masterfip_tx_payld_reg60_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg61' in reg: 'tx payload reg61'
        masterfip_tx_payld_reg61_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg62' in reg: 'tx payload reg62'
        masterfip_tx_payld_reg62_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg63' in reg: 'tx payload reg63'
        masterfip_tx_payld_reg63_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg64' in reg: 'tx payload reg64'
        masterfip_tx_payld_reg64_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg65' in reg: 'tx payload reg65'
        masterfip_tx_payld_reg65_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg66' in reg: 'tx payload reg66'
        masterfip_tx_payld_reg66_o               : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg67' in reg: 'tx payload reg67'
        masterfip_tx_payld_reg67_o               : out    std_logic_vector(31 downto 0)
    );
end masterfip_wbgen2_csr;

architecture syn of masterfip_wbgen2_csr is

signal masterfip_rst_core_dly0                  : std_logic      ;
signal masterfip_rst_core_int                   : std_logic      ;
signal masterfip_rst_fd_dly0                    : std_logic      ;
signal masterfip_rst_fd_int                     : std_logic      ;
signal masterfip_led_rx_act_int                 : std_logic      ;
signal masterfip_led_rx_err_int                 : std_logic      ;
signal masterfip_led_tx_act_int                 : std_logic      ;
signal masterfip_led_tx_err_int                 : std_logic      ;
signal masterfip_led_ext_sync_act_int           : std_logic      ;
signal masterfip_led_ext_sync_err_int           : std_logic      ;
signal masterfip_led_dbg_int                    : std_logic_vector(23 downto 0);
signal masterfip_ext_sync_ctrl_term_en_int      : std_logic      ;
signal masterfip_ext_sync_ctrl_dir_int          : std_logic      ;
signal masterfip_ext_sync_ctrl_oe_n_int         : std_logic      ;
signal masterfip_ext_sync_ctrl_p_cnt_rst_int    : std_logic      ;
signal masterfip_ext_sync_ctrl_opt_int          : std_logic      ;
signal masterfip_ext_sync_ctrl_safe_wind_int    : std_logic      ;
signal masterfip_macrocyc_lgth_int              : std_logic_vector(30 downto 0);
signal masterfip_macrocyc_start_dly0            : std_logic      ;
signal masterfip_macrocyc_start_int             : std_logic      ;
signal masterfip_turnar_lgth_int                : std_logic_vector(30 downto 0);
signal masterfip_turnar_start_dly0              : std_logic      ;
signal masterfip_turnar_start_int               : std_logic      ;
signal masterfip_silen_lgth_int                 : std_logic_vector(30 downto 0);
signal masterfip_silen_start_dly0               : std_logic      ;
signal masterfip_silen_start_int                : std_logic      ;
signal masterfip_tx_ctrl_rst_dly0               : std_logic      ;
signal masterfip_tx_ctrl_rst_int                : std_logic      ;
signal masterfip_tx_ctrl_start_dly0             : std_logic      ;
signal masterfip_tx_ctrl_start_int              : std_logic      ;
signal masterfip_tx_ctrl_bytes_num_int          : std_logic_vector(15 downto 0);
signal masterfip_rx_ctrl_rst_dly0               : std_logic      ;
signal masterfip_rx_ctrl_rst_int                : std_logic      ;
signal masterfip_tx_payld_ctrl_int              : std_logic_vector(7 downto 0);
signal masterfip_tx_payld_reg1_int              : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg2_int              : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg3_int              : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg4_int              : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg5_int              : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg6_int              : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg7_int              : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg8_int              : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg9_int              : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg10_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg11_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg12_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg13_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg14_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg15_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg16_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg17_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg18_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg19_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg20_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg21_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg22_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg23_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg24_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg25_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg26_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg27_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg28_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg29_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg30_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg31_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg32_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg33_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg34_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg35_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg36_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg37_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg38_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg39_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg40_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg41_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg42_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg43_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg44_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg45_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg46_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg47_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg48_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg49_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg50_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg51_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg52_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg53_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg54_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg55_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg56_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg57_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg58_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg59_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg60_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg61_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg62_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg63_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg64_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg65_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg66_int             : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg67_int             : std_logic_vector(31 downto 0);
signal ack_sreg                                 : std_logic_vector(9 downto 0);
signal rddata_reg                               : std_logic_vector(31 downto 0);
signal wrdata_reg                               : std_logic_vector(31 downto 0);
signal bwsel_reg                                : std_logic_vector(3 downto 0);
signal rwaddr_reg                               : std_logic_vector(7 downto 0);
signal ack_in_progress                          : std_logic      ;
signal wr_int                                   : std_logic      ;
signal rd_int                                   : std_logic      ;
signal allones                                  : std_logic_vector(31 downto 0);
signal allzeros                                 : std_logic_vector(31 downto 0);

begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
    wrdata_reg <= wb_dat_i;
    bwsel_reg <= wb_sel_i;
    rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
    wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
    allones <= (others => '1');
    allzeros <= (others => '0');
-- 
-- Main register bank access process.
    process (clk_sys_i, rst_n_i)
    begin
        if (rst_n_i = '0') then 
            ack_sreg <= "0000000000";
            ack_in_progress <= '0';
            rddata_reg <= "00000000000000000000000000000000";
            masterfip_rst_core_int <= '0';
            masterfip_rst_fd_int <= '0';
            masterfip_led_rx_act_int <= '0';
            masterfip_led_rx_err_int <= '0';
            masterfip_led_tx_act_int <= '0';
            masterfip_led_tx_err_int <= '0';
            masterfip_led_ext_sync_act_int <= '0';
            masterfip_led_ext_sync_err_int <= '0';
            masterfip_led_dbg_int <= "000000000000000000000000";
            masterfip_ext_sync_ctrl_term_en_int <= '0';
            masterfip_ext_sync_ctrl_dir_int <= '0';
            masterfip_ext_sync_ctrl_oe_n_int <= '0';
            masterfip_ext_sync_ctrl_p_cnt_rst_int <= '0';
            masterfip_ext_sync_ctrl_opt_int <= '0';
            masterfip_ext_sync_ctrl_safe_wind_int <= '0';
            masterfip_macrocyc_lgth_int <= "0000000000000000000000000000000";
            masterfip_macrocyc_start_int <= '0';
            masterfip_turnar_lgth_int <= "0000000000000000000000000000000";
            masterfip_turnar_start_int <= '0';
            masterfip_silen_lgth_int <= "0000000000000000000000000000000";
            masterfip_silen_start_int <= '0';
            masterfip_tx_ctrl_rst_int <= '0';
            masterfip_tx_ctrl_start_int <= '0';
            masterfip_tx_ctrl_bytes_num_int <= "0000000000000000";
            masterfip_rx_ctrl_rst_int <= '0';
            masterfip_tx_payld_ctrl_int <= "00000000";
            masterfip_tx_payld_reg1_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg2_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg3_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg4_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg5_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg6_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg7_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg8_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg9_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg10_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg11_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg12_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg13_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg14_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg15_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg16_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg17_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg18_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg19_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg20_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg21_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg22_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg23_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg24_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg25_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg26_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg27_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg28_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg29_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg30_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg31_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg32_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg33_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg34_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg35_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg36_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg37_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg38_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg39_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg40_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg41_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg42_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg43_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg44_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg45_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg46_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg47_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg48_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg49_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg50_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg51_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg52_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg53_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg54_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg55_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg56_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg57_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg58_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg59_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg60_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg61_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg62_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg63_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg64_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg65_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg66_int <= "00000000000000000000000000000000";
            masterfip_tx_payld_reg67_int <= "00000000000000000000000000000000";
        elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
            ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
            ack_sreg(9) <= '0';
            if (ack_in_progress = '1') then
                if (ack_sreg(0) = '1') then
                    masterfip_rst_core_int <= '0';
                    masterfip_rst_fd_int <= '0';
                    masterfip_macrocyc_start_int <= '0';
                    masterfip_turnar_start_int <= '0';
                    masterfip_silen_start_int <= '0';
                    masterfip_tx_ctrl_rst_int <= '0';
                    masterfip_tx_ctrl_start_int <= '0';
                    masterfip_rx_ctrl_rst_int <= '0';
                    ack_in_progress <= '0';
                else
                end if;
            else
                if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
                    case rwaddr_reg(7 downto 0) is
                    when "00000000" => 
                        if (wb_we_i = '1') then
                            masterfip_rst_core_int <= wrdata_reg(0);
                            masterfip_rst_fd_int <= wrdata_reg(1);
                        end if;
                        rddata_reg(0) <= '0';
                        rddata_reg(1) <= '0';
                        rddata_reg(0) <= 'X';
                        rddata_reg(1) <= 'X';
                        rddata_reg(2) <= 'X';
                        rddata_reg(3) <= 'X';
                        rddata_reg(4) <= 'X';
                        rddata_reg(5) <= 'X';
                        rddata_reg(6) <= 'X';
                        rddata_reg(7) <= 'X';
                        rddata_reg(8) <= 'X';
                        rddata_reg(9) <= 'X';
                        rddata_reg(10) <= 'X';
                        rddata_reg(11) <= 'X';
                        rddata_reg(12) <= 'X';
                        rddata_reg(13) <= 'X';
                        rddata_reg(14) <= 'X';
                        rddata_reg(15) <= 'X';
                        rddata_reg(16) <= 'X';
                        rddata_reg(17) <= 'X';
                        rddata_reg(18) <= 'X';
                        rddata_reg(19) <= 'X';
                        rddata_reg(20) <= 'X';
                        rddata_reg(21) <= 'X';
                        rddata_reg(22) <= 'X';
                        rddata_reg(23) <= 'X';
                        rddata_reg(24) <= 'X';
                        rddata_reg(25) <= 'X';
                        rddata_reg(26) <= 'X';
                        rddata_reg(27) <= 'X';
                        rddata_reg(28) <= 'X';
                        rddata_reg(29) <= 'X';
                        rddata_reg(30) <= 'X';
                        rddata_reg(31) <= 'X';
                        ack_sreg(2) <= '1';
                        ack_in_progress <= '1';
                    when "00000001" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= "11000000000000001111111111101110";
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00000010" => 
                        if (wb_we_i = '1') then
                            masterfip_led_rx_act_int <= wrdata_reg(0);
                            masterfip_led_rx_err_int <= wrdata_reg(1);
                            masterfip_led_tx_act_int <= wrdata_reg(2);
                            masterfip_led_tx_err_int <= wrdata_reg(3);
                            masterfip_led_ext_sync_act_int <= wrdata_reg(4);
                            masterfip_led_ext_sync_err_int <= wrdata_reg(5);
                            masterfip_led_dbg_int <= wrdata_reg(31 downto 8);
                        end if;
                        rddata_reg(0) <= masterfip_led_rx_act_int;
                        rddata_reg(1) <= masterfip_led_rx_err_int;
                        rddata_reg(2) <= masterfip_led_tx_act_int;
                        rddata_reg(3) <= masterfip_led_tx_err_int;
                        rddata_reg(4) <= masterfip_led_ext_sync_act_int;
                        rddata_reg(5) <= masterfip_led_ext_sync_err_int;
                        rddata_reg(31 downto 8) <= masterfip_led_dbg_int;
                        rddata_reg(6) <= 'X';
                        rddata_reg(7) <= 'X';
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00000011" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(15 downto 0) <= masterfip_ds1820_temper_i;
                        rddata_reg(16) <= 'X';
                        rddata_reg(17) <= 'X';
                        rddata_reg(18) <= 'X';
                        rddata_reg(19) <= 'X';
                        rddata_reg(20) <= 'X';
                        rddata_reg(21) <= 'X';
                        rddata_reg(22) <= 'X';
                        rddata_reg(23) <= 'X';
                        rddata_reg(24) <= 'X';
                        rddata_reg(25) <= 'X';
                        rddata_reg(26) <= 'X';
                        rddata_reg(27) <= 'X';
                        rddata_reg(28) <= 'X';
                        rddata_reg(29) <= 'X';
                        rddata_reg(30) <= 'X';
                        rddata_reg(31) <= 'X';
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00000100" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_ds1820_id_lsb_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00000101" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_ds1820_id_msb_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00000110" => 
                        if (wb_we_i = '1') then
                            masterfip_ext_sync_ctrl_term_en_int <= wrdata_reg(0);
                            masterfip_ext_sync_ctrl_dir_int <= wrdata_reg(1);
                            masterfip_ext_sync_ctrl_oe_n_int <= wrdata_reg(2);
                            masterfip_ext_sync_ctrl_p_cnt_rst_int <= wrdata_reg(8);
                            masterfip_ext_sync_ctrl_opt_int <= wrdata_reg(16);
                            masterfip_ext_sync_ctrl_safe_wind_int <= wrdata_reg(24);
                        end if;
                        rddata_reg(0) <= masterfip_ext_sync_ctrl_term_en_int;
                        rddata_reg(1) <= masterfip_ext_sync_ctrl_dir_int;
                        rddata_reg(2) <= masterfip_ext_sync_ctrl_oe_n_int;
                        rddata_reg(8) <= masterfip_ext_sync_ctrl_p_cnt_rst_int;
                        rddata_reg(16) <= masterfip_ext_sync_ctrl_opt_int;
                        rddata_reg(24) <= masterfip_ext_sync_ctrl_safe_wind_int;
                        rddata_reg(3) <= 'X';
                        rddata_reg(4) <= 'X';
                        rddata_reg(5) <= 'X';
                        rddata_reg(6) <= 'X';
                        rddata_reg(7) <= 'X';
                        rddata_reg(9) <= 'X';
                        rddata_reg(10) <= 'X';
                        rddata_reg(11) <= 'X';
                        rddata_reg(12) <= 'X';
                        rddata_reg(13) <= 'X';
                        rddata_reg(14) <= 'X';
                        rddata_reg(15) <= 'X';
                        rddata_reg(17) <= 'X';
                        rddata_reg(18) <= 'X';
                        rddata_reg(19) <= 'X';
                        rddata_reg(20) <= 'X';
                        rddata_reg(21) <= 'X';
                        rddata_reg(22) <= 'X';
                        rddata_reg(23) <= 'X';
                        rddata_reg(25) <= 'X';
                        rddata_reg(26) <= 'X';
                        rddata_reg(27) <= 'X';
                        rddata_reg(28) <= 'X';
                        rddata_reg(29) <= 'X';
                        rddata_reg(30) <= 'X';
                        rddata_reg(31) <= 'X';
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00000111" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_ext_sync_p_cnt_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00001000" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(1 downto 0) <= masterfip_speed_i;
                        rddata_reg(2) <= 'X';
                        rddata_reg(3) <= 'X';
                        rddata_reg(4) <= 'X';
                        rddata_reg(5) <= 'X';
                        rddata_reg(6) <= 'X';
                        rddata_reg(7) <= 'X';
                        rddata_reg(8) <= 'X';
                        rddata_reg(9) <= 'X';
                        rddata_reg(10) <= 'X';
                        rddata_reg(11) <= 'X';
                        rddata_reg(12) <= 'X';
                        rddata_reg(13) <= 'X';
                        rddata_reg(14) <= 'X';
                        rddata_reg(15) <= 'X';
                        rddata_reg(16) <= 'X';
                        rddata_reg(17) <= 'X';
                        rddata_reg(18) <= 'X';
                        rddata_reg(19) <= 'X';
                        rddata_reg(20) <= 'X';
                        rddata_reg(21) <= 'X';
                        rddata_reg(22) <= 'X';
                        rddata_reg(23) <= 'X';
                        rddata_reg(24) <= 'X';
                        rddata_reg(25) <= 'X';
                        rddata_reg(26) <= 'X';
                        rddata_reg(27) <= 'X';
                        rddata_reg(28) <= 'X';
                        rddata_reg(29) <= 'X';
                        rddata_reg(30) <= 'X';
                        rddata_reg(31) <= 'X';
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00001001" => 
                        if (wb_we_i = '1') then
                            masterfip_macrocyc_lgth_int <= wrdata_reg(30 downto 0);
                            masterfip_macrocyc_start_int <= wrdata_reg(31);
                        end if;
                        rddata_reg(30 downto 0) <= masterfip_macrocyc_lgth_int;
                        rddata_reg(31) <= '0';
                        ack_sreg(2) <= '1';
                        ack_in_progress <= '1';
                    when "00001010" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(30 downto 0) <= masterfip_macrocyc_time_cnt_i;
                        rddata_reg(31) <= 'X';
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00001011" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_macrocyc_num_cnt_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00001100" => 
                        if (wb_we_i = '1') then
                            masterfip_turnar_lgth_int <= wrdata_reg(30 downto 0);
                            masterfip_turnar_start_int <= wrdata_reg(31);
                        end if;
                        rddata_reg(30 downto 0) <= masterfip_turnar_lgth_int;
                        rddata_reg(31) <= '0';
                        ack_sreg(2) <= '1';
                        ack_in_progress <= '1';
                    when "00001101" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(30 downto 0) <= masterfip_turnar_time_cnt_i;
                        rddata_reg(31) <= 'X';
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00001110" => 
                        if (wb_we_i = '1') then
                            masterfip_silen_lgth_int <= wrdata_reg(30 downto 0);
                            masterfip_silen_start_int <= wrdata_reg(31);
                        end if;
                        rddata_reg(30 downto 0) <= masterfip_silen_lgth_int;
                        rddata_reg(31) <= '0';
                        ack_sreg(2) <= '1';
                        ack_in_progress <= '1';
                    when "00001111" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(30 downto 0) <= masterfip_silen_time_cnt_i;
                        rddata_reg(31) <= 'X';
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00010000" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_ctrl_rst_int <= wrdata_reg(0);
                            masterfip_tx_ctrl_start_int <= wrdata_reg(1);
                            masterfip_tx_ctrl_bytes_num_int <= wrdata_reg(23 downto 8);
                        end if;
                        rddata_reg(0) <= '0';
                        rddata_reg(1) <= '0';
                        rddata_reg(23 downto 8) <= masterfip_tx_ctrl_bytes_num_int;
                        rddata_reg(2) <= 'X';
                        rddata_reg(3) <= 'X';
                        rddata_reg(4) <= 'X';
                        rddata_reg(5) <= 'X';
                        rddata_reg(6) <= 'X';
                        rddata_reg(7) <= 'X';
                        rddata_reg(24) <= 'X';
                        rddata_reg(25) <= 'X';
                        rddata_reg(26) <= 'X';
                        rddata_reg(27) <= 'X';
                        rddata_reg(28) <= 'X';
                        rddata_reg(29) <= 'X';
                        rddata_reg(30) <= 'X';
                        rddata_reg(31) <= 'X';
                        ack_sreg(2) <= '1';
                        ack_in_progress <= '1';
                    when "00010001" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(0) <= masterfip_tx_stat_stop_i;
                        rddata_reg(8) <= masterfip_tx_stat_ena_i;
                        rddata_reg(31 downto 16) <= masterfip_tx_stat_curr_byte_indx_i;
                        rddata_reg(1) <= 'X';
                        rddata_reg(2) <= 'X';
                        rddata_reg(3) <= 'X';
                        rddata_reg(4) <= 'X';
                        rddata_reg(5) <= 'X';
                        rddata_reg(6) <= 'X';
                        rddata_reg(7) <= 'X';
                        rddata_reg(9) <= 'X';
                        rddata_reg(10) <= 'X';
                        rddata_reg(11) <= 'X';
                        rddata_reg(12) <= 'X';
                        rddata_reg(13) <= 'X';
                        rddata_reg(14) <= 'X';
                        rddata_reg(15) <= 'X';
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00010010" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(0) <= masterfip_fd_wdg_i;
                        rddata_reg(1) <= masterfip_fd_cd_i;
                        rddata_reg(2) <= 'X';
                        rddata_reg(3) <= 'X';
                        rddata_reg(4) <= 'X';
                        rddata_reg(5) <= 'X';
                        rddata_reg(6) <= 'X';
                        rddata_reg(7) <= 'X';
                        rddata_reg(8) <= 'X';
                        rddata_reg(9) <= 'X';
                        rddata_reg(10) <= 'X';
                        rddata_reg(11) <= 'X';
                        rddata_reg(12) <= 'X';
                        rddata_reg(13) <= 'X';
                        rddata_reg(14) <= 'X';
                        rddata_reg(15) <= 'X';
                        rddata_reg(16) <= 'X';
                        rddata_reg(17) <= 'X';
                        rddata_reg(18) <= 'X';
                        rddata_reg(19) <= 'X';
                        rddata_reg(20) <= 'X';
                        rddata_reg(21) <= 'X';
                        rddata_reg(22) <= 'X';
                        rddata_reg(23) <= 'X';
                        rddata_reg(24) <= 'X';
                        rddata_reg(25) <= 'X';
                        rddata_reg(26) <= 'X';
                        rddata_reg(27) <= 'X';
                        rddata_reg(28) <= 'X';
                        rddata_reg(29) <= 'X';
                        rddata_reg(30) <= 'X';
                        rddata_reg(31) <= 'X';
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00010011" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_fd_wdg_tstamp_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00010100" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_fd_txer_cnt_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00010101" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_fd_txer_tstamp_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00010110" => 
                        if (wb_we_i = '1') then
                            masterfip_rx_ctrl_rst_int <= wrdata_reg(0);
                        end if;
                        rddata_reg(0) <= '0';
                        rddata_reg(1) <= 'X';
                        rddata_reg(2) <= 'X';
                        rddata_reg(3) <= 'X';
                        rddata_reg(4) <= 'X';
                        rddata_reg(5) <= 'X';
                        rddata_reg(6) <= 'X';
                        rddata_reg(7) <= 'X';
                        rddata_reg(8) <= 'X';
                        rddata_reg(9) <= 'X';
                        rddata_reg(10) <= 'X';
                        rddata_reg(11) <= 'X';
                        rddata_reg(12) <= 'X';
                        rddata_reg(13) <= 'X';
                        rddata_reg(14) <= 'X';
                        rddata_reg(15) <= 'X';
                        rddata_reg(16) <= 'X';
                        rddata_reg(17) <= 'X';
                        rddata_reg(18) <= 'X';
                        rddata_reg(19) <= 'X';
                        rddata_reg(20) <= 'X';
                        rddata_reg(21) <= 'X';
                        rddata_reg(22) <= 'X';
                        rddata_reg(23) <= 'X';
                        rddata_reg(24) <= 'X';
                        rddata_reg(25) <= 'X';
                        rddata_reg(26) <= 'X';
                        rddata_reg(27) <= 'X';
                        rddata_reg(28) <= 'X';
                        rddata_reg(29) <= 'X';
                        rddata_reg(30) <= 'X';
                        rddata_reg(31) <= 'X';
                        ack_sreg(2) <= '1';
                        ack_in_progress <= '1';
                    when "00010111" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(0) <= masterfip_rx_stat_pream_ok_i;
                        rddata_reg(1) <= masterfip_rx_stat_frame_ok_i;
                        rddata_reg(2) <= masterfip_rx_stat_frame_crc_err_i;
                        rddata_reg(23 downto 8) <= masterfip_rx_stat_bytes_num_i;
                        rddata_reg(3) <= 'X';
                        rddata_reg(4) <= 'X';
                        rddata_reg(5) <= 'X';
                        rddata_reg(6) <= 'X';
                        rddata_reg(7) <= 'X';
                        rddata_reg(24) <= 'X';
                        rddata_reg(25) <= 'X';
                        rddata_reg(26) <= 'X';
                        rddata_reg(27) <= 'X';
                        rddata_reg(28) <= 'X';
                        rddata_reg(29) <= 'X';
                        rddata_reg(30) <= 'X';
                        rddata_reg(31) <= 'X';
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00011000" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(7 downto 0) <= masterfip_rx_stat_curr_word_indx_i;
                        rddata_reg(8) <= 'X';
                        rddata_reg(9) <= 'X';
                        rddata_reg(10) <= 'X';
                        rddata_reg(11) <= 'X';
                        rddata_reg(12) <= 'X';
                        rddata_reg(13) <= 'X';
                        rddata_reg(14) <= 'X';
                        rddata_reg(15) <= 'X';
                        rddata_reg(16) <= 'X';
                        rddata_reg(17) <= 'X';
                        rddata_reg(18) <= 'X';
                        rddata_reg(19) <= 'X';
                        rddata_reg(20) <= 'X';
                        rddata_reg(21) <= 'X';
                        rddata_reg(22) <= 'X';
                        rddata_reg(23) <= 'X';
                        rddata_reg(24) <= 'X';
                        rddata_reg(25) <= 'X';
                        rddata_reg(26) <= 'X';
                        rddata_reg(27) <= 'X';
                        rddata_reg(28) <= 'X';
                        rddata_reg(29) <= 'X';
                        rddata_reg(30) <= 'X';
                        rddata_reg(31) <= 'X';
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00011001" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_stat_crc_err_cnt_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00011010" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(7 downto 0) <= masterfip_rx_payld_ctrl_i;
                        rddata_reg(8) <= 'X';
                        rddata_reg(9) <= 'X';
                        rddata_reg(10) <= 'X';
                        rddata_reg(11) <= 'X';
                        rddata_reg(12) <= 'X';
                        rddata_reg(13) <= 'X';
                        rddata_reg(14) <= 'X';
                        rddata_reg(15) <= 'X';
                        rddata_reg(16) <= 'X';
                        rddata_reg(17) <= 'X';
                        rddata_reg(18) <= 'X';
                        rddata_reg(19) <= 'X';
                        rddata_reg(20) <= 'X';
                        rddata_reg(21) <= 'X';
                        rddata_reg(22) <= 'X';
                        rddata_reg(23) <= 'X';
                        rddata_reg(24) <= 'X';
                        rddata_reg(25) <= 'X';
                        rddata_reg(26) <= 'X';
                        rddata_reg(27) <= 'X';
                        rddata_reg(28) <= 'X';
                        rddata_reg(29) <= 'X';
                        rddata_reg(30) <= 'X';
                        rddata_reg(31) <= 'X';
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00011011" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg1_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00011100" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg2_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00011101" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg3_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00011110" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg4_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00011111" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg5_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00100000" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg6_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00100001" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg7_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00100010" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg8_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00100011" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg9_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00100100" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg10_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00100101" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg11_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00100110" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg12_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00100111" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg13_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00101000" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg14_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00101001" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg15_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00101010" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg16_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00101011" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg17_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00101100" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg18_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00101101" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg19_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00101110" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg20_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00101111" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg21_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00110000" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg22_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00110001" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg23_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00110010" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg24_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00110011" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg25_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00110100" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg26_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00110101" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg27_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00110110" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg28_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00110111" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg29_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00111000" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg30_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00111001" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg31_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00111010" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg32_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00111011" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg33_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00111100" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg34_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00111101" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg35_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00111110" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg36_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "00111111" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg37_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01000000" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg38_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01000001" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg39_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01000010" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg40_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01000011" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg41_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01000100" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg42_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01000101" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg43_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01000110" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg44_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01000111" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg45_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01001000" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg46_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01001001" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg47_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01001010" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg48_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01001011" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg49_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01001100" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg50_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01001101" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg51_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01001110" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg52_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01001111" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg53_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01010000" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg54_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01010001" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg55_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01010010" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg56_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01010011" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg57_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01010100" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg58_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01010101" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg59_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01010110" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg60_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01010111" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg61_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01011000" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg62_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01011001" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg63_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01011010" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg64_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01011011" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg65_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01011100" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg66_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01011101" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_rx_payld_reg67_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01011110" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_ctrl_int <= wrdata_reg(7 downto 0);
                        end if;
                        rddata_reg(7 downto 0) <= masterfip_tx_payld_ctrl_int;
                        rddata_reg(8) <= 'X';
                        rddata_reg(9) <= 'X';
                        rddata_reg(10) <= 'X';
                        rddata_reg(11) <= 'X';
                        rddata_reg(12) <= 'X';
                        rddata_reg(13) <= 'X';
                        rddata_reg(14) <= 'X';
                        rddata_reg(15) <= 'X';
                        rddata_reg(16) <= 'X';
                        rddata_reg(17) <= 'X';
                        rddata_reg(18) <= 'X';
                        rddata_reg(19) <= 'X';
                        rddata_reg(20) <= 'X';
                        rddata_reg(21) <= 'X';
                        rddata_reg(22) <= 'X';
                        rddata_reg(23) <= 'X';
                        rddata_reg(24) <= 'X';
                        rddata_reg(25) <= 'X';
                        rddata_reg(26) <= 'X';
                        rddata_reg(27) <= 'X';
                        rddata_reg(28) <= 'X';
                        rddata_reg(29) <= 'X';
                        rddata_reg(30) <= 'X';
                        rddata_reg(31) <= 'X';
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01011111" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg1_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg1_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01100000" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg2_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg2_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01100001" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg3_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg3_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01100010" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg4_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg4_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01100011" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg5_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg5_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01100100" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg6_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg6_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01100101" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg7_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg7_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01100110" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg8_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg8_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01100111" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg9_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg9_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01101000" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg10_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg10_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01101001" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg11_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg11_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01101010" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg12_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg12_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01101011" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg13_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg13_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01101100" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg14_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg14_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01101101" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg15_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg15_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01101110" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg16_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg16_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01101111" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg17_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg17_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01110000" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg18_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg18_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01110001" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg19_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg19_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01110010" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg20_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg20_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01110011" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg21_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg21_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01110100" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg22_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg22_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01110101" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg23_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg23_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01110110" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg24_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg24_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01110111" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg25_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg25_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01111000" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg26_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg26_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01111001" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg27_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg27_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01111010" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg28_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg28_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01111011" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg29_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg29_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01111100" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg30_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg30_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01111101" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg31_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg31_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01111110" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg32_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg32_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "01111111" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg33_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg33_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "10000000" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg34_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg34_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "10000001" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg35_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg35_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "10000010" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg36_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg36_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "10000011" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg37_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg37_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "10000100" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg38_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg38_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "10000101" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg39_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg39_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "10000110" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg40_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg40_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "10000111" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg41_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg41_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "10001000" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg42_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg42_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "10001001" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg43_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg43_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "10001010" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg44_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg44_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "10001011" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg45_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg45_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "10001100" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg46_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg46_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "10001101" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg47_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg47_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "10001110" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg48_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg48_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "10001111" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg49_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg49_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "10010000" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg50_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg50_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "10010001" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg51_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg51_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "10010010" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg52_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg52_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "10010011" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg53_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg53_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "10010100" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg54_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg54_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "10010101" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg55_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg55_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "10010110" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg56_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg56_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "10010111" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg57_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg57_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "10011000" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg58_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg58_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "10011001" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg59_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg59_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "10011010" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg60_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg60_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "10011011" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg61_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg61_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "10011100" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg62_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg62_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "10011101" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg63_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg63_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "10011110" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg64_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg64_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "10011111" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg65_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg65_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "10100000" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg66_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg66_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "10100001" => 
                        if (wb_we_i = '1') then
                            masterfip_tx_payld_reg67_int <= wrdata_reg(31 downto 0);
                        end if;
                        rddata_reg(31 downto 0) <= masterfip_tx_payld_reg67_int;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when others =>
-- prevent the slave from hanging the bus on invalid address
                        ack_in_progress <= '1';
                        ack_sreg(0) <= '1';
                    end case;
                end if;
            end if;
        end if;
    end process;
    
    
-- Drive the data output bus
    wb_dat_o <= rddata_reg;
-- reset of the masterFIP core
    process (clk_sys_i, rst_n_i)
    begin
        if (rst_n_i = '0') then 
            masterfip_rst_core_dly0 <= '0';
            masterfip_rst_core_o <= '0';
        elsif rising_edge(clk_sys_i) then
            masterfip_rst_core_dly0 <= masterfip_rst_core_int;
            masterfip_rst_core_o <= masterfip_rst_core_int and (not masterfip_rst_core_dly0);
        end if;
    end process;
    
    
-- reset of the FielDrive chip
    process (clk_sys_i, rst_n_i)
    begin
        if (rst_n_i = '0') then 
            masterfip_rst_fd_dly0 <= '0';
            masterfip_rst_fd_o <= '0';
        elsif rising_edge(clk_sys_i) then
            masterfip_rst_fd_dly0 <= masterfip_rst_fd_int;
            masterfip_rst_fd_o <= masterfip_rst_fd_int and (not masterfip_rst_fd_dly0);
        end if;
    end process;
    
    
-- rx act green led
    masterfip_led_rx_act_o <= masterfip_led_rx_act_int;
-- rx err red led
    masterfip_led_rx_err_o <= masterfip_led_rx_err_int;
-- tx act green led
    masterfip_led_tx_act_o <= masterfip_led_tx_act_int;
-- tx err red led
    masterfip_led_tx_err_o <= masterfip_led_tx_err_int;
-- ext sync act green led
    masterfip_led_ext_sync_act_o <= masterfip_led_ext_sync_act_int;
-- ext sync err red led
    masterfip_led_ext_sync_err_o <= masterfip_led_ext_sync_err_int;
-- dbg
    masterfip_led_dbg_o <= masterfip_led_dbg_int;
-- ds1820 temperature
-- ds1820 id lsb
-- ds1820 id msb
-- termination enable
    masterfip_ext_sync_ctrl_term_en_o <= masterfip_ext_sync_ctrl_term_en_int;
-- transceiver direction
    masterfip_ext_sync_ctrl_dir_o <= masterfip_ext_sync_ctrl_dir_int;
-- transceiver output enable negative logic
    masterfip_ext_sync_ctrl_oe_n_o <= masterfip_ext_sync_ctrl_oe_n_int;
-- pulses counter reset
    masterfip_ext_sync_ctrl_p_cnt_rst_o <= masterfip_ext_sync_ctrl_p_cnt_rst_int;
-- counting options
    masterfip_ext_sync_ctrl_opt_o <= masterfip_ext_sync_ctrl_opt_int;
-- safe window
    masterfip_ext_sync_ctrl_safe_wind_o <= masterfip_ext_sync_ctrl_safe_wind_int;
-- ext_sync_p_cnt
-- WorldFIP speed, hard-wired on the FMC
-- macrocycle lgth
    masterfip_macrocyc_lgth_o <= masterfip_macrocyc_lgth_int;
-- macrocycle cnt start
    process (clk_sys_i, rst_n_i)
    begin
        if (rst_n_i = '0') then 
            masterfip_macrocyc_start_dly0 <= '0';
            masterfip_macrocyc_start_o <= '0';
        elsif rising_edge(clk_sys_i) then
            masterfip_macrocyc_start_dly0 <= masterfip_macrocyc_start_int;
            masterfip_macrocyc_start_o <= masterfip_macrocyc_start_int and (not masterfip_macrocyc_start_dly0);
        end if;
    end process;
    
    
-- macrocycle time counter
-- number of macrocycles
-- turnaround time
    masterfip_turnar_lgth_o <= masterfip_turnar_lgth_int;
-- turnaround cnt start
    process (clk_sys_i, rst_n_i)
    begin
        if (rst_n_i = '0') then 
            masterfip_turnar_start_dly0 <= '0';
            masterfip_turnar_start_o <= '0';
        elsif rising_edge(clk_sys_i) then
            masterfip_turnar_start_dly0 <= masterfip_turnar_start_int;
            masterfip_turnar_start_o <= masterfip_turnar_start_int and (not masterfip_turnar_start_dly0);
        end if;
    end process;
    
    
-- turnaround time counter
-- silence time
    masterfip_silen_lgth_o <= masterfip_silen_lgth_int;
-- silence cnt start
    process (clk_sys_i, rst_n_i)
    begin
        if (rst_n_i = '0') then 
            masterfip_silen_start_dly0 <= '0';
            masterfip_silen_start_o <= '0';
        elsif rising_edge(clk_sys_i) then
            masterfip_silen_start_dly0 <= masterfip_silen_start_int;
            masterfip_silen_start_o <= masterfip_silen_start_int and (not masterfip_silen_start_dly0);
        end if;
    end process;
    
    
-- silence time counter
-- tx rst
    process (clk_sys_i, rst_n_i)
    begin
        if (rst_n_i = '0') then 
            masterfip_tx_ctrl_rst_dly0 <= '0';
            masterfip_tx_ctrl_rst_o <= '0';
        elsif rising_edge(clk_sys_i) then
            masterfip_tx_ctrl_rst_dly0 <= masterfip_tx_ctrl_rst_int;
            masterfip_tx_ctrl_rst_o <= masterfip_tx_ctrl_rst_int and (not masterfip_tx_ctrl_rst_dly0);
        end if;
    end process;
    
    
-- tx strt
    process (clk_sys_i, rst_n_i)
    begin
        if (rst_n_i = '0') then 
            masterfip_tx_ctrl_start_dly0 <= '0';
            masterfip_tx_ctrl_start_o <= '0';
        elsif rising_edge(clk_sys_i) then
            masterfip_tx_ctrl_start_dly0 <= masterfip_tx_ctrl_start_int;
            masterfip_tx_ctrl_start_o <= masterfip_tx_ctrl_start_int and (not masterfip_tx_ctrl_start_dly0);
        end if;
    end process;
    
    
-- tx number of bytes
    masterfip_tx_ctrl_bytes_num_o <= masterfip_tx_ctrl_bytes_num_int;
-- tx ended
-- tx enable
-- tx status current byte index
-- FielDrive watchdog
-- FielDrive carrier detect
-- fd_wdgn_tstamp
-- fd_txer_cnt
-- fd_txer_tstamp
-- rx rst
    process (clk_sys_i, rst_n_i)
    begin
        if (rst_n_i = '0') then 
            masterfip_rx_ctrl_rst_dly0 <= '0';
            masterfip_rx_ctrl_rst_o <= '0';
        elsif rising_edge(clk_sys_i) then
            masterfip_rx_ctrl_rst_dly0 <= masterfip_rx_ctrl_rst_int;
            masterfip_rx_ctrl_rst_o <= masterfip_rx_ctrl_rst_int and (not masterfip_rx_ctrl_rst_dly0);
        end if;
    end process;
    
    
-- rx Preamble(FSS) detected
-- rx frame ok
-- rx frame crc error
-- rx number of payload bytes
-- current word index
-- rx number of frames with CRC error
-- rx payload ctrl byte
-- reg 1
-- reg2
-- reg3
-- reg4
-- reg5
-- reg6
-- reg7
-- reg8
-- reg9
-- reg10
-- reg11
-- reg12
-- reg13
-- reg14
-- reg15
-- reg16
-- reg17
-- reg18
-- reg19
-- reg20
-- reg21
-- reg22
-- reg23
-- reg24
-- reg25
-- reg26
-- reg27
-- reg28
-- reg29
-- reg30
-- reg31
-- reg32
-- reg 33
-- reg34
-- reg35
-- reg36
-- reg37
-- reg38
-- reg39
-- reg40
-- reg41
-- reg42
-- reg43
-- reg44
-- reg45
-- reg46
-- reg47
-- reg48
-- reg49
-- reg50
-- reg51
-- reg52
-- reg53
-- reg54
-- reg55
-- reg56
-- reg57
-- reg58
-- reg59
-- reg60
-- reg61
-- reg62
-- reg63
-- reg64
-- reg65
-- reg66
-- reg67
-- tx ctrl byte
    masterfip_tx_payld_ctrl_o <= masterfip_tx_payld_ctrl_int;
-- reg1
    masterfip_tx_payld_reg1_o <= masterfip_tx_payld_reg1_int;
-- reg2
    masterfip_tx_payld_reg2_o <= masterfip_tx_payld_reg2_int;
-- reg3
    masterfip_tx_payld_reg3_o <= masterfip_tx_payld_reg3_int;
-- reg4
    masterfip_tx_payld_reg4_o <= masterfip_tx_payld_reg4_int;
-- reg5
    masterfip_tx_payld_reg5_o <= masterfip_tx_payld_reg5_int;
-- reg6
    masterfip_tx_payld_reg6_o <= masterfip_tx_payld_reg6_int;
-- reg7
    masterfip_tx_payld_reg7_o <= masterfip_tx_payld_reg7_int;
-- reg8
    masterfip_tx_payld_reg8_o <= masterfip_tx_payld_reg8_int;
-- reg9
    masterfip_tx_payld_reg9_o <= masterfip_tx_payld_reg9_int;
-- reg10
    masterfip_tx_payld_reg10_o <= masterfip_tx_payld_reg10_int;
-- reg11
    masterfip_tx_payld_reg11_o <= masterfip_tx_payld_reg11_int;
-- reg12
    masterfip_tx_payld_reg12_o <= masterfip_tx_payld_reg12_int;
-- reg13
    masterfip_tx_payld_reg13_o <= masterfip_tx_payld_reg13_int;
-- reg14
    masterfip_tx_payld_reg14_o <= masterfip_tx_payld_reg14_int;
-- reg15
    masterfip_tx_payld_reg15_o <= masterfip_tx_payld_reg15_int;
-- reg16
    masterfip_tx_payld_reg16_o <= masterfip_tx_payld_reg16_int;
-- reg17
    masterfip_tx_payld_reg17_o <= masterfip_tx_payld_reg17_int;
-- reg18
    masterfip_tx_payld_reg18_o <= masterfip_tx_payld_reg18_int;
-- reg19
    masterfip_tx_payld_reg19_o <= masterfip_tx_payld_reg19_int;
-- reg20
    masterfip_tx_payld_reg20_o <= masterfip_tx_payld_reg20_int;
-- reg21
    masterfip_tx_payld_reg21_o <= masterfip_tx_payld_reg21_int;
-- reg22
    masterfip_tx_payld_reg22_o <= masterfip_tx_payld_reg22_int;
-- reg23
    masterfip_tx_payld_reg23_o <= masterfip_tx_payld_reg23_int;
-- reg24
    masterfip_tx_payld_reg24_o <= masterfip_tx_payld_reg24_int;
-- reg25
    masterfip_tx_payld_reg25_o <= masterfip_tx_payld_reg25_int;
-- reg26
    masterfip_tx_payld_reg26_o <= masterfip_tx_payld_reg26_int;
-- reg27
    masterfip_tx_payld_reg27_o <= masterfip_tx_payld_reg27_int;
-- reg28
    masterfip_tx_payld_reg28_o <= masterfip_tx_payld_reg28_int;
-- reg29
    masterfip_tx_payld_reg29_o <= masterfip_tx_payld_reg29_int;
-- reg30
    masterfip_tx_payld_reg30_o <= masterfip_tx_payld_reg30_int;
-- reg31
    masterfip_tx_payld_reg31_o <= masterfip_tx_payld_reg31_int;
-- reg32
    masterfip_tx_payld_reg32_o <= masterfip_tx_payld_reg32_int;
-- reg 33
    masterfip_tx_payld_reg33_o <= masterfip_tx_payld_reg33_int;
-- reg34
    masterfip_tx_payld_reg34_o <= masterfip_tx_payld_reg34_int;
-- reg35
    masterfip_tx_payld_reg35_o <= masterfip_tx_payld_reg35_int;
-- reg36
    masterfip_tx_payld_reg36_o <= masterfip_tx_payld_reg36_int;
-- reg37
    masterfip_tx_payld_reg37_o <= masterfip_tx_payld_reg37_int;
-- reg38
    masterfip_tx_payld_reg38_o <= masterfip_tx_payld_reg38_int;
-- reg39
    masterfip_tx_payld_reg39_o <= masterfip_tx_payld_reg39_int;
-- reg40
    masterfip_tx_payld_reg40_o <= masterfip_tx_payld_reg40_int;
-- reg41
    masterfip_tx_payld_reg41_o <= masterfip_tx_payld_reg41_int;
-- reg42
    masterfip_tx_payld_reg42_o <= masterfip_tx_payld_reg42_int;
-- reg43
    masterfip_tx_payld_reg43_o <= masterfip_tx_payld_reg43_int;
-- reg44
    masterfip_tx_payld_reg44_o <= masterfip_tx_payld_reg44_int;
-- reg45
    masterfip_tx_payld_reg45_o <= masterfip_tx_payld_reg45_int;
-- reg46
    masterfip_tx_payld_reg46_o <= masterfip_tx_payld_reg46_int;
-- reg47
    masterfip_tx_payld_reg47_o <= masterfip_tx_payld_reg47_int;
-- reg48
    masterfip_tx_payld_reg48_o <= masterfip_tx_payld_reg48_int;
-- reg49
    masterfip_tx_payld_reg49_o <= masterfip_tx_payld_reg49_int;
-- reg50
    masterfip_tx_payld_reg50_o <= masterfip_tx_payld_reg50_int;
-- reg51
    masterfip_tx_payld_reg51_o <= masterfip_tx_payld_reg51_int;
-- reg52
    masterfip_tx_payld_reg52_o <= masterfip_tx_payld_reg52_int;
-- reg53
    masterfip_tx_payld_reg53_o <= masterfip_tx_payld_reg53_int;
-- reg54
    masterfip_tx_payld_reg54_o <= masterfip_tx_payld_reg54_int;
-- reg55
    masterfip_tx_payld_reg55_o <= masterfip_tx_payld_reg55_int;
-- reg56
    masterfip_tx_payld_reg56_o <= masterfip_tx_payld_reg56_int;
-- reg57
    masterfip_tx_payld_reg57_o <= masterfip_tx_payld_reg57_int;
-- reg58
    masterfip_tx_payld_reg58_o <= masterfip_tx_payld_reg58_int;
-- reg59
    masterfip_tx_payld_reg59_o <= masterfip_tx_payld_reg59_int;
-- reg60
    masterfip_tx_payld_reg60_o <= masterfip_tx_payld_reg60_int;
-- reg61
    masterfip_tx_payld_reg61_o <= masterfip_tx_payld_reg61_int;
-- reg62
    masterfip_tx_payld_reg62_o <= masterfip_tx_payld_reg62_int;
-- reg63
    masterfip_tx_payld_reg63_o <= masterfip_tx_payld_reg63_int;
-- reg64
    masterfip_tx_payld_reg64_o <= masterfip_tx_payld_reg64_int;
-- reg65
    masterfip_tx_payld_reg65_o <= masterfip_tx_payld_reg65_int;
-- reg66
    masterfip_tx_payld_reg66_o <= masterfip_tx_payld_reg66_int;
-- reg67
    masterfip_tx_payld_reg67_o <= masterfip_tx_payld_reg67_int;
    rwaddr_reg <= wb_adr_i;
    wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
    wb_ack_o <= ack_sreg(0);
end syn;
