--_________________________________________________________________________________________________
--                                                                                                |
--                                        |SPEC masterFIP|                                        |
--                                                                                                |
--                                         CERN, BE/CO-HT                                         |
--________________________________________________________________________________________________|

---------------------------------------------------------------------------------------------------
--                                                                                                |
--                                        spec_masterfip_pts                                       |
--                                                                                                |
---------------------------------------------------------------------------------------------------
-- File         spec_masterfip_pts.vhd                                                             |
--                                                                                                |
-- Description  Top level of the masterFIP design with Mock Turtle on a SPEC carrier.             |
--                                                                                                |
--              Figure 1 shows the architecture and main components of the design.                |
--                ______________________________________________________________________          |
--               |                                                                      |         |
--               |                         _________________________________________    |         |
--               |                        |                             MOCK TURTLE |   |         |
--         _     |                        |                                _____    |   |         |
--        | |    |                        |                         ___   |     |   |   |         |
--        |F|    |                     . .| . . . . . . . . . . . >|   |  |     |   |   |         |
--        |I|    |   _____             .  |                        |   |  |     |   |   |         |
--        |E|    |  |     |            .  |        . . . . . . . .>|   |  |     |   |   |         |
--        |L| <--|  |     |            .  |        .         HMQs  |   |  |     |   |   |         |
--        |D|    |  |  F  |            .  |        .               |   |  |     |   |   |         |
--        |R|    |  |  M  |            .  |     ______             |   |  |     |   |   |         |
--        |I| -->|  |  C  |            .  | DP |      |            |   |  |     |   |   |         |
--        |V|    |  |     |            . .|. .>| CPU0 |   _____    | X |  |  G  |   |   |         |
--        |E|    |  |  M  |     ____   .  |    |______|  |     |   | b |  |  N  |   |   | <-PCIe->|
--        |_|    |  |  A  |    |    |  .  |              | SH. |   | a |  |  4  |   |   |   host  |
--               |  |  S  |....|Xbar|...  |     ______   | MEM |   | r |  |  1  |   |   |         |
-- ext pulse --> |  |  T  |    |____|  .  |    |      |  |_____|   |   |  |  2  |   |   |         |
--               |  |  E  |            .  | DP | CPU1 |            |   |  |  4  |   |   |         |
--               |  |  R  |            . .|. .>|______|            |   |  |     |   |   |         |
-- FMC 1wire <-->|  |  F  |               |       .                |   |  |     |   |   |         |
--               |  |  I  |               |       .           HMQs |   |  |     |   |   |         |
--               |  |  P  |               |       . . . . . . . . >|___|  |     |   |   |         |
--   FMC LEDs <--|  |     |               |                               |_____|   |   |         |
--               |  |_____|               |                                 _^_     |   |         |
--               |                        |                                |   |    |   |         |
--               |                        |                                |VIC|    |   |         |
--               |                        |                                |___|    |   |         |
--               |                        |_________________________________________|   |         |
--               |______________________________________________________________________|         |
--                              Figure 1: spec_masterfip_pts architecture                          |
--                                                                                                |
--                                                                                                |
--              FMC MASTERFIP CORE:                                                               |
--              On one side the FMC MASTERFIP CORE is the interface to the FMC hardware (i.e.     |
--              FielDrive chip, external pulse LEMO, 1-wire DS18B20 chip, LEDs) on the other side |
--              it provides a wbgen2 WISHBONE where a set of control and status registers have    |
--              been defined to interface with the MOCK TURTLE.                                   |
--              The core ignores the notion of the WorldFIP frame type (ID_DAT/RT_DAT/..etc),     |
--              or the macrocycle sequence and macrocycle timing; the sw running on the Mock      |
--              Turtle CPUs is responsible for managing these aspects and for providing to this   |
--              core all the payload bytes (coming from the host) that have to be serializedand,  |
--              together with a serialization startup trigger, or for enabling the deserializer   |
--              and then providing to the host the deserialized bytes.                            |
--              Figure 2 shows the structure of a WorldFIP frame. The core is internally          |
--              generating (in the case of serialization) or validating (in the case of           |
--              deserialization) only the FSS, CRC and FES bytes; the rest of the bytes are       |
--              retrieved from or provided to the MOCK TURTLE. The core also encodes/decodes all  |
--              the bytes to/from the Manchester2 code (as specified by the WorldFIP protocol) and|
--              controls/monitors all the FielDrive signals.                                      |
--               _____________________________________________________________________________    |
--              |_____FSS_____|__Ctrl__|_____________Payload_____________|_____CRC____|__FES__|   |
--                                                                                                |
--                                     Figure 2: WorldFIP frame structure                         |
--                                                                                                |
--              MOCK TURTLE:                                                                      |
--              Instead of having a big FSM in HDL that would be executing the WorldFIP           |
--              macrocycle, we have software running on an embedded CPU, in order to add          |
--              flexibility and ease the implementation of the design. Mock Turtle is the         |
--              generic core that offers multi-CPU processing and all the infrastructure around.  |
--              The interface between the CPUs and the PCIe host is though HostMessageQueues(HMQ).|
--              The interface between the CPUs with the FMC MASTERFIP CORE is a set of wbgen2-    |
--              generated registers.                                                              |
--              In this design MT is configured with 2 CPUs:                                      |
--              - CPU0 is the heart of the design; it is "playing" the WorldFIP macrocycle.       |
--                For example,it initiates the delivery of a WorldFIP question frame, by providing|
--                the frame bytes to the FMC MASTERFIP CORE, and then awaits for the reception of |
--                the response frame.It retrieves these consumed data from the FMC MASTERFIP CORE,|
--                packs them in the corresponding HMQ (according to the frame type) and can notify|
--                the host through an IRQ.                                                        |
--              - CPU1 is mainly polling the host to retrieve new payload bytes for production.   |
--                When new data is received from the host through a dedicated HMQ, CPU1 puts them |
--                into the Shared Memory for CPU0 to retrieve them and provide them to the        |
--                FMC MASTERFIP CORE for serialization.                                           |
--                CPU1 does not need access to the FMC MASTERFIP CORE; however access is possible |
--                for debugging purposes.                                                         |
--                                                                                                |
--              XBAR:                                                                             |
--              The crossbar between the FMC MASTERFIP CORE and MOCK TURTLE is used so that       |
--              CPU0, CPU1 and to the PCIe host can access directly the wbgen2-defined regs       |
--              in the FMC MASTERFIP CORE.                                                        |
--              Note that to give access to the FMC MASTERFIP CORE to both CPU0 and CPU1, we      |
--              could have used the Shared Port of MT, instead of using the Dedicated Ports (DP)  |
--              and this crossbar; this though would have also affected (potentially slowed down) |
--              the accesses to the MT Shared Memory.                                             |
--              Note also that as mentioned above CPU1 is only accessing the FMC MASTERFIP CORE   |
--              for debugging purposes; the same goes also for the PCIe host.                     |
--                                                                                                |
--              CLK, RST:                                                                         |
--              There is only one clock domain of 100 MHz, in the whole design. The clock is       |
--              generated inside the MOCK TURTLE, from the 125 MHz SPEC PLL IC6 output clock      |
--              (clk_125m_pllref_p_i,clk_125m_pllref_n_i) and it is used by both MOCK TURTLE CPUs,|
--              by the FMC MASTERFIP CORE and the XBAR. A PCIe reset signal, synchronous to       |
--              the 100 MHz clock is also provided by MOCK TURTLE.                                |
--                                                                                                |
--              MEMORY MAP AS SEEN FROM PCIe:                                                     |
--              0x00000000 (size: 4 bytes)      : SDB signature                                   |
--              0x00002000 (size: 64 bytes)     : VIC                                             |
--              0x00010000 (size: 644 bytes)    : Host access to the FMC MASTERFIP CORE           |
--              0x00020000 (size: 128 kB)       : MOCK TURTLE                                     |
--                |-- 0x00020000                : HMQ Global Control Registers                    |
--                |-- 0x00024000                : HMQ incoming slots (Host->CPUs)                 |
--                |-- 0x00028000                : HMQ outgoing slots (CPUs->Host)                 |
--                |-- 0x0002c000                : CPU Control/Status Registers                    |
--                |-- 0x00030000                : Shared Memory (64 KB)                           |
--                                                                                                |
-- Authors      Evangelia Gousiou (Evangelia.Gousiou@cern.ch)                                     |
--              Eva Calvo Giraldo (Eva.Calvo.Giraldo@cern.ch)                                     |
--              Tomasz Wlostowski (Tomasz.Wlostowski@cern.ch)                                     |
--                                                                                                |
---------------------------------------------------------------------------------------------------

---------------------------------------------------------------------------------------------------
--                               GNU LESSER GENERAL PUBLIC LICENSE                                |
--                              ------------------------------------                              |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either     |
-- version 2.1 of the License, or (at your option) any later version.                             |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;       |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.      |
-- See the GNU Lesser General Public License for more details.                                    |
-- You should have received a copy of the GNU Lesser General Public License along with this       |
-- source; if not, please download it from http://www.gnu.org/licenses/lgpl-2.1.html              |
---------------------------------------------------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;       -- std_logic definitions
use IEEE.numeric_std.all;          -- conversion functions

library work;
use work.wishbone_pkg.all;         -- for the wb_crossbar
use work.spec_node_pkg.all;        -- for the spec_node_template definition
use work.wr_node_pkg.all;          -- for the spec_node_template configuration
use work.wrn_mqueue_pkg.all;       -- for the HMQ
use work.masterFIP_pkg.all;        -- for the fmc_masterfip_core definition
use work.masterfip_wbgen2_pkg.all; -- for the masterfip_wbgen2_csr records


entity spec_masterfip_pts is
  generic (g_simulation : boolean := false);
  port
   (-- Carrier signals
    --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
    -- Clock
     clk_125m_pllref_p_i : in   std_logic;                     -- 125 MHz PLL reference,
     clk_125m_pllref_n_i : in   std_logic;                     -- used in MT to generate 100 MHz

    -- GENNUM interface
     l_rst_n_i           : in    std_logic;                    -- reset from GENNUM (RSTOUT18_N)
     gpio_b              : inout std_logic_vector(1 downto 0); -- general purpose interface
     -- -- PCIe to Local [Inbound Data] - RX
     p2l_rdy_o           : out   std_logic;                    -- rx buffer full flag
     p2l_clkn_i          : in    std_logic;                    -- receiver source synch clock-
     p2l_clkp_i          : in    std_logic;                    -- receiver source synch clock+
     p2l_data_i          : in    std_logic_vector(15 downto 0);-- parallel receive data
     p2l_dframe_i        : in    std_logic;                    -- receive frame
     p2l_valid_i         : in    std_logic;                    -- receive data valid
     -- -- Inbound Buffer Request/Status
     p_wr_req_i          : in    std_logic_vector(1 downto 0); -- PCIe write request
     p_wr_rdy_o          : out   std_logic_vector(1 downto 0); -- PCIe write ready
     rx_error_o          : out   std_logic;                    -- receive error
     -- -- Local to Parallel [Outbound Data] - TX
     l2p_data_o          : out   std_logic_vector(15 downto 0);-- parallel transmit data
     l2p_dframe_o        : out   std_logic;                    -- transmit data frame
     l2p_valid_o         : out   std_logic;                    -- transmit data valid
     l2p_clkn_o          : out   std_logic;                    -- transmitter source synch clock-
     l2p_clkp_o          : out   std_logic;                    -- transmitter source synch clock+
     l2p_edb_o           : out   std_logic;                    -- packet termination and discard
     -- -- Outbound Buffer Status
     l2p_rdy_i           : in    std_logic;                    -- tx buffer full flag
     l_wr_rdy_i          : in    std_logic_vector(1 downto 0); -- Local-to-PCIe Write
     p_rd_d_rdy_i        : in    std_logic_vector(1 downto 0); -- PCIe-to-Local read resp data ready
     tx_error_i          : in    std_logic;                    -- transmit error
     vc_rdy_i            : in    std_logic_vector(1 downto 0); -- channel ready

    -- DAC I2C (driven by MT for max stability on the 100 MHz clk)
     dac_cs_n_o          : out   std_logic_vector(1 downto 0); -- 0: select SPEC 25MHz OSC5 VCXO
     dac_sclk_o          : out   std_logic;                    -- 1: select SPEC 20MHz OSC1 VCXO
     dac_din_o           : out   std_logic;

    -- SPEC LEDs
     led_green_o         : out   std_logic;                    -- blinking with clk_100m_sys
     led_red_o           : out   std_logic;                    -- active during a PCIe rst, l_rst_n_i
          -- PCB version
    pcb_ver_i : in std_logic_vector(3 downto 0);

    -- FMC signals
    --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
    -- FMC presence
     fmc_prsnt_m2c_n_i   : in    std_logic;                    -- FMC presence (used by MT)

         -- fmc i2c interface
    fmc_scl_io           : inout std_logic;
    fmc_sda_io           : inout std_logic;

    -- FMC 1-wire
     fmc_onewire_b       : inout std_logic;                    -- temper and unique id

    -- WorldFIP bus speed                                      -- 31K25bps: speed_b1=0, speed_b0=0
     speed_b0_i          : in  std_logic;                      -- 1Mbps   : speed_b1=0, speed_b0=1
     speed_b1_i          : in  std_logic;                      -- 2M5bps  : speed_b1=1, speed_b0=0
                                                               -- 5Mbps   : speed_b1=1, speed_b0=1
    -- WorldFIP FielDrive
     fd_rstn_o           : out   std_logic;                    -- reset
     fd_rxcdn_i          : in    std_logic;                    -- rx carrier detect
     fd_rxd_i            : in    std_logic;                    -- rx data
     fd_txer_i           : in    std_logic;                    -- tx error
     fd_wdgn_i           : in    std_logic;                    -- tx watchdog
     fd_txck_o           : out   std_logic;                    -- tx clk
     fd_txd_o            : out   std_logic;                    -- tx data
     fd_txena_o          : out   std_logic;                    -- tx enable

    -- External synchronisation pulse (input signal and transceiver control)
     ext_sync_term_en_o  : out std_logic;                      -- enable 50 Ohm termin of the pulse
     ext_sync_dir_o      : out std_logic := '0';               -- direction fixed B -> A
     ext_sync_oe_n_o     : out std_logic := '0';               -- output fixed to enabled
     ext_sync_io         : inout  std_logic;                      -- sync pulse

    -- FMC Front panel LEDs: controlled by the MT firmware, updated every macrocycle
     led_rx_act_n_o      : out   std_logic;
     led_rx_err_n_o      : out   std_logic;
     led_tx_act_n_o      : out   std_logic;
     led_tx_err_n_o      : out   std_logic;
     led_sync_act_n_o    : out   std_logic;                    -- stays OFF when ext_sync is not used
     led_sync_err_n_o    : out   std_logic;                    -- stays OFF when ext_sync is not used

    -- Test points
     tp1_o               : out   std_logic;                    -- connected to fd_rxd
     tp2_o               : out   std_logic;                    -- connected to fd_txd
     tp3_o               : out   std_logic;                    -- connected to MT led&dbg reg bit 8
     tp4_o               : out   std_logic;                    -- connected to MT led&dbg reg bit 9

    -- To be removed on hw V3
     adc_1v8_shdn_n_o    : out   std_logic;
     adc_m5v_shdn_n_o    : out   std_logic;
     adc_5v_en_n_o       : out   std_logic);
end spec_masterfip_pts;


--=================================================================================================
--                                    architecture declaration
--=================================================================================================
architecture rtl of spec_masterfip_pts is

---------------------------------------------------------------------------------------------------
--                                     MOCK TURTLE CONSTANTS                                     --
---------------------------------------------------------------------------------------------------
--  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-- HMQ: It total 10 HMQs have been defined. Each HMQ has 4 entries of 128 x 32 bits, each.

--   8 "out HMQs" from the MT -> towards the host
--     - 0: HMQ from CPU0 with the WorldFIP payloads from periodic consumed variables
--     - 1: HMQ from CPU0 with the WorldFIP payloads from aperiodic consumed variables
--         (only for the case of identif variable, scheduled as periodic variable, by radMon app)
--     - 2: HMQ from CPU0 with the WorldFIP payloads from aperiodic consumed messages
--     - 3: HMQ from CPU0 with the WorldFIP payloads from periodic consumed diagnostic variables
--         (only for the case of the FIPdiag variable 0x067F)
--     - 4: HMQ from CPU0 with the WorldFIP payloads from aperiodic consumed diagnostic variables
--         (aperiodic presence and identification)
--     - 5: HMQ for debugging data from CPU0 and CPU1 towards the host
--     - 6: HMQ for the responses of CPU0 to the commands of the host, see below "in HMQ0"
--         (e.g.: acknowledgement of the configuration???)
--     - 7: HMQ for the responses of CPU1 to the commands of the host, see below "in HMQ1",
--         (e.g.: content of the report variable)

--   2 "in HMQs" from the host -> towards MT
--     - 0: HMQ towards CPU0 with commands for the bus config, used only at startup (e.g.: HW_RESET,
--                                                                 PROGRAM_BA, BA_START, BA_RUNNING)
--     - 1: HMQ towards CPU1 with the payloads for produced WorldFIP frames (variables and messages;
--       CPU1 then puts this data into the Shared Memory for CPU0 to access and put them in the bus)
--       as well as requests for report data, requests for the scheduling of aperiodic traffic
--       (presence/ identification) etc (CPU1 again passes these requests into the Shared Memory).

  constant C_HMQ_CONFIG : t_wrn_mqueue_config :=
    (out_slot_count  => 8, -- MT -> towards the host
     out_slot_config =>
       (0 => (width => 128, entries => 4),
        1 => (width => 128, entries => 4),
        2 => (width => 128, entries => 4),
        3 => (width => 128, entries => 4),
        4 => (width => 128, entries => 4),
        5 => (width => 128, entries => 4),
	    6 => (width => 128, entries => 4),
        7 => (width => 128, entries => 4),
        others => (0, 0)),

     in_slot_count  => 2, -- host -> towards MT
     in_slot_config =>
       (0 => (width => 128, entries => 4),
        1 => (width => 128, entries => 4),
        others => (0, 0)));

--  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-- RMQs not used!
  constant C_RMQ_CONFIG : t_wrn_mqueue_config :=
    (out_slot_count  => 0,
     out_slot_config => (others => (0, 0)),
     in_slot_count   => 0,
     in_slot_config  => (others => (0, 0)));

--  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
  constant C_NODE_CONFIG : t_wr_node_config :=
    (app_id          => x"0f1dc03e",
     cpu_count       => 1,
     cpu_memsizes    => (98304, 0, 0, 0, 0, 0, 0, 0), -- in bytes; for CPU0 the size should be enough
                                                         -- for the storage of the RT sw running on CPU0
                                                         -- and for the macrocycle configuration
     hmq_config      => C_HMQ_CONFIG,
     rmq_config      => C_RMQ_CONFIG,
     shared_mem_size => 65536); -- in bytes

      -- SPEC carrier CSR constants
  constant c_CARRIER_TYPE : std_logic_vector(15 downto 0) := X"0001";


--  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-- crossbar constants
    constant c_NUM_WB_SLAVES           : integer := 4;
    constant    c_WB_SLAVE_MF_CORE     : integer := 0;
    constant    c_WB_SLAVE_STATUS_CSR  : integer := 1;
    constant    c_WB_SLAVE_FMC_I2C     : integer := 2;
    constant    c_WB_SLAVE_MF_PTS_CSR  : integer := 3;

    

  constant C_SLAVE_ADDR : t_wishbone_address_array(c_NUM_WB_SLAVES-1 downto 0):= (
        c_WB_SLAVE_MF_CORE          => x"00010000",
        c_WB_SLAVE_STATUS_CSR       => x"00011000",
        c_WB_SLAVE_FMC_I2C          => x"00012000",
        c_WB_SLAVE_MF_PTS_CSR       => x"00013000"
        );
  constant C_SLAVE_MASK : t_wishbone_address_array(c_NUM_WB_SLAVES-1 downto 0):= (
        c_WB_SLAVE_MF_CORE          => x"fffff000",
        c_WB_SLAVE_STATUS_CSR       => x"fffff000",
        c_WB_SLAVE_FMC_I2C          => x"fffff000",
        c_WB_SLAVE_MF_PTS_CSR       => x"fffff000"
        );


---------------------------------------------------------------------------------------------------
--                                            Signals                                            --
---------------------------------------------------------------------------------------------------
  -- clk, reset
  signal clk_100m_sys           : std_logic;
  signal rst_n_sys              : std_logic;
  -- Mock Turtle
  signal wbmain_masters_ms        : t_wishbone_master_out_array(1 downto 0);
  signal wbmain_masters_sm         : t_wishbone_master_in_array(1 downto 0);
  signal wbmain_slaves_ms       : t_wishbone_master_out_array(c_NUM_WB_SLAVES-1 downto 0);
  signal wbmain_slaves_sm        : t_wishbone_master_in_array(c_NUM_WB_SLAVES-1 downto 0);
  -- SPEC LEDs
  signal led_divider            : unsigned(22 downto 0);
  signal leds                   : std_logic_vector(31 downto 0);
  signal spec_led               : std_logic_vector(7 downto 0);
  signal fd_txd                 : std_logic;

  -- Mezzanine system I2C for EEPROM
  signal sys_scl_in   : std_logic;
  signal sys_scl_out  : std_logic;
  signal sys_scl_oe_n : std_logic;
  signal sys_sda_in   : std_logic;
  signal sys_sda_out  : std_logic;
  signal sys_sda_oe_n : std_logic;
  
  signal rst_sys        : std_logic;
  signal fd_txd_corrupt        : std_logic;


--=================================================================================================
--                                       architecture begin
--=================================================================================================
begin

---------------------------------------------------------------------------------------------------
--                                        FIXED SIGNALS                                          --
---------------------------------------------------------------------------------------------------
  -- ext_sync_dir_o    <= '0'; -- Direction fixed to: B -> A
  -- ext_sync_oe_n_o   <= '0'; -- Output fixed to: enabled

  -- To be removed on hw V3
  -- Note: For the hw v1 signals ext_sync_tst_n_o, adc_prim_conn_n_o and adc_sec_conn_n_o, in order
  -- to disable them (that is set them to 'Z'), the ISE setting "Unused IOB pins" is set to 
  -- "floating", so there is no need to declare them.
  adc_1v8_shdn_n_o  <= '0'; -- OFF
  adc_m5v_shdn_n_o  <= '0'; -- OFF
  adc_5v_en_n_o     <= '1'; -- OFF

  rst_sys       <= not rst_n_sys;

---------------------------------------------------------------------------------------------------
--                                      MOCK TURTLE CORE                                         --
---------------------------------------------------------------------------------------------------
  cmp_mock_turtle : spec_node_template
  generic map
    (g_simulation               => g_simulation,
     g_with_wr_phy              => false,     -- no White Rabbit support, dah
     g_with_white_rabbit        => false,
     g_double_wrnode_core_clock => false,
     g_system_clock_freq        => 100000000, -- both CPUs at 100 MHz
     g_wr_node_config           => C_NODE_CONFIG)
  port map
    (clk_125m_pllref_p_i => clk_125m_pllref_p_i,
     clk_125m_pllref_n_i => clk_125m_pllref_n_i,
     rst_n_sys_o         => rst_n_sys,    -- PCIe rst, synced with clk_sys
     clk_sys_o           => clk_100m_sys, -- 100 MHz; one clk domain in the whole design
     -- PCIe interface
     l_rst_n             => l_rst_n_i,
     gpio                => gpio_b,
     p2l_rdy             => p2l_rdy_o,
     p2l_clkn            => p2l_clkn_i,
     p2l_clkp            => p2l_clkp_i,
     p2l_data            => p2l_data_i,
     p2l_dframe          => p2l_dframe_i,
     p2l_valid           => p2l_valid_i,
     p_wr_req            => p_wr_req_i,
     p_wr_rdy            => p_wr_rdy_o,
     rx_error            => rx_error_o,
     l2p_data            => l2p_data_o,
     l2p_dframe          => l2p_dframe_o,
     l2p_valid           => l2p_valid_o,
     l2p_clkn            => l2p_clkn_o,
     l2p_clkp            => l2p_clkp_o,
     l2p_edb             => l2p_edb_o,
     l2p_rdy             => l2p_rdy_i,
     l_wr_rdy            => l_wr_rdy_i,
     p_rd_d_rdy          => p_rd_d_rdy_i,
     tx_error            => tx_error_i,
     vc_rdy              => vc_rdy_i,
     -- DAC interface
     dac_sclk_o          => dac_sclk_o,
     dac_din_o           => dac_din_o,
     dac_cs1_n_o         => dac_cs_n_o(0),
     dac_cs2_n_o         => dac_cs_n_o(1),
     -- FMC presence
     fmc_prsnt_m2c_l_i   => fmc_prsnt_m2c_n_i,
     -- WISHBONE connection of the fmc_masterFIP_core to the MT CPUs
     dp_master_o(0)      => wbmain_masters_ms(0), -- access from MT CPU0 at base address 0x100000
     -- dp_master_o(1)      => wbmain_masters_ms(1),
     dp_master_i(0)      => wbmain_masters_sm(0),  -- access from MT CPU1 at base address 0x100000
     -- dp_master_i(1)      => wbmain_masters_sm(1),
     -- WISHBONE connection of the fmc_masterFIP_core to the host
     fmc0_host_wb_o      => wbmain_masters_ms(1), -- access from PCIe host at base address 0x10000
     fmc0_host_wb_i      => wbmain_masters_sm(1),
     fmc0_host_irq_i     => '0',
     -- not used
     clk_20m_vcxo_i      => '0',
     clk_125m_gtp_n_i    => '0',
     clk_125m_gtp_p_i    => '1');


---------------------------------------------------------------------------------------------------
--                                             XBAR                                              --
---------------------------------------------------------------------------------------------------
-- Crossbar to give access to the fmc_masterFIP_core to CPU0, CPU1 and directly to the PCIe host.
-- Note that to give access to the fmc_masterFIP_core to both CPU0 and CPU1, the SP of MT could
-- have been used instead of the DP and this crossbar; this though would have also affected
-- (potentially slowed down) the accesses to the MT Shared Memory.
-- Note that in the MT firmware the CPU1 is only accessing the masterfip_leds register for debugging
-- purposes. The PCIe host is accessing the core directly only for testing purposes.
  cmp_wb_crossbar : xwb_crossbar
  generic map
    (g_num_masters => 2,
     g_num_slaves  => c_NUM_WB_SLAVES,
     g_registered  => true,
     g_address     => C_SLAVE_ADDR,
     g_mask        => C_SLAVE_MASK)
  port map
    (clk_sys_i     => clk_100m_sys,
     rst_n_i       => rst_n_sys,
     slave_i        => wbmain_masters_ms,
     slave_o        => wbmain_masters_sm,
     master_o       => wbmain_slaves_ms,
     master_i       => wbmain_slaves_sm
     );


---------------------------------------------------------------------------------------------------
--                                      FMC MASTERFIP CORE                                       --
---------------------------------------------------------------------------------------------------
  cmp_masterFIP_core : fmc_masterFIP_core
  generic map
    (g_span             => 32,
     g_width            => 32,
     values_for_simul   => g_simulation)
  port map
    (clk_i              => clk_100m_sys,
     rst_n_i            => rst_n_sys,
     -- FMC one-wire
     onewire_b          => fmc_onewire_b,
     -- WorldFIP speed
     speed_b0_i         => speed_b0_i,
     speed_b1_i         => speed_b1_i,
     -- FIELDRIVE
     fd_rxcdn_a_i       => fd_rxcdn_i,
     fd_rxd_a_i         => fd_rxd_i,
     fd_txer_a_i        => fd_txer_i,
     fd_wdgn_a_i        => fd_wdgn_i,
     fd_rstn_o          => fd_rstn_o,
     fd_txck_o          => fd_txck_o,
     fd_txd_o           => fd_txd,
     fd_txena_o         => fd_txena_o,
     -- External Synch
     ext_sync_term_en_o => open,
     ext_sync_a_i       => '0',
     ext_sync_dir_o     => open, -- hard-wired to '0'
     ext_sync_oe_n_o    => open, -- hard-wired to '0'
     -- LEDs
     leds_o             => leds,
     -- WISHBONE interface with MT CPU0 and CPU1
     wb_adr_i           => wbmain_slaves_ms(c_WB_SLAVE_MF_CORE).adr,
     wb_dat_i           => wbmain_slaves_ms(c_WB_SLAVE_MF_CORE).dat,
     wb_stb_i           => wbmain_slaves_ms(c_WB_SLAVE_MF_CORE).stb,
     wb_we_i            => wbmain_slaves_ms(c_WB_SLAVE_MF_CORE).we,
     wb_cyc_i           => wbmain_slaves_ms(c_WB_SLAVE_MF_CORE).cyc,
     wb_sel_i           => wbmain_slaves_ms(c_WB_SLAVE_MF_CORE).sel,
     wb_dat_o           => wbmain_slaves_sm(c_WB_SLAVE_MF_CORE).dat,
     wb_ack_o           => wbmain_slaves_sm(c_WB_SLAVE_MF_CORE).ack,
     wb_stall_o         => wbmain_slaves_sm(c_WB_SLAVE_MF_CORE).stall);

  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  -
  -- unused WISHBONE signals
  wbmain_slaves_sm(c_WB_SLAVE_MF_CORE).err   <= '0';
  wbmain_slaves_sm(c_WB_SLAVE_MF_CORE).rty   <= '0';
  wbmain_slaves_sm(c_WB_SLAVE_MF_CORE).int   <= '0';

  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  -
  led_rx_act_n_o        <= leds(0); -- probe on R4
  led_rx_err_n_o        <= leds(1); -- probe on R8
  led_tx_act_n_o        <= leds(2); -- probe on R4
  led_tx_err_n_o        <= leds(3); -- probe on R7
  led_sync_act_n_o      <= leds(4); -- probe on R1
  led_sync_err_n_o      <= leds(5); -- probe on R6

  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  -
  -- fd_txd_o             <= fd_txd;
  fd_txd_o                <= fd_txd when fd_txd_corrupt = '0' else '0';
  tp1_o                <= fd_rxd_i;
  tp2_o                <= fd_txd;
  tp3_o                <= leds(8);
  tp4_o                <= leds(9);


  ------------------------------------------------------------------------------
  -- Carrier CSR
  --    Carrier type and PCB version
  --    Bitstream (firmware) type and date
  --    Release tag
  --    VCXO DAC control (CLR_N)
  ------------------------------------------------------------------------------
  cmp_carrier_csr : entity work.carrier_csr
    port map(
      rst_n_i                          => rst_n_sys,
      clk_sys_i                        => clk_100m_sys,
      wb_adr_i                         => wbmain_slaves_ms(c_WB_SLAVE_STATUS_CSR).adr(3 downto 2),  -- wbmain_slaves_ms.adr is byte address
      wb_dat_i                         => wbmain_slaves_ms(c_WB_SLAVE_STATUS_CSR).dat,
      wb_dat_o                         => wbmain_slaves_sm(c_WB_SLAVE_STATUS_CSR).dat,
      wb_cyc_i                         => wbmain_slaves_ms(c_WB_SLAVE_STATUS_CSR).cyc,
      wb_sel_i                         => wbmain_slaves_ms(c_WB_SLAVE_STATUS_CSR).sel,
      wb_stb_i                         => wbmain_slaves_ms(c_WB_SLAVE_STATUS_CSR).stb,
      wb_we_i                          => wbmain_slaves_ms(c_WB_SLAVE_STATUS_CSR).we,
      wb_ack_o                         => wbmain_slaves_sm(c_WB_SLAVE_STATUS_CSR).ack,
      wb_stall_o                       => open,
      carrier_csr_carrier_pcb_rev_i    => pcb_ver_i,
      carrier_csr_carrier_reserved_i   => X"000",
      carrier_csr_carrier_type_i       => c_CARRIER_TYPE,
      carrier_csr_stat_fmc_pres_i      => fmc_prsnt_m2c_n_i,
      carrier_csr_stat_p2l_pll_lck_i   => '1',
      carrier_csr_stat_sys_pll_lck_i   => '1',
      carrier_csr_stat_ddr3_cal_done_i => '1',
      carrier_csr_ctrl_led_green_o     => open,
      carrier_csr_ctrl_led_red_o       => open,
      carrier_csr_ctrl_dac_clr_n_o     => open,
      carrier_csr_rst_fmc0_n_o         => open,
      carrier_csr_rst_fmc0_n_i         => '0',
      carrier_csr_rst_fmc0_n_load_o    => open
      );

  wbmain_slaves_sm(c_WB_SLAVE_STATUS_CSR).err   <= '0';
  wbmain_slaves_sm(c_WB_SLAVE_STATUS_CSR).rty   <= '0';
  wbmain_slaves_sm(c_WB_SLAVE_STATUS_CSR).int   <= '0';


 -- Mezzanine system managment I2C master
  --    Access to mezzanine EEPROM
  ------------------------------------------------------------------------------
    cmp_fmc_sys_i2c : xwb_i2c_master
    generic map(
        g_interface_mode            => CLASSIC,
        g_address_granularity       => BYTE
    )
    port map (
        clk_sys_i                   => clk_100m_sys,
        rst_n_i                     => rst_n_sys,

        slave_i                     => wbmain_slaves_ms(c_WB_SLAVE_FMC_I2C),
        slave_o                     => wbmain_slaves_sm(c_WB_SLAVE_FMC_I2C),
        desc_o                      => open,

        scl_pad_i(0)                => sys_scl_in,
        scl_pad_o(0)                => sys_scl_out,
        scl_padoen_o(0)             => sys_scl_oe_n,
        sda_pad_i(0)                => sys_sda_in,
        sda_pad_o(0)                => sys_sda_out,
        sda_padoen_o(0)             => sys_sda_oe_n
        );

      -- Tri-state buffer for SDA and SCL
    fmc_scl_io          <= sys_scl_out when sys_scl_oe_n = '0' else 'Z';
    sys_scl_in          <= fmc_scl_io;

    fmc_sda_io          <= sys_sda_out when sys_sda_oe_n = '0' else 'Z';
    sys_sda_in          <= fmc_sda_io;

  -- Tri-state buffer for SDA and SCL


  ---------------------------------------------------------
  ---- Module containing PTS cores
  ---------------------------------------------------------

    pts_core_inst: entity work.masterfip_pts
    port map(
        -- Clock and reset
        clk_i              => clk_100m_sys,
        rst_i              => rst_sys,   

        -- External synchronisation pulse transceiver
        ext_sync_term_en_o  => ext_sync_term_en_o,
        ext_sync_dir_o      => ext_sync_dir_o, 
        ext_sync_oe_n_o     => ext_sync_oe_n_o,
        ext_sync_io         => ext_sync_io,

        -- FielDrive
        fd_rxcdn_i         => fd_rxcdn_i,
        fd_txer_i          => fd_txer_i,
        fd_wdgn_i          => fd_wdgn_i,
        fd_txd_corrupt_o   => fd_txd_corrupt,

        -- WISHBONE classic bus interface
        slave_i            => wbmain_slaves_ms(c_WB_SLAVE_MF_PTS_CSR),
        slave_o            => wbmain_slaves_sm(c_WB_SLAVE_MF_PTS_CSR)
    );  

  
---------------------------------------------------------------------------------------------------
--                                     SPEC front panel LEDs                                     --
---------------------------------------------------------------------------------------------------
  drive_led_clk_sys: process (clk_100m_sys)
  begin
    if rising_edge(clk_100m_sys) then
      if(rst_n_sys = '0') then
        spec_led     <= "01111111";
        led_divider <= (others => '0');
      else
        led_divider <= led_divider+ 1;
        if(led_divider = 0) then
          spec_led   <= spec_led(6 downto 0) & spec_led(7);
        end if;
      end if;
    end if;
  end process;

  led_green_o <= spec_led(7);
  led_red_o   <= not rst_n_sys;


end rtl;
--=================================================================================================
--                                        architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
--                                      E N D   O F   F I L E
--------------------------------------------------------------------------------------------------