# masterfip_pts_csr

### FMC masterFIP PTS registers

Wishbone slave for FMC masterFIP PTS

### Contents:

1. Memory map summary
2. HDL symbol
3. Register description
3.1. rst
3.2. ext sync
3.3. PTS options
3.4. fieldrive status
3.5. fieldrive rx not carrier detect counter
3.6. fieldrive tx error counter

### 1. Memory map summary

H/W Address | Type | Name | VHDL/Verilog prefix | C prefix
--- | --- | --- | --- | ---
0x0 | REG | rst | mfpts_rst | RST
0x1 | REG | ext sync | mfpts_ext_sync | EXT_SYNC
0x2 | REG | PTS options | mfpts_tx_corrupt | TX_CORRUPT
0x3 | REG | fieldrive status | mfpts_fd | FD
0x4 | REG | fieldrive rx not carrier detect counter | mfpts_fd_rxcdn_cnt | FD_RXCDN_CNT
0x5 | REG | fieldrive tx error counter | mfpts_fd_txerr_cnt | FD_TXERR_CNT

### 2. HDL symbol

→ | rst_n_i |  | rst: |
→ | clk_sys_i |  | mfpts_rst_core_o | →
⇒ | wb_adr_i[2:0] |  |  |
⇒ | wb_dat_i[31:0] |  | ext sync: |
⇐ | wb_dat_o[31:0] |  | mfpts_ext_sync_term_en_o | →
→ | wb_cyc_i |  | mfpts_ext_sync_dir_o | →
⇒ | wb_sel_i[3:0] |  | mfpts_ext_sync_oe_o | →
→ | wb_stb_i |  | mfpts_ext_sync_output_value_o | →
→ | wb_we_i |  | mfpts_ext_sync_fpga_io_dir_o | →
← | wb_ack_o |  | mfpts_ext_sync_raw_input_i | ←
← | wb_stall_o |  |  |
|  |  | PTS options: |
|  |  | mfpts_tx_corrupt_enable_o | →
|  |  | fieldrive status: |
|  |  | mfpts_fd_wdgn_i | ←
|  |  | mfpts_fd_wdgn_latch_i | ←
|  |  | mfpts_fd_cd_n_i | ←
|  |  | mfpts_fd_txer_i | ←
|  |  | fieldrive rx not carrier detect counter: |
|  |  | mfpts_fd_rxcdn_cnt_i[31:0] | ⇐
|  |  | fieldrive tx error counter: |
|  |  | mfpts_fd_txerr_cnt_i[31:0] | ⇐

### 3. Register description

### 3.1. rst

HW prefix: | mfpts_rst
HW address: | 0x0
C prefix: | RST
C offset: | 0x0

software reset of the masterFIP core

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | CORE

- CORE [write-only]: reset of the masterFIP core
  write 1: generates a 1-clk-tick-long (10ns) masterFIP core reset;
  note: there is no need to clear the bit before writing another '1'

### 3.2. ext sync

HW prefix: | mfpts_ext_sync
HW address: | 0x1
C prefix: | EXT_SYNC
C offset: | 0x4

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | RAW_INPUT | FPGA_IO_DIR | OUTPUT_VALUE | OE | DIR | TERM_EN

- TERM_EN [read/write]: termination enable
  write 0: disable 50ohms termination of the external sync pulse
  write 1: enable 50ohms termination of the external sync pulse
- DIR [read/write]: transceiver direction
  write 0: normal operation (input)
  write 1: test mode where a pulse from the FPGA can be output to the front panel LEMO connector
- OE [read/write]: transceiver output enable
  This line is negated in the GW in order to correctly control the relay
  write 1: the external sync pulse arrives to the FPGA
  write 0: the external sync pulse does not arrive to the FPGA
- OUTPUT_VALUE [read/write]: External sync output value (when buffer is switched)
  Value outputted then sync is set to output direction
- FPGA_IO_DIR [read/write]: FPGA IO direction
  Direction of FPGA IO
- RAW_INPUT [read-only]: raw_input
  External sync input value. Only valid when direction is set to input

### 3.3. PTS options

HW prefix: | mfpts_tx_corrupt
HW address: | 0x2
C prefix: | TX_CORRUPT
C offset: | 0x8

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | ENABLE

- ENABLE [read/write]: enable
  When corrupt is set to 1 serial tx data is forced to 0.

### 3.4. fieldrive status

HW prefix: | mfpts_fd
HW address: | 0x3
C prefix: | FD
C offset: | 0xc

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | TXER | CD_N | WDGN_LATCH | WDGN

- WDGN [read-only]: fd watchdog
  fd_wdgn input from the fieldrive chip
- WDGN_LATCH [read-only]: fd watchdog latched
  Active watchdog state is latched. Register is reseted by reset core and reset fd
- CD_N [read-only]: fd carrier detect
  CDn input from the fieldrive chip
- TXER [read-only]: fd transmitter error
  fd_txer input from the fieldrive chip

### 3.5. fieldrive rx not carrier detect counter

HW prefix: | mfpts_fd_rxcdn_cnt
HW address: | 0x4
C prefix: | FD_RXCDN_CNT
C offset: | 0x10

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
FD_RXCDN_CNT[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
FD_RXCDN_CNT[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
FD_RXCDN_CNT[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
FD_RXCDN_CNT[7:0] |  |  |  |  |  |  |

- FD_RXCDN_CNT [read-only]: fieldrive rx not carrier detect counter
  Number of RX NOT carrier detect periods. Counter is reset by macrocycle, core reset and fd reset

### 3.6. fieldrive tx error counter

HW prefix: | mfpts_fd_txerr_cnt
HW address: | 0x5
C prefix: | FD_TXERR_CNT
C offset: | 0x14

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
FD_TXERR_CNT[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
FD_TXERR_CNT[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
FD_TXERR_CNT[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
FD_TXERR_CNT[7:0] |  |  |  |  |  |  |

- FD_TXERR_CNT [read-only]: fieldrive tx error counter
  Number of TX Errors. Counter is reset by macrocycle, core reset and fd reset