masterFIP Software
Overview
Following the evaluation of different implementation solutions, the technical choice for the masterFIP design was the use of Mock Turtle (also referred to as White Rabbit Node Core).
Mock Turtle is a HDL core of a generic distributed control system node,
based on multiple deterministic CPU cores where the users can run
any sort of hard real time applications.
The applications can be written in bare metal C, using standard GNU
tool set, cross-compiled and loaded into the CPUs. The CPUs can
communicate between each other through
a dedicated Shared Memory and with the host through Host Message
Queues.
This project includes:
- the real-time software, written in bare-metal C, running in the embedded CPUs
- the associated libraries that ease the developmet of applications
- example application
In this design Mock Turtle has been configured as the following table shows:
Parameter | Value |
CPUs | CPU0, CPU1: running at 100 MHz |
White Rabbit Support | No |
Remote Message Queues | 0 |
CPU0 memory size | 98304 bytes |
CPU1 memory size | 8192 bytes |
Shared Memory size | 65536 bytes |
Host Message Queues from MT -> host | 8 |
Host Message Queues from host -> MT | 2 |
CPU0* is the heart of the design; its purpose it to “play" in a
deterministic way the WorldFIP macrocycle.
For example, it initiates the delivery of a WorldFIP question frame, by
providing the frame bytes to the fmc_masterfip_core,
and then awaits for the reception of the response frame. It retrieves
the consumed data from the fmc_masterfip_core, packs them
in the corresponding HMQ (according to the frame type) and can notify
the host through an IRQ.
The main interaction between the host and CPU0 is for the macrocycle
configuration. This in principle takes place only once at startup,
where
CPU0 is LOADed through a dedicated HMQ (RD HMQ0) with the macrocycle
configuration, for example: the number and size of produced/ consumed
variables, the lengths of periodic/aperiodic windows etc.
The following figure shows the states of the CPU0 state machine. During
WorldFIP operation the state machine is at “RUNNING” state.
Note that at the end of every window (periodic/aperiodic window of a
macrocycle) CPU0 is also polling RD HMQ0 to check for a RESET/
STOP.
https://www.ohwr.org/5016
CPU0 state machine*
CPU1 is mainly polling the host to retrieve new payload bytes for
production. When new data is received from the host through a dedicated
HMQ,
CPU1 puts them into the Shared Memory for CPU0 to retrieve them and
provide them to the fmc_masterFIP_core for serialization.
CPU1 does not need access to the fmc_masterFIP_core; however, access
is possible for debugging
purposes.
Mock Turtle configuration and main modules*
Documents
Project Status
Contacts
E.Gousiou, 27 February 2017