wip: corrected mistake on mem sizes (before it was half of what is needed), but now design does not fit /!\

changed wbgen reg with FPGA vers from 02.00.00 to 02.01.00 to reflect the change to urv; note no change in wb regs i/f

The comment reflects only on the generated html file; no source code change

corrected core_rst_n that was used instead of core_rst for the counting of the number of macrocycles and the counting of crc errors

corrected core_rst_n that was used instead of core_rst for the counting of the number of macrocycles and the counting of crc errors

- updated gitignore to allow for wbgen2 html

WIP: added 2 more rx status bits: one activated upon CTRL byte reception and one upon detection of more bytes than the max frame size

added more bits to tx and rx bytes counters so as to be compatible with the PTS that needs to send 1024 bytes.

removed sw folder; changed general-cores branch (tom-proposed-master-feb28; unused IOBs set to floating; clean up counters