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MasterFIP - Gateware
Commit fbc6ed5a authored by Evangelia Gousiou's avatar Evangelia Gousiou
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synthesized for the new proto fmc-worldfip boards 

small changes on signals names of fmc_masterfip_csr
parent 269d2738
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Showing with 137 additions and 55 deletions
rtl/fmc_masterFIP_core.vhd
View file @ fbc6ed5a
......@@ -65,7 +65,11 @@ entity fmc_masterFIP_core is
clk_i : in std_logic; --
rst_i : in std_logic; --
-- FielDrive
-- Bus Speed
speed_b0_i : in std_logic;
speed_b1_i : in std_logic;
-- FielDrive
fd_rxcdn_i : in std_logic;
fd_rxd_i : in std_logic;
fd_txer_i : in std_logic;
......@@ -109,6 +113,7 @@ architecture rtl of fmc_masterFIP_core is
signal rx_fss_received_p, rx_fss_crc_fes_ok_p : std_logic;
signal rx_crc_wrong_p, rx_byte_ready_p : std_logic;
signal rx_byte : std_logic_vector (7 downto 0);
signal rx_data_bytes : std_logic_vector (8 downto 0);
-- wf_production outputs
signal byte_to_tx : std_logic_vector (7 downto 0);
-- masterfip_tx outputs
......@@ -118,6 +123,9 @@ architecture rtl of fmc_masterFIP_core is
signal core_sw_rst, fd_sw_rst : std_logic;
signal core_sw_rst_p, core_sw_rst_n, fd_sw_rst_n : std_logic;
signal core_sw_rstn_lock : std_logic_vector (15 downto 0);
-- speed
signal speed_host : std_logic_vector (1 downto 0);
signal speed_ok : std_logic;
-- counters
signal macrocyc_lgth, turnar_lgth, silen_lgth : std_logic_vector (30 downto 0);
signal macrocyc_sw_load, turnar_sw_load, silen_sw_load : std_logic;
......@@ -185,11 +193,11 @@ begin
mf_rst_lock_o => core_sw_rstn_lock,
mf_rst_lock_wr_o => core_sw_rst_p,
-- config
mf_config_host_bitrate_o => open,--host_bitrate_conf,
mf_config_host_speed_o => speed_host,
mf_config_host_ext_sync_term_en_n_o => open,
mf_config_host_subs_o => open,
mf_config_fmc_bitrate_i => "01",--fmc_bitrate_conf,
mf_config_fmc_bitrate_ok_i => '1', --bitrate_ok,
mf_config_fmc_speed_i => speed_b1_i & speed_b0_i,
mf_config_fmc_speed_ok_i => speed_ok,
-- counters outputs
mf_macrocyc_lgth_o => macrocyc_lgth,
mf_macrocyc_start_o => macrocyc_sw_load,
......@@ -216,7 +224,7 @@ begin
mf_rx_frame_ok_i => rx_frame_ok_p, -- have to extend the pulse
mf_rx_frame_err_i => '0',
mf_rx_frame_err_code_i => "000",
mf_rx_bytes_num_i => '0' & rx_byte_index,
mf_rx_bytes_num_i => rx_data_bytes,
-- rx data
mf_rx_data_ctrl_i => rx_ctrl_byte,
mf_rx_data_reg1_i => rx_frame(0),
......@@ -286,7 +294,7 @@ begin
mf_tx_data_reg31_o => tx_frame(30),
mf_tx_data_reg32_o => tx_frame(31));
speed_ok <= '1' when speed_b1_i & speed_b0_i = speed_host else '0';
---------------------------------------------------------------------------------------------------
-- resets --
---------------------------------------------------------------------------------------------------
......@@ -394,7 +402,7 @@ begin
--------------------------------------------------------------------------------------------------
cmp_rx_extend_p : gc_extend_pulse
generic map (
g_width => 5000000)
g_width => 16)
port map (
clk_i => clk_i,
rst_n_i => rst_n,
......@@ -432,7 +440,8 @@ begin
rx_crc_wrong_p_o => rx_crc_wrong_p);
-------------------------------------------------------------
rx_data_bytes <= '0' & (std_logic_vector(unsigned(rx_byte_index)-4));
-- actual size of data bytes (without preamble, postamble, ctrl, CRC); check with an RP_FIN if ok!
---------------------------------------------------------------------------------------------------
-- tx --
---------------------------------------------------------------------------------------------------
......@@ -465,7 +474,7 @@ fd_txena_o <= fd_txena;
-- aux --
---------------------------------------------------------------------------------------------------
aux_o <= "0000000" & tx_start_p;
aux_o <= "00000" & rx_crc_wrong_p & rx_byte_ready_p & tx_start_p;
---------------------------------------------------------------------------------------------------
-- CHIPSCOPE --
---------------------------------------------------------------------------------------------------
......
rtl/fmc_masterFIP_mezz.vhd
View file @ fbc6ed5a
......@@ -102,6 +102,9 @@ entity fmc_masterFIP_mezz is
(-- Clock & reset 40MHz
clk_sys_i : in std_logic; -- 40 MHz clock
rst_sys_n_i : in std_logic; -- reset for 40 MHz logic
-- Bus Speed
speed_b0_i : in std_logic;
speed_b1_i : in std_logic;
-- FielDrive
fd_rxcdn_i : in std_logic;
fd_rxd_i : in std_logic;
......@@ -243,6 +246,9 @@ begin
(-- clks, rst
clk_i => clk_sys_i,
rst_i => not (rst_sys_n_i),
-- Bus Speed
speed_b0_i => speed_b0_i,
speed_b1_i => speed_b1_i,
-- FielDrive
fd_rxcdn_i => fd_rxcdn_i,
fd_rxd_i => fd_rxd_i,
......
rtl/fmc_masterfip_csr.vhd
View file @ fbc6ed5a
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fmc_masterfip_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_masterfip_csr.wb
-- Created : 07/21/15 11:01:11
-- Created : 07/23/15 17:04:12
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_masterfip_csr.wb
......@@ -34,16 +34,16 @@ entity fmc_masterfip_csr is
-- Ports for PASS_THROUGH field: 'reset magic value' in reg: 'rst'
mf_rst_lock_o : out std_logic_vector(15 downto 0);
mf_rst_lock_wr_o : out std_logic;
-- Port for std_logic_vector field: 'bit rate' in reg: 'config from host'
mf_config_host_bitrate_o : out std_logic_vector(1 downto 0);
-- Port for std_logic_vector field: 'speed' in reg: 'config from host'
mf_config_host_speed_o : out std_logic_vector(1 downto 0);
-- Port for BIT field: 'termination enable on the external synch input' in reg: 'config from host'
mf_config_host_ext_sync_term_en_n_o : out std_logic;
-- Port for std_logic_vector field: 'station address' in reg: 'config from host'
mf_config_host_subs_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'bit rate' in reg: 'config from fmc'
mf_config_fmc_bitrate_i : in std_logic_vector(1 downto 0);
-- Port for BIT field: 'bit rate match' in reg: 'config from fmc'
mf_config_fmc_bitrate_ok_i : in std_logic;
-- Port for std_logic_vector field: 'speed' in reg: 'config from fmc'
mf_config_fmc_speed_i : in std_logic_vector(1 downto 0);
-- Port for BIT field: 'speed match' in reg: 'config from fmc'
mf_config_fmc_speed_ok_i : in std_logic;
-- Port for std_logic_vector field: 'macrocycle lgth' in reg: 'macrocycle lgth'
mf_macrocyc_lgth_o : out std_logic_vector(30 downto 0);
-- Port for BIT field: 'macrocycle cnt start' in reg: 'macrocycle lgth'
......@@ -227,7 +227,7 @@ architecture syn of fmc_masterfip_csr is
signal mf_rst_core_int : std_logic ;
signal mf_rst_fd_int : std_logic ;
signal mf_config_host_bitrate_int : std_logic_vector(1 downto 0);
signal mf_config_host_speed_int : std_logic_vector(1 downto 0);
signal mf_config_host_ext_sync_term_en_n_int : std_logic ;
signal mf_config_host_subs_int : std_logic_vector(7 downto 0);
signal mf_macrocyc_lgth_int : std_logic_vector(30 downto 0);
......@@ -303,7 +303,7 @@ begin
mf_rst_core_int <= '0';
mf_rst_fd_int <= '0';
mf_rst_lock_wr_o <= '0';
mf_config_host_bitrate_int <= "00";
mf_config_host_speed_int <= "00";
mf_config_host_ext_sync_term_en_n_int <= '0';
mf_config_host_subs_int <= "00000000";
mf_macrocyc_lgth_int <= "0000000000000000000000000000000";
......@@ -411,11 +411,11 @@ begin
ack_in_progress <= '1';
when "0000010" =>
if (wb_we_i = '1') then
mf_config_host_bitrate_int <= wrdata_reg(1 downto 0);
mf_config_host_speed_int <= wrdata_reg(1 downto 0);
mf_config_host_ext_sync_term_en_n_int <= wrdata_reg(2);
mf_config_host_subs_int <= wrdata_reg(15 downto 8);
end if;
rddata_reg(1 downto 0) <= mf_config_host_bitrate_int;
rddata_reg(1 downto 0) <= mf_config_host_speed_int;
rddata_reg(2) <= mf_config_host_ext_sync_term_en_n_int;
rddata_reg(15 downto 8) <= mf_config_host_subs_int;
rddata_reg(3) <= 'X';
......@@ -444,8 +444,8 @@ begin
when "0000011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(1 downto 0) <= mf_config_fmc_bitrate_i;
rddata_reg(31) <= mf_config_fmc_bitrate_ok_i;
rddata_reg(1 downto 0) <= mf_config_fmc_speed_i;
rddata_reg(31) <= mf_config_fmc_speed_ok_i;
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
......@@ -1196,14 +1196,14 @@ begin
-- reset magic value
-- pass-through field: reset magic value in register: rst
mf_rst_lock_o <= wrdata_reg(31 downto 16);
-- bit rate
mf_config_host_bitrate_o <= mf_config_host_bitrate_int;
-- speed
mf_config_host_speed_o <= mf_config_host_speed_int;
-- termination enable on the external synch input
mf_config_host_ext_sync_term_en_n_o <= mf_config_host_ext_sync_term_en_n_int;
-- station address
mf_config_host_subs_o <= mf_config_host_subs_int;
-- bit rate
-- bit rate match
-- speed
-- speed match
-- macrocycle lgth
mf_macrocyc_lgth_o <= mf_macrocyc_lgth_int;
-- macrocycle cnt start
......
rtl/masterFIP_pkg.vhd
View file @ fbc6ed5a
......@@ -202,6 +202,8 @@ package masterFIP_pkg is
port
(clk_sys_i : in std_logic;
rst_sys_n_i : in std_logic;
speed_b0_i : in std_logic;
speed_b1_i : in std_logic;
fd_rxcdn_i : in std_logic;
fd_rxd_i : in std_logic;
fd_txer_i : in std_logic;
......@@ -243,11 +245,11 @@ package masterFIP_pkg is
mf_rst_fd_o : out std_logic;
mf_rst_lock_o : out std_logic_vector(15 downto 0);
mf_rst_lock_wr_o : out std_logic;
mf_config_host_bitrate_o : out std_logic_vector(1 downto 0);
mf_config_host_speed_o : out std_logic_vector(1 downto 0);
mf_config_host_ext_sync_term_en_n_o : out std_logic;
mf_config_host_subs_o : out std_logic_vector(7 downto 0);
mf_config_fmc_bitrate_i : in std_logic_vector(1 downto 0);
mf_config_fmc_bitrate_ok_i : in std_logic;
mf_config_fmc_speed_i : in std_logic_vector(1 downto 0);
mf_config_fmc_speed_ok_i : in std_logic;
mf_macrocyc_lgth_o : out std_logic_vector(30 downto 0);
mf_macrocyc_start_o : out std_logic;
mf_turnar_lgth_o : out std_logic_vector(30 downto 0);
......@@ -347,6 +349,8 @@ package masterFIP_pkg is
port
(clk_i : in std_logic;
rst_i : in std_logic;
speed_b0_i : in std_logic;
speed_b1_i : in std_logic;
fd_rxcdn_i : in std_logic;
fd_rxd_i : in std_logic;
fd_txer_i : in std_logic;
......
rtl/wbgen/fmc_masterfip_csr.wb
View file @ fbc6ed5a
......@@ -71,9 +71,9 @@ peripheral {
prefix = "config_host";
field {
name = "bit rate";
description = "WorldFIP bit rate: 00: 31.25Kbps | 01: 1Mbps | 10: 2.5 Mbps | 11: not used";
prefix = "bitrate";
name = "speed";
description = "WorldFIP speed: 00: 31.25Kbps | 01: 1Mbps | 10: 2.5 Mbps | 11: not used";
prefix = "speed";
type = SLV;
size = 2;
access_bus = READ_WRITE;
......@@ -112,9 +112,9 @@ peripheral {
prefix = "config_fmc";
field {
name = "bit rate";
description = "WorldFIP bit rate: 00: 31.25Kbps | 01: 1Mbps | 10: 2.5 Mbps | 11: not used";
prefix = "bitrate";
name = "speed";
description = "WorldFIP speed: 00: 31.25Kbps | 01: 1Mbps | 10: 2.5 Mbps | 11: not used";
prefix = "speed";
type = SLV;
size = 2;
access_bus = READ_ONLY;
......@@ -122,10 +122,10 @@ peripheral {
};
field {
name = "bit rate match";
name = "speed match";
description = "read 0: configuration from host and from fmc board mismatch\
read 1: configuration from host and from fmc board match";
prefix = "bitrate_ok";
prefix = "speed_ok";
type = BIT;
align = 31;
access_bus = READ_ONLY;
......
top/spec/spec_masterFIP.ucf
View file @ fbc6ed5a
......@@ -24,30 +24,50 @@ TIMESPEC TS_p2l_clk_n_i = PERIOD "p2l_clk_n_i" 5 ns HIGH 50%;
# This section has bee generated automatically by ucfgen.py. Do not hand-modify if not really necessary.
# ucfgen pin assignments for mezzanine fmc-tdc-v3 slot 0
NET "fd_rstn_o" LOC = "W11";
NET "fd_rstn_o" LOC = "Y18";
NET "fd_rstn_o" IOSTANDARD = "LVCMOS25";
NET "fd_txd_o" LOC = "Y6";
NET "fd_txd_o" LOC = "T14";
NET "fd_txd_o" IOSTANDARD = "LVCMOS25";
NET "fd_txck_o" LOC = "T8";
NET "fd_txck_o" LOC = "W17";
NET "fd_txck_o" IOSTANDARD = "LVCMOS25";
NET "fd_txer_i" LOC = "U8";
NET "fd_txer_i" LOC = "T11";
NET "fd_txer_i" IOSTANDARD = "LVCMOS25";
NET "fd_rxcdn_i" LOC = "U9";
NET "fd_rxcdn_i" LOC = "T15";
NET "fd_rxcdn_i" IOSTANDARD = "LVCMOS25";
NET "fd_rxd_i" LOC = "V9";
NET "fd_rxd_i" LOC = "U15";
NET "fd_rxd_i" IOSTANDARD = "LVCMOS25";
NET "fd_wdgn_i" LOC = "W10";
NET "fd_wdgn_i" LOC = "R11";
NET "fd_wdgn_i" IOSTANDARD = "LVCMOS25";
NET "fd_txena_o" LOC = "Y10";
NET "fd_txena_o" LOC = "R13";
NET "fd_txena_o" IOSTANDARD = "LVCMOS25";
NET "speed_b0_i" LOC = Y5;
NET "speed_b0_i" IOSTANDARD = "LVCMOS25";
NET "speed_b1_i" LOC = AB5;
NET "speed_b1_i" IOSTANDARD = "LVCMOS25";
NET "led_tx_err_n_o" LOC = C19;
NET "led_tx_err_n_o" IOSTANDARD = "LVCMOS25";
NET "led_tx_act_n_o" LOC = A19;
NET "led_tx_act_n_o" IOSTANDARD = "LVCMOS25";
NET "led_rx_err_n_o" LOC = B20;
NET "led_rx_err_n_o" IOSTANDARD = "LVCMOS25";
NET "led_rx_act_n_o" LOC = A20;
NET "led_rx_act_n_o" IOSTANDARD = "LVCMOS25";
#NET "mezz_onewire_b" LOC = "A19";
#NET "mezz_onewire_b" IOSTANDARD = "LVCMOS25";
# <ucfgen_end>
......@@ -193,6 +213,14 @@ NET "pcb_ver_i[2]" LOC = AA2;
NET "pcb_ver_i[2]" IOSTANDARD = "LVCMOS15";
NET "pcb_ver_i[3]" LOC = AA1;
NET "pcb_ver_i[3]" IOSTANDARD = "LVCMOS15";
NET "pcb_ver_i[0]" LOC = P5;
NET "pcb_ver_i[0]" IOSTANDARD = "LVCMOS15";
NET "pcb_ver_i[1]" LOC = P4;
NET "pcb_ver_i[1]" IOSTANDARD = "LVCMOS15";
NET "pcb_ver_i[2]" LOC = AA2;
NET "pcb_ver_i[2]" IOSTANDARD = "LVCMOS15";
NET "pcb_ver_i[3]" LOC = AA1;
NET "pcb_ver_i[3]" IOSTANDARD = "LVCMOS15";
#----------------------------------------
# FMC Presence
......
top/spec/spec_masterFIP.vhd
View file @ fbc6ed5a
......@@ -144,6 +144,10 @@ entity spec_masterFIP is
irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO 8
irq_aux_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO 9, aux signal
-- Bus Speed
speed_b0_i : in std_logic;
speed_b1_i : in std_logic;
-- FielDrive
fd_rxcdn_i : in std_logic;
fd_rxd_i : in std_logic;
......@@ -153,11 +157,16 @@ entity spec_masterFIP is
fd_txck_o : out std_logic;
fd_txd_o : out std_logic;
fd_txena_o : out std_logic;
-- font panel leds (not used)
led_red_o : out std_logic;
led_green_o : out std_logic;
-- LEDs mezzanine
led_tx_err_n_o : out std_logic;
led_tx_act_n_o : out std_logic;
led_rx_err_n_o : out std_logic;
led_rx_act_n_o : out std_logic;
-- LEDs spec
led_green_o : out std_logic;
led_red_o : out std_logic;
-- Carrier other signals
pcb_ver_i : in std_logic_vector(3 downto 0); -- PCB version
prsnt_m2c_n_i : in std_logic); -- Mezzanine presence (active low)
......@@ -239,6 +248,7 @@ architecture rtl of spec_masterFIP is
-- LEDs
signal led_clk_40m_divider : unsigned(22 downto 0);
signal led_clk_40m_aux : std_logic_vector(7 downto 0);
signal rx_err, rx_act, fd_txena : std_logic;
--=================================================================================================
......@@ -307,8 +317,6 @@ begin
rst_n_o => rst_sys_n);
-- -- -- -- -- -- -- -- -- --
rst_sys <= not rst_sys_n;
-- -- -- -- -- -- -- -- -- --
fd_rstn_o <= rst_sys_n;
---------------------------------------------------------------------------------------------------
-- CSR WISHBONE CROSSBAR --
......@@ -426,10 +434,12 @@ begin
fd_rxd_i => fd_rxd_i,
fd_txer_i => fd_txer_i,
fd_wdgn_i => fd_wdgn_i,
fd_rstn_o => open,
fd_rstn_o => fd_rstn_o,
fd_txck_o => fd_txck_o,
fd_txd_o => fd_txd_o,
fd_txena_o => fd_txena_o,
fd_txena_o => fd_txena,
speed_b0_i => speed_b0_i,
speed_b1_i => speed_b1_i,
-- WISHBONE interface with the GN4124 core
wb_adr_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).adr,
wb_dat_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).dat,
......@@ -450,7 +460,32 @@ begin
cnx_master_in(c_WB_SLAVE_MASTERFIP).rty <= '0';
cnx_master_in(c_WB_SLAVE_MASTERFIP).int <= '0';
fd_txena_o <= fd_txena;
-- LEDs font panel
led_tx_err_n_o <= fd_txer_i;
led_tx_act_n_o <= fd_txena;
led_rx_err_n_o <= rx_err;
led_rx_act_n_o <= rx_act;
cmp_rx_err_extend_p : gc_extend_pulse
generic map (
g_width => 50000)
port map (
clk_i => clk_40m_sys,
rst_n_i => rst_sys_n,
pulse_i => aux(2),
extended_o => rx_err);
cmp_rx_act_extend_p : gc_extend_pulse
generic map (
g_width => 50000)
port map (
clk_i => clk_40m_sys,
rst_n_i => rst_sys_n,
pulse_i => aux(1),
extended_o => rx_act);
---------------------------------------------------------------------------------------------------
-- VIC --
---------------------------------------------------------------------------------------------------
......
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