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MasterFIP - Gateware
Commit aae395c5 authored by Evangelia Gousiou's avatar Evangelia Gousiou
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updated testbench to support nanofip in memory mode

parent 71c1e137
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sim/spec/data_vectors/WFIP_communication_config.txt 0 → 100644
View file @ aae395c5
1 -- bit rate: 31.25 kbit/s(0), 1 Mbit/s(1), 2.5 Mbit/s(2)
10001110111001111 -- gx bit polynomial for CRC
101010101XX10XX0 -- FSS value
1XXXX101 -- FES value
03 -- id_dat frame control byte
02 -- rp_dat frame control byte
14 -- Presence Variable address
10 -- Identification Variable address
91 -- Broadcast Variable address
05 -- Consumed Variable address
06 -- Produced Variable address
E0 -- Reset Variable address
40 -- pdu_type byte
05 -- mps byte
2000 ms -- time for which the configuration above is valid
sim/spec/data_vectors/board_settings_config.txt 0 → 100644
View file @ aae395c5
vcc -- c_id_3 can take the values (gnd, vcc, sd0, sd1)
sd0 -- c_id_2 can take the values (gnd, vcc, sd0, sd1)
sd1 -- c_id_1 can take the values (gnd, vcc, sd0, sd1)
gnd -- c_id_0 can take the values (gnd, vcc, sd0, sd1)
gnd -- m_id_3 can take the values (gnd, vcc, sd0, sd1)
sd1 -- m_id_2 can take the values (gnd, vcc, sd0, sd1)
sd0 -- m_id_1 can take the values (gnd, vcc, sd0, sd1)
vcc -- m_id_0 can take the values (gnd, vcc, sd0, sd1)
1 -- nostat: nanoFIP status enabled(0), nanoFIP status disabled(1)
000 -- produced variable length: 2 bytes(000), 8 bytes(001), 16 bytes(010), 32 bytes(011), 64 bytes(100), 124 bytes(101)
01 -- rate: 31.25 kbits(00), 1 Mbit(01), 2.5 Mbits(10)
0 -- mode (slone): memory mode(0), stand alone(1)
03 -- station_adr (8-bit bus in hexadecimal format)
20000 ms -- time for which the configuration above is valid
sim/spec/data_vectors/errors_config.txt 0 → 100644
View file @ aae395c5
FALSE -- Truncate preamble
FALSE -- Insert violation error for one clk cycle
0 ps -- Jitter error inserted on the manchester encoded signal
0 -- Number of bits per byte truncated in reception (integer 1 to 8)
0 ps -- TXERR error length
0 ps -- WDGN error length
20000 ms --++ time for which the configuration above is valid
sim/spec/data_vectors/masterFIP_test.vec
View file @ aae395c5
-------------------------------------------------------------------------------
-- masterFIP_test.vec
-------------------------------------------------------------------------------
-- Select the GN4124 Primary BFM
model 0
......@@ -14,6 +14,7 @@ init
-- bar BAR ADDR SIZE VC TC S
bar 0 0000000000000000 00100000 0 7 0
-- This allocates a RAM block inside the BFM for the FPGA to access
-- bfm_bar BAR ADDR SIZE
bfm_bar 0 0000000040000000 20000000
......@@ -57,7 +58,7 @@ wait %d20
--------------- ID_DAT ---------------
tx_rst
-- tx_rst
wr 0000000000030034 F 00000001
wait %d10
wr 0000000000030034 F 00000000
......@@ -77,7 +78,7 @@ wait %d20000
--------------- RP_DAT ---------------
tx_rst
-- tx_rst
wr 0000000000030034 F 00000001
wait %d10
wr 0000000000030034 F 00000000
......@@ -88,11 +89,11 @@ wr 0000000000030154 F 00000002
wait %d20
-- data bytes
wr 0000000000030158 F BBAA0340
wr 0000000000030158 F BBAA0340 -- for 2 data bytes: BBAA0340 | for 8 data bytes: BBAA0940
wait %d20
wr 000000000003015c F EEDDCC05
wr 000000000003015c F EEDDCC05 -- for 2 data bytes: EEDDCC05 | for 8 data bytes: FFEEDDCC
wait %d20
wr 0000000000030160 F 0A090807
wr 0000000000030160 F 0A05A2A1
wait %d20
wr 0000000000030164 F 0E0D0C0B
wait %d20
......@@ -100,12 +101,12 @@ wr 0000000000030168 F 06060605
wait %d20
-- tx_start
wr 0000000000030034 F 00000502
wr 0000000000030034 F 00000502 -- for 2 data bytes: 0502 | for 8 data bytes: 0B02
wait %d40000
--------------- ID_DAT ---------------
tx_rst
-- tx_rst
wr 0000000000030034 F 00000001
wait %d10
wr 0000000000030034 F 00000000
......@@ -116,7 +117,7 @@ wr 0000000000030154 F 00000003
wait %d20
-- data bytes varid = 1403 for agent to send identification
wr 0000000000030158 F 00000306
wr 0000000000030158 F 00000314
wait %d20
-- tx_start
......@@ -133,8 +134,45 @@ wait %d40000
-- read received data
rd 0000000000030048 F 00000002
wait %d20
rd 000000000003004c F 00000050
rd 000000000003004c F 03800550
wait %d40000
--------------- ID_DAT ---------------
tx_rst
wr 0000000000030034 F 00000001
wait %d10
wr 0000000000030034 F 00000000
wait %d20
-- control byte of id_dat
wr 0000000000030154 F 00000003
wait %d20
-- data bytes varid = 0603 for agent to produce
wr 0000000000030158 F 00000306
wait %d20
-- tx_start
wr 0000000000030034 F 00000202
wait %d20
-- deactivate tx_start
wr 0000000000030034 F 00000000
-- release rx_rst
wr 0000000000030040 F 00000000
wait %d40000
-- read received data
rd 0000000000030048 F 00000000 FFFFFFFF -- XXXXXX02 FFFFFFFF
wait %d400
rd 000000000003004c F 00000000 FFFFFFFF -- BC870940 FFFFFFFF
wait %d400
rd 0000000000030050 F 00000000 FFFFFFFF -- B07D75EF FFFFFFFF
wait %d400
rd 0000000000030054 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d400
wait %d40000
--------------- RP_FIN ---------------
-- control byte of rp_fin
......
sim/spec/data_vectors/user_logic_config.txt 0 → 100644
View file @ aae395c5
25 ns -- User clock period (should not be modified during test)
25 ns -- Wishbone interface clock period (should not be modified during test)
3 us -- Power-on reset length
1 us -- User reset length
1 us -- Wishbone interface reset length
20000 ms -- validity time: time for which the configuration above is valid
sim/spec/data_vectors/user_sequence.txt 0 → 100644
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sim/spec/testbench/acam_data_model.vhd deleted 100644 → 0
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sim/spec/testbench/acam_fifo_model.vhd deleted 100644 → 0
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-- Created by : G. Penacoba
-- Creation Date: June 2011
-- Description: reproduces roughly the functionality of the acam:
-- handles the FIFO and the data communication handshake
-- Modified by:
-- Modification Date:
-- Modification consisted on:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity acam_fifo_model is
generic(
size : integer;
full_threshold : integer;
empty_threshold : integer
);
port(
data_input : in std_logic_vector(27 downto 0);
rd_fifo : in std_logic;
data_output : out std_logic_vector(27 downto 0);
empty : out std_logic;
full : out std_logic
);
end acam_fifo_model;
architecture behavioral of acam_fifo_model is
constant ts_ef : time:= 11800 ps; -- maximum empty flag set time
subtype index is natural range size-1 downto 0;
subtype memory_cell is std_logic_vector(27 downto 0);
type memory_block is array (natural range size-1 downto 0) of memory_cell;
signal fifo : memory_block;
signal wr_pointer : index:= 0;
signal rd_pointer : index:= 0;
signal level : index:= 0;
begin
writing: process(data_input)
begin
if now /= 0 ps then
fifo(wr_pointer) <= data_input;
if wr_pointer = size-1 then
wr_pointer <= 0;
else
wr_pointer <= wr_pointer + 1;
end if;
end if;
end process;
reading: process(rd_fifo)
begin
if rising_edge(rd_fifo) then
data_output <= fifo(rd_pointer);
if rd_pointer = size-1 then
rd_pointer <= 0 after ts_ef;
else
rd_pointer <= rd_pointer + 1 after ts_ef;
end if;
end if;
-- if falling_edge(rd_fifo) then
-- if rd_pointer = size-1 then
-- rd_pointer <= 0;
-- else
-- rd_pointer <= rd_pointer + 1;
-- end if;
-- end if;
end process;
flags: process(level)
begin
if level > full_threshold then
full <= '1';
else
full <= '0';
end if;
if level < empty_threshold then
empty <= '1';
else
empty <= '0';
end if;
end process;
filling_level: process(rd_pointer, wr_pointer)
begin
if wr_pointer >= rd_pointer then
level <= wr_pointer - rd_pointer;
else
level <= wr_pointer + 256 - rd_pointer;
end if;
end process;
-- process(level)
-- begin
-- report " filling level " & integer'image(level) & LF &
-- " rd_pointer " & integer'image(rd_pointer) & LF &
-- " wr_pointer " & integer'image(wr_pointer) & LF;
-- end process;
corruption_reporting_reading: process(rd_pointer)
begin
if now /= 0 ps then
if rd_pointer = wr_pointer then
report LF & " #### Interface FIFO is empty: no further reading should be performed" & LF
severity warning;
end if;
end if;
end process;
corruption_reporting_writing: process(wr_pointer)
begin
if now /= 0 ps then
if rd_pointer = wr_pointer then
report LF & " #### Interface FIFO is full: no further writing should be performed" & LF
severity warning;
end if;
end if;
end process;
end behavioral;
sim/spec/testbench/acam_model.vhd deleted 100644 → 0
View file @ 71c1e137
-- Creation Date: May 2011
-- Description: reproduced roughly the functionality of the acam:
-- Modified by:
-- Modification Date:
-- Modification consisted on:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity acam_model is
generic(
start_retrig_period : time:= 3200 ns;
refclk_period : time:= 32 ns
);
port(
tstart_i : in std_logic;
tstop1_i : in std_logic;
tstop2_i : in std_logic;
tstop3_i : in std_logic;
tstop4_i : in std_logic;
tstop5_i : in std_logic;
startdis_i : in std_logic;
stopdis_i : in std_logic;
int_flag_o : out std_logic;
err_flag_o : out std_logic;
address_i : in std_logic_vector(3 downto 0);
cs_n_i : in std_logic;
oe_n_i : in std_logic;
rd_n_i : in std_logic;
wr_n_i : in std_logic;
data_bus_io : inout std_logic_vector(27 downto 0);
ef1_o : out std_logic;
ef2_o : out std_logic;
lf1_o : out std_logic;
lf2_o : out std_logic
);
end acam_model;
architecture behavioral of acam_model is
component acam_timing_model
generic(
refclk_period : time:= 32 ns;
start_retrig_period : time:= 3200 ns
);
port(
tstart_i : in std_logic;
tstop1_i : in std_logic;
tstop2_i : in std_logic;
tstop3_i : in std_logic;
tstop4_i : in std_logic;
tstop5_i : in std_logic;
startdis_i : in std_logic;
stopdis_i : in std_logic;
err_flag_o : out std_logic;
int_flag_o : out std_logic;
start01_o : out std_logic_vector(16 downto 0);
timestamp_for_fifo1 : out std_logic_vector(27 downto 0);
timestamp_for_fifo2 : out std_logic_vector(27 downto 0)
);
end component;
component acam_data_model
port(
start01_i : in std_logic_vector(16 downto 0);
timestamp_for_fifo1 : in std_logic_vector(27 downto 0);
timestamp_for_fifo2 : in std_logic_vector(27 downto 0);
address_i : in std_logic_vector(3 downto 0);
cs_n_i : in std_logic;
oe_n_i : in std_logic;
rd_n_i : in std_logic;
wr_n_i : in std_logic;
data_bus_o : out std_logic_vector(27 downto 0);
ef1_o : out std_logic;
ef2_o : out std_logic;
lf1_o : out std_logic;
lf2_o : out std_logic
);
end component;
signal timestamp_for_fifo1 : std_logic_vector(27 downto 0);
signal timestamp_for_fifo2 : std_logic_vector(27 downto 0);
signal start01 : std_logic_vector(16 downto 0);
begin
timing_block: acam_timing_model
generic map(
refclk_period => refclk_period,
start_retrig_period => start_retrig_period
)
port map(
tstart_i => tstart_i,
tstop1_i => tstop1_i,
tstop2_i => tstop2_i,
tstop3_i => tstop3_i,
tstop4_i => tstop4_i,
tstop5_i => tstop5_i,
startdis_i => startdis_i,
stopdis_i => stopdis_i,
err_flag_o => err_flag_o,
int_flag_o => int_flag_o,
start01_o => start01,
timestamp_for_fifo1 => timestamp_for_fifo1,
timestamp_for_fifo2 => timestamp_for_fifo2
);
data_block: acam_data_model
port map(
start01_i => start01,
timestamp_for_fifo1 => timestamp_for_fifo1,
timestamp_for_fifo2 => timestamp_for_fifo2,
address_i => address_i,
cs_n_i => cs_n_i,
oe_n_i => oe_n_i,
rd_n_i => rd_n_i,
wr_n_i => wr_n_i,
data_bus_o => data_bus_io,
ef1_o => ef1_o,
ef2_o => ef2_o,
lf1_o => lf1_o,
lf2_o => lf2_o
);
end behavioral;
sim/spec/testbench/acam_timing_model.vhd deleted 100644 → 0
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sim/spec/testbench/board_settings.vhd 0 → 100644
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sim/spec/testbench/encounter.vhd 0 → 100644
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-- Created by : G. Penacoba
-- Creation Date: March 2010
-- Description: Counter with enable signal. Count value and 'done' signal
-- available. 'done' signal asserted at count value = 0.
-- Modified by: G. Penacoba
-- Modification Date: 30/04/2010
-- Modification consisted on: using unsigned types and numeric_std package
-- instead of std_logic_vectors and std_logic_unsigned
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity encounter is
generic(
width : integer:=16
);
port(
clk : in std_logic;
en : in std_logic;
reset : in std_logic;
start_value : in std_logic_vector(width-1 downto 0);
count : out std_logic_vector(width-1 downto 0);
count_done : out std_logic
);
end encounter;
architecture archi of encounter is
constant zeroes : unsigned(width-1 downto 0):=(others=>'0');
signal one : unsigned(width-1 downto 0);
signal value : unsigned(width-1 downto 0);
begin
decount: process (reset, clk, start_value)
begin
if reset = '1' then
value <= unsigned(start_value);
elsif clk'event and clk= '1' then
if en = '1' and value > zeroes then
value <= value - "1";
end if;
end if;
end process;
count <= std_logic_vector(value);
one <= zeroes + "1";
redundant: process (reset, clk)
begin
if reset = '1' then
count_done <= '0';
elsif clk'event and clk ='1' then
if en ='1' and value = one then
count_done <= '1';
elsif value = zeroes then
count_done <= '1';
else
count_done <= '0';
end if;
end if;
end process;
end archi;
sim/spec/testbench/nanoFIP/wf_dualram_512x8_clka_rd_clkb_wr.vhd
View file @ aae395c5
......@@ -129,7 +129,7 @@ begin
-- end generate;
---------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- for triplication: Combinatorial Majority_Voter
-- for triplication: Majority_Voter: data_porta_o <= (s_data_o_A_array(0) and s_data_o_A_array(1)) or
......
sim/spec/testbench/slone_interface.vhd 0 → 100644
View file @ aae395c5
-- Created by : G. Penacoba
-- Creation Date: November 2010
-- Description: Generates the produced variable data
-- and the variable access signals to indicate activity in stand-alone
-- Modified by:
-- Modification Date:
-- Modification consisted on:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_textio.all;
use std.textio.all;
use work.tb_package.all;
entity slone_interface is
port(
launch_slone_read : in std_logic;
launch_slone_write : in std_logic;
uclk : in std_logic;
ureset : in std_logic;
dat_o : out std_logic_vector(15 downto 0);
slone_access_read : out std_logic;
slone_access_write : out std_logic
);
end slone_interface;
architecture archi of slone_interface is
signal action : std_logic;
signal data_for_slone_hi : std_logic_vector(7 downto 0);
signal data_for_slone_lo : std_logic_vector(7 downto 0);
signal slone_rd : std_logic;
signal slone_wr : std_logic;
begin
-- process to dectect a rising edge on the inputs
-------------------------------------------------
input_registers: process
begin
slone_rd <= launch_slone_read;
slone_wr <= launch_slone_write;
if ureset ='1' then
action <= '0';
elsif (slone_rd ='0' and launch_slone_read ='1')
or (slone_wr ='0' and launch_slone_write ='1') then
action <= '1';
else
action <= '0';
end if;
wait until uclk ='1';
end process;
-- processes to fix the output data
-----------------------------------
output_register: process
begin
if ureset ='1' then
dat_o <= (others=>'0');
elsif action ='1' and slone_wr ='1' then
dat_o(15 downto 8) <= data_for_slone_hi;
dat_o(7 downto 0) <= data_for_slone_lo;
end if;
wait until uclk ='1';
end process;
access_register: process
begin
if ureset ='1' then
slone_access_read <= '0';
elsif launch_slone_read ='1' or (action ='1' and slone_rd ='1') then
slone_access_read <= '1';
else
slone_access_read <= '0';
end if;
if ureset ='1' then
slone_access_write <= '0';
elsif launch_slone_write ='1' or (action ='1' and slone_wr ='1') then
slone_access_write <= '1';
else
slone_access_write <= '0';
end if;
wait until uclk ='1';
end process;
-- process reading bytes from random data file
---------------------------------------------
read_store: process
file data_file: text open read_mode is "../../sim/spec/data_vectors/data_store.txt";
variable data_line: line;
variable data_byte_hi: std_logic_vector(7 downto 0);
variable data_byte_lo: std_logic_vector(7 downto 0);
begin
readline (data_file, data_line);
hread (data_line, data_byte_hi);
readline (data_file, data_line);
hread (data_line, data_byte_lo);
data_for_slone_hi <= data_byte_hi;
data_for_slone_lo <= data_byte_lo;
wait until uclk ='1';
end process;
end archi;
sim/spec/testbench/slone_monitor.vhd 0 → 100644
View file @ aae395c5
-- Created by : G. Penacoba
-- Creation Date: November 2010
-- Description: Generates the produced variable data
-- and the variable access signals to indicate activity in stand-alone
-- Modified by:
-- Modification Date:
-- Modification consisted on:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_textio.all;
use std.textio.all;
use work.tb_package.all;
entity slone_monitor is
port(
dat_i : in std_logic_vector(15 downto 0);
dat_o : in std_logic_vector(15 downto 0);
slone_access_read : in std_logic;
slone_access_write : in std_logic;
uclk : in std_logic;
ureset : in std_logic;
var_id : in std_logic_vector(1 downto 0)
);
end slone_monitor;
architecture archi of slone_monitor is
signal in_consumed : std_logic_vector(15 downto 0);
signal in_broadcast : std_logic_vector(15 downto 0);
signal out_produced : vector_type;
begin
-- process reading from a text file the data sent by FIP for consumption
------------------------------------------------------------------------
read_incoming: process(slone_access_read, var_id)
file data_file : text;
variable data_line : line;
variable data_byte_hi : std_logic_vector(7 downto 0);
variable data_byte_lo : std_logic_vector(7 downto 0);
begin
if slone_access_read ='1' then
if var_id = "01" then
file_open(data_file,"../../sim/spec/data_vectors/tmp_var1_mem.txt",read_mode);
readline (data_file, data_line);
readline (data_file, data_line);
readline (data_file, data_line);
hread (data_line, data_byte_lo);
readline (data_file, data_line);
hread (data_line, data_byte_hi);
file_close(data_file);
in_consumed <= data_byte_hi & data_byte_lo;
elsif var_id = "10" then
file_open(data_file,"../../sim/spec/data_vectors/tmp_var2_mem.txt",read_mode);
readline (data_file, data_line);
readline (data_file, data_line);
readline (data_file, data_line);
read (data_line, data_byte_lo);
readline (data_file, data_line);
read (data_line, data_byte_hi);
file_close(data_file);
in_broadcast <= data_byte_hi & data_byte_lo;
end if;
end if;
end process;
-- process checking the validity of the incoming consumed data as they are read from nanoFIP slone bus
------------------------------------------------------------------------------------------------------
check_consumed_and_broadcast: process(slone_access_read)
begin
if slone_access_read ='0' then
if var_id = "01" then
if in_consumed = dat_i then
report " __ check OK __ The value read from the 16-bit stand-alone bus" &
" matches the one sent from FIP for the consumed variable" & LF;
else
report " #### check NOT OK #### The value read from the 16-bit stand-alone bus" &
" does not match the one sent from FIP for the consumed variable" & LF
severity warning;
end if;
elsif var_id = "10" then
if in_broadcast = dat_i then
report " __ check OK __ The value read from the 16-bit stand-alone bus" &
" matches the one sent from FIP for the broadcast variable" & LF;
else
report " #### check NOT OK #### The value read from the 16-bit stand-alone bus" &
" does not match the one sent from FIP for the broadcast variable" & LF
severity warning;
end if;
end if;
end if;
end process;
-- process building an image of the nanoFIP memory for the produced variable
----------------------------------------------------------------------------
building_produced: process
begin
if slone_access_write ='1' then
out_produced(2) <= dat_o(7 downto 0);
out_produced(3) <= dat_o(15 downto 8);
end if;
wait until uclk ='1';
end process;
-- process transcribing to a text file the image of the nanoFIP memory for the produced variable
------------------------------------------------------------------------------------------------
write_outgoing: process(slone_access_write)
file data_file : text;
variable data_line : line;
begin
if slone_access_write ='0' then
file_open(data_file,"../../sim/spec/data_vectors/tmp_var3_mem.txt",write_mode);
for i in 0 to max_frame_length-1 loop
hwrite (data_line, out_produced(i));
writeline (data_file, data_line);
end loop;
file_close(data_file);
end if;
end process;
end archi;
sim/spec/testbench/start_stop_gen.vhd deleted 100644 → 0
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-- Created by : G. Penacoba
-- Creation Date: May 2011
-- Description: generates start and stop pulses for test-bench
-- Modified by:
-- Modification Date:
-- Modification consisted on:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_textio.all;
use std.textio.all;
entity start_stop_gen is
port(
tstart_o : out std_logic;
tstop1_o : out std_logic;
tstop2_o : out std_logic;
tstop3_o : out std_logic;
tstop4_o : out std_logic;
tstop5_o : out std_logic
);
end start_stop_gen;
architecture behavioral of start_stop_gen is
signal tstart : std_logic:='0';
signal tstop1 : std_logic:='0';
signal tstop2 : std_logic:='0';
signal tstop3 : std_logic:='0';
signal tstop4 : std_logic:='0';
signal tstop5 : std_logic:='0';
signal pulse_channel : integer;
signal pulse_length : time;
begin
-- process reading the schedule of frame exchange from a text file
------------------------------------------------------------------
sequence: process
file sequence_file : text open read_mode is "data_vectors/pulses.txt";
variable sequence_line : line;
variable interval_time : time;
variable coma : string(1 to 1);
variable pulse_ch : integer;
variable pulse_lgth : time;
begin
readline (sequence_file, sequence_line);
read (sequence_line, interval_time);
read (sequence_line, coma);
read (sequence_line, pulse_ch);
read (sequence_line, coma);
read (sequence_line, pulse_lgth);
wait for interval_time;
pulse_channel <= pulse_ch;
pulse_length <= pulse_lgth;
if endfile(sequence_file) then
file_close(sequence_file);
wait;
end if;
end process;
start_extender: process
begin
wait until pulse_channel = 0;
tstart <= '1';
wait for pulse_length;
tstart <= '0';
end process;
stop1_extender: process
begin
wait until pulse_channel = 1;
tstop1 <= '1';
wait for pulse_length;
tstop1 <= '0';
end process;
stop2_extender: process
begin
wait until pulse_channel = 2;
tstop2 <= '1';
wait for pulse_length;
tstop2 <= '0';
end process;
stop3_extender: process
begin
wait until pulse_channel = 3;
tstop3 <= '1';
wait for pulse_length;
tstop3 <= '0';
end process;
stop4_extender: process
begin
wait until pulse_channel = 4;
tstop4 <= '1';
wait for pulse_length;
tstop4 <= '0';
end process;
stop5_extender: process
begin
wait until pulse_channel = 5;
tstop5 <= '1';
wait for pulse_length;
tstop5 <= '0';
end process;
tstart_o <= tstart;
tstop1_o <= tstop1;
tstop2_o <= tstop2;
tstop3_o <= tstop3;
tstop4_o <= tstop4;
tstop5_o <= tstop5;
end behavioral;
sim/spec/testbench/tb_masterFIP.vhd
View file @ aae395c5
......@@ -218,7 +218,47 @@ port
jc_tck_o : out std_logic);
end component;
component user_interface
port(
urstn_from_nf : in std_logic;
var1_rdy_i : in std_logic;
var2_rdy_i : in std_logic;
var3_rdy_i : in std_logic;
rstpon_o : out std_logic;
uclk_o : out std_logic;
urstn_to_nf : out std_logic;
var1_acc_o : out std_logic;
var2_acc_o : out std_logic;
var3_acc_o : out std_logic;
ack_i : in std_logic;
dat_i : in std_logic_vector(15 downto 0);
adr_o : out std_logic_vector(9 downto 0);
cyc_o : out std_logic;
dat_o : out std_logic_vector(15 downto 0);
rst_o : out std_logic;
stb_o : out std_logic;
wclk_o : out std_logic;
we_o : out std_logic
);
end component;
component board_settings
port(
s_id_i : in std_logic_vector(1 downto 0);
c_id_o : out std_logic_vector(3 downto 0);
m_id_o : out std_logic_vector(3 downto 0);
nostat_o : out std_logic;
p3_lgth_o : out std_logic_vector(2 downto 0);
rate_o : out std_logic_vector(1 downto 0);
slone_o : out std_logic;
subs_o : out std_logic_vector(7 downto 0)
);
end component;
-----------------------------------------------------------------------------
-- CMD_ROUTER component
-----------------------------------------------------------------------------
......@@ -240,8 +280,7 @@ constant pll_clk_period : time:= 8 ns;
constant g_width : integer:= 32;
constant g_span : integer:= 32;
constant spec_clk_period : time:= 50 ns;
signal nanoFIP_clk_period : time:= 25 ns;
constant start_retrig_period : time:= 512 ns;
--signal nanoFIP_clk_period : time:= 25 ns;
-- Number of Models receiving commands
constant N_BFM : integer := 1; -- 0 : GN412X_BFM in Model Mode
......@@ -317,7 +356,7 @@ signal spec_led_red : std_logic;
signal fd_rxcdn, fd_rxd, fd_txer, fd_wdgn, fd_rstn, fd_txck, fd_txena, fd_txd : std_logic;
signal consu_data : std_logic_vector (15 downto 0);
signal nanoFIP_rxcdn, nanoFIP_txena, nanoFIP_txck, nanoFIP_rstno ,nanoFIP_wdgn : std_logic;
signal nanoFIP_clk : std_logic:='0';
signal nanoFIP_clk : std_logic;
signal ext_sync : std_logic := '0';
......@@ -353,6 +392,44 @@ signal spare : std_logic;
signal TX_ERROR : std_logic;
signal GPIO : std_logic_vector(15 downto 0);
signal rstpon : std_logic; --! Power On Reset, active low
signal uclk : std_logic; --! 40 MHz clock
signal urst_to_nf : std_logic; --! Initialisation control, active low
signal urst_from_nf : std_logic; --! Reset output, active low
signal var1_rdy : std_logic; --! Variable 1 ready
signal var1_acc : std_logic; --! Variable 1 access
signal var2_rdy : std_logic; --! Variable 2 ready
signal var2_acc : std_logic; --! Variable 2 access
signal var3_rdy : std_logic; --! Variable 3 ready
signal var3_acc : std_logic; --! Variable 3 access
signal u_cacer : std_logic; --! nanoFIP status byte, bit 2
signal u_pacer : std_logic; --! nanoFIP status byte, bit 3
signal r_tler : std_logic; --! nanoFIP status byte, bit 4
signal r_fcser : std_logic; --! nanoFIP status byte, bit 5
signal clk : std_logic:='1';
signal reset : std_logic;
signal ack : std_logic:='0';
signal dat_from_fip : std_logic_vector(15 downto 0);
signal adr : std_logic_vector(9 downto 0);
signal cyc : std_logic;
signal dat_to_fip : std_logic_vector(15 downto 0);
signal rst : std_logic := '0';
signal stb : std_logic;
signal wclk : std_logic;
signal we : std_logic;
signal rate : std_logic_vector (1 downto 0); --! Bit rate
signal subs : std_logic_vector (7 downto 0); --! Subscriber number coding.
signal s_id : std_logic_vector (1 downto 0); --! Identification selection
signal m_id : std_logic_vector (3 downto 0); --! Model identification settings
signal c_id : std_logic_vector (3 downto 0); --! Constructor identification settings
signal p3_lgth : std_logic_vector (2 downto 0); --! Produced variable data length
signal slone : std_logic; --! Stand-alone mode
signal nostat : std_logic; --! No NanoFIP status transmission
-----------------------------------------------------------------------------
-- Command Router Signals
......@@ -419,11 +496,13 @@ begin
agent: nanofip
port map(
c_id_i => (others => '0'),
m_id_i => (others => '0'),
p3_lgth_i => (others => '0'),
rate_i => "01",
subs_i => "00000011",
uclk_i => nanoFIP_clk,
c_id_i => c_id,
m_id_i => m_id,
p3_lgth_i => p3_lgth,
rate_i => rate,
subs_i => subs,
fd_rxcdn_i => nanoFIP_rxcdn,
fd_rxd_i => fd_txd,
......@@ -435,38 +514,80 @@ begin
fd_txd_o => fd_rxd,
fd_txena_o => nanoFIP_txena,
nostat_i => '1',
nostat_i => nostat,
rstin_i => (rst_n),--was not
rstpon_i => '1',
slone_i => '1',
uclk_i => nanoFIP_clk,
var1_acc_i => '0',
var2_acc_i => '0',
var3_acc_i => '0',
wclk_i => nanoFIP_clk,
adr_i => (others => '0'),
cyc_i => '0',
dat_i => consu_data,
rst_i => '0',
stb_i => '0',
we_i => '0',
jc_tdo_i => '0',
rston_o => open,
slone_i => '0',
rston_o => urst_from_nf,
var1_acc_i => var1_acc,
var2_acc_i => var2_acc,
var3_acc_i => var3_acc,
wclk_i => wclk,
rst_i => rst,
ack_o => ack,
adr_i => adr,
cyc_i => cyc,
dat_i => dat_to_fip,
dat_o => dat_from_fip,
stb_i => stb,
we_i => we,
var1_rdy_o => var1_rdy,
var2_rdy_o => var2_rdy,
var3_rdy_o => var3_rdy,
s_id_o => open,
r_fcser_o => open,
r_tler_o => open,
u_cacer_o => open,
u_pacer_o => open,
var1_rdy_o => open,
var2_rdy_o => open,
var3_rdy_o => open,
ack_o => open,
jc_tdo_i => '0',
jc_tms_o => open,
jc_tdi_o => open,
jc_tck_o => open,
dat_o => consu_data);
jc_tck_o => open);
user_logic: user_interface
port map(
uclk_o => nanoFIP_clk,
urstn_from_nf => urst_from_nf,
rstpon_o => open,
urstn_to_nf => open,
var1_rdy_i => var1_rdy,
var2_rdy_i => var2_rdy,
var3_rdy_i => var3_rdy,
var1_acc_o => var1_acc,
var2_acc_o => var2_acc,
var3_acc_o => var3_acc,
ack_i => ack,
dat_i => dat_from_fip,
adr_o => adr,
cyc_o => cyc,
dat_o => dat_to_fip,
rst_o => rst,
stb_o => stb,
wclk_o => wclk,
we_o => we
);
board: board_settings
port map(
s_id_i => s_id,
c_id_o => c_id,
m_id_o => m_id,
nostat_o => nostat,
p3_lgth_o => p3_lgth,
rate_o => rate,
slone_o => slone,
subs_o => subs
);
CMD_ERR <= (others => '0');
......@@ -601,11 +722,11 @@ begin
wait for spec_clk_period/2;
end process;
nanoFIP_clock: process
begin
nanoFIP_clk <= not (nanoFIP_clk) after 1 ns;
wait for nanoFIP_clk_period/2;
end process;
-- nanoFIP_clock: process
-- begin
-- nanoFIP_clk <= not (nanoFIP_clk) after 1 ns;
-- wait for nanoFIP_clk_period/2;
-- end process;
--ext_sync <= '1' after 8500 ns, '0' after 8580 ns,
-- '1' after 194000 ns, '0' after 194080 ns,
......
sim/spec/testbench/tb_package.vhd 0 → 100644
View file @ aae395c5
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package tb_package is
constant max_frame_length : integer := 131;
subtype byte_count_type is integer range 0 to max_frame_length-1;
type vector_type is array (max_frame_length-1 downto 0) of std_logic_vector(7 downto 0);
constant reset_max_latency : time := 2 ms;
subtype byte_slice is integer range 0 to 7;
subtype byte_width is integer range 8 downto 1;
subtype jitter_time is time range 0 fs to 1 ms;
component hex_byte_transcriber
port(
input : in std_logic_vector(7 downto 0);
output : out string (1 to 2)
);
end component;
component bin_byte_transcriber
port(
input : in std_logic_vector(7 downto 0);
output : out string (1 to 8)
);
end component;
end tb_package;
package body tb_package is
end tb_package;
sim/spec/testbench/user_access_monitor.vhd 0 → 100644
View file @ aae395c5
This diff is collapsed.
sim/spec/testbench/user_config.vhd 0 → 100644
View file @ aae395c5
-- Created by : G. Penacoba
-- Creation Date: September 2010
-- Description: Module for the readout of the configuration settings from a
-- text file.
-- Modified by: G. Penacoba
-- Modification Date: January 2011.
-- Modification consisted on: Times of resets are registered in tmp files for use by other units.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_textio.all;
use std.textio.all;
use work.tb_package.all;
entity user_config is
port(
config_validity : out time;
uclk_period : out time;
ureset_length : out time;
wclk_period : out time;
wreset_length : out time;
preset_length : out time
);
end user_config;
architecture archi of user_config is
signal read_config_trigger : std_logic;
signal report_config_trigger: std_logic;
signal s_uclk_period : time;
signal s_ureset_length : time;
signal s_wclk_period : time;
signal s_wreset_length : time;
signal s_preset_length : time;
begin
-- process reading config values from a file
---------------------------------------------
read_config: process
file config_file : text open read_mode is "../../sim/spec/data_vectors/user_logic_config.txt";
variable config_line : line;
variable validity_time : time;
variable uclk_period_config : time;
variable ureset_lgth_config : time;
variable wclk_period_config : time;
variable wreset_lgth_config : time;
variable preset_lgth_config : time;
begin
readline (config_file, config_line);
read (config_line, uclk_period_config);
readline (config_file, config_line);
read (config_line, wclk_period_config);
readline (config_file, config_line);
read (config_line, preset_lgth_config);
readline (config_file, config_line);
read (config_line, ureset_lgth_config);
readline (config_file, config_line);
read (config_line, wreset_lgth_config);
readline (config_file, config_line);
read (config_line, validity_time);
if endfile(config_file) then
file_close(config_file);
end if;
config_validity <= validity_time;
s_uclk_period <= uclk_period_config;
uclk_period <= uclk_period_config;
s_wclk_period <= wclk_period_config;
wclk_period <= wclk_period_config;
s_preset_length <= preset_lgth_config;
preset_length <= preset_lgth_config;
s_ureset_length <= ureset_lgth_config;
ureset_length <= ureset_lgth_config;
s_wreset_length <= wreset_lgth_config;
wreset_length <= wreset_lgth_config;
read_config_trigger <= '1';
wait for validity_time - 1 ps;
read_config_trigger <= '0';
wait for 1 ps;
end process;
-- reporting processes
-----------------------
report_config_trigger <= read_config_trigger;
history: process(report_config_trigger)
file phist_file : text;
file uhist_file : text;
variable phist_line : line;
variable uhist_line : line;
variable prst_time : time;
variable urst_time : time;
begin
if report_config_trigger'event and report_config_trigger ='1' then
if s_preset_length > 0 fs then
prst_time := now;
file_open(phist_file, "../../sim/spec/data_vectors/tmp_preset_hist.txt", write_mode);
write (phist_line, prst_time);
writeline (phist_file, phist_line);
file_close(phist_file);
end if;
if s_ureset_length > 0 fs then
urst_time := now;
file_open(uhist_file, "../../sim/spec/data_vectors/tmp_ureset_hist.txt", write_mode);
write (uhist_line, urst_time);
writeline (uhist_file, uhist_line);
file_close(uhist_file);
end if;
end if;
end process;
reporting: process(report_config_trigger)
begin
if report_config_trigger'event and report_config_trigger ='1' then
if now = 0 ps then
report LF & "User logic configuration settings" & LF &
"---------------------------------" & LF &
"User Clock period : " & time'image(s_uclk_period) & LF &
"Wishbone interface Clock period: " & time'image(s_wclk_period) & LF & LF;
end if;
if s_preset_length > 0 fs then
report " ++ The power-on reset (RSTPON) is asserted for " & time'image(s_preset_length)
& LF & " ++ As a consequence, nanoFIP should reset its internal registers and error flags,"
& LF & " ++ assert the Fieldrive reset (FD_RSTN)"
& LF & " ++ and reset the VAR_RDY user interface signals" & LF
severity warning;
end if;
if s_ureset_length > 0 fs then
report " ++ The user reset (RSTIN) is asserted for " & time'image(s_ureset_length)
& LF & " ++ As a consequence, nanoFIP should reset its internal registers and error flags,"
& LF & " ++ assert the Fieldrive reset (FD_RSTN)"
& LF & " ++ and reset the VAR_RDY user interface signals" & LF
severity warning;
end if;
if s_wreset_length > 0 fs then
report " ++ The wishbone reset (RST_I) is asserted for " & time'image(s_wreset_length) & LF
severity warning;
end if;
end if;
end process;
end archi;
sim/spec/testbench/user_interface.vhd 0 → 100644
View file @ aae395c5
-- Created by : G. Penacoba
-- Creation Date: MAy 2010
-- Description: Module emulating all the user logic activity
-- Modified by: G. Penacoba
-- Modification Date: September 2010
-- Modification consisted on: Configuration settings retrieved from a text file through an independent module.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.tb_package.all;
entity user_interface is
port(
urstn_from_nf : in std_logic;
var1_rdy_i : in std_logic;
var2_rdy_i : in std_logic;
var3_rdy_i : in std_logic;
rstpon_o : out std_logic;
uclk_o : out std_logic;
urstn_to_nf : out std_logic;
var1_acc_o : out std_logic;
var2_acc_o : out std_logic;
var3_acc_o : out std_logic;
ack_i : in std_logic;
dat_i : in std_logic_vector(15 downto 0);
adr_o : out std_logic_vector(9 downto 0);
cyc_o : out std_logic;
dat_o : out std_logic_vector(15 downto 0);
rst_o : out std_logic;
stb_o : out std_logic;
wclk_o : out std_logic;
we_o : out std_logic
);
end user_interface;
architecture archi of user_interface is
component slone_interface
port(
launch_slone_read : in std_logic;
launch_slone_write : in std_logic;
uclk : in std_logic;
ureset : in std_logic;
dat_o : out std_logic_vector(15 downto 0);
slone_access_read : out std_logic;
slone_access_write : out std_logic
);
end component;
component slone_monitor
port(
dat_i : in std_logic_vector(15 downto 0);
dat_o : in std_logic_vector(15 downto 0);
slone_access_read : in std_logic;
slone_access_write : in std_logic;
uclk : in std_logic;
ureset : in std_logic;
var_id : in std_logic_vector(1 downto 0)
);
end component;
component user_sequencer
port(
uclk_period : in time;
wclk_period : in time;
block_size : out std_logic_vector(6 downto 0);
launch_slone_read : out std_logic;
launch_slone_write : out std_logic;
launch_wb_read : out std_logic;
launch_wb_write : out std_logic;
transfer_length : out std_logic_vector(6 downto 0);
transfer_offset : out std_logic_vector(6 downto 0);
var_id : out std_logic_vector(1 downto 0)
);
end component;
component user_access_monitor is
port(
cyc : in std_logic;
uclk_period : in time;
urstn_from_nf : in std_logic;
slone_access_read : in std_logic;
slone_access_write : in std_logic;
var1_rdy_i : in std_logic;
var2_rdy_i : in std_logic;
var3_rdy_i : in std_logic;
var_id : in std_logic_vector(1 downto 0);
var1_acc_o : out std_logic;
var2_acc_o : out std_logic;
var3_acc_o : out std_logic
);
end component;
component wishbone_interface
port(
block_size : in std_logic_vector(6 downto 0);
launch_wb_read : in std_logic;
launch_wb_write : in std_logic;
transfer_length : in std_logic_vector(6 downto 0);
transfer_offset : in std_logic_vector(6 downto 0);
var_id : in std_logic_vector(1 downto 0);
ack_i : in std_logic;
clk_i : in std_logic;
dat_i : in std_logic_vector(7 downto 0);
rst_i : in std_logic;
adr_o : out std_logic_vector(9 downto 0);
cyc_o : out std_logic;
dat_o : out std_logic_vector(7 downto 0);
stb_o : out std_logic;
we_o : out std_logic
);
end component;
component wishbone_monitor
port(
ack_i : in std_logic;
clk_o : in std_logic;
dat_i : in std_logic_vector(7 downto 0);
rst_o : in std_logic;
adr_o : in std_logic_vector(9 downto 0);
cyc_o : in std_logic;
dat_o : in std_logic_vector(7 downto 0);
stb_o : in std_logic;
we_o : in std_logic
);
end component;
component user_config is
port(
config_validity : out time;
uclk_period : out time;
ureset_length : out time;
wclk_period : out time;
wreset_length : out time;
preset_length : out time
);
end component;
signal adr : std_logic_vector(9 downto 0);
signal data_from_wb : std_logic_vector(7 downto 0);
signal stb : std_logic;
signal we : std_logic;
signal block_size : std_logic_vector(6 downto 0):="000" & x"0";
signal config_validity_time : time;
signal cyc : std_logic;
signal data_from_slone : std_logic_vector(15 downto 0);
signal memory_output : boolean;
signal slone_access_read : std_logic;
signal slone_access_write : std_logic;
signal slone_output : boolean;
signal launch_slone_read : std_logic:='0';
signal launch_slone_write : std_logic:='0';
signal launch_wb_read : std_logic:='0';
signal launch_wb_write : std_logic:='0';
signal transfer_length : std_logic_vector(6 downto 0):="000" & x"0";
signal transfer_offset : std_logic_vector(6 downto 0):="000" & x"0";
signal uclk : std_logic:='0';
signal uclk_period : time;
signal ureset : std_logic;
signal ureset_length : time;
signal var_id : std_logic_vector(1 downto 0):="00";
signal wclk : std_logic:='0';
signal wclk_period : time;
signal wreset : std_logic;
signal wreset_length : time;
signal preset : std_logic;
signal preset_length : time;
begin
user_clock: process
begin
wait for 0 us; -- wait needed for the config text file to be read
uclk <= not(uclk);
wait for uclk_period/2;
end process;
user_reset: process
begin
wait for 0 us; -- wait needed for the config text file to be read
if ureset_length > 0 ps then
ureset <= '1';
wait for ureset_length;
else
ureset <= '0';
wait for ureset_length;
end if;
ureset <= '0';
wait for config_validity_time - ureset_length;
end process;
wb_clock: process
begin
wait for 0 us; -- wait needed for the config text file to be read
wclk <= not(wclk);
wait for wclk_period/2;
end process;
wb_reset: process
begin
wait for 0 us; -- wait needed for the config text file to be read
if wreset_length > 0 ps then
wreset <= '1';
wait for wreset_length;
else
wreset <= '0';
wait for wreset_length;
end if;
wreset <= '0';
wait for config_validity_time - wreset_length;
end process;
por_reset: process
begin
wait for 0 us; -- wait needed for the config text file to be read
if preset_length > 0 ps then
preset <= '1';
wait for preset_length;
else
preset <= '0';
wait for preset_length;
end if;
preset <= '0';
wait for config_validity_time - preset_length;
end process;
slone_output_detector: process
begin
if launch_slone_write ='1' then
slone_output <= TRUE;
elsif memory_output then
slone_output <= FALSE;
end if;
wait until uclk ='1';
end process;
memory_output_detector: process
begin
if launch_wb_write ='1' then
memory_output <= TRUE;
elsif slone_output then
memory_output <= FALSE;
end if;
wait until wclk ='1';
end process;
sa_interface: slone_interface
port map(
launch_slone_read => launch_slone_read,
launch_slone_write => launch_slone_write,
uclk => uclk,
ureset => ureset,
dat_o => data_from_slone,
slone_access_read => slone_access_read,
slone_access_write => slone_access_write
);
sa_monitor: slone_monitor
port map(
dat_i => dat_i,
dat_o => data_from_slone,
slone_access_read => slone_access_read,
slone_access_write => slone_access_write,
uclk => uclk,
ureset => ureset,
var_id => var_id
);
user_sequence: user_sequencer
port map(
uclk_period => uclk_period,
wclk_period => wclk_period,
block_size => block_size,
launch_slone_read => launch_slone_read,
launch_slone_write => launch_slone_write,
launch_wb_read => launch_wb_read,
launch_wb_write => launch_wb_write,
transfer_length => transfer_length,
transfer_offset => transfer_offset,
var_id => var_id
);
user_acc_monitor: user_access_monitor
port map(
cyc => cyc,
uclk_period => uclk_period,
urstn_from_nf => urstn_from_nf,
slone_access_read => slone_access_read,
slone_access_write => slone_access_write,
var1_rdy_i => var1_rdy_i,
var2_rdy_i => var2_rdy_i,
var3_rdy_i => var3_rdy_i,
var_id => var_id,
var1_acc_o => var1_acc_o,
var2_acc_o => var2_acc_o,
var3_acc_o => var3_acc_o
);
wb_interface: wishbone_interface
port map(
block_size => block_size,
launch_wb_read => launch_wb_read,
launch_wb_write => launch_wb_write,
transfer_length => transfer_length,
transfer_offset => transfer_offset,
var_id => var_id,
ack_i => ack_i,
clk_i => wclk,
dat_i => dat_i(7 downto 0),
rst_i => wreset,
adr_o => adr,
cyc_o => cyc,
dat_o => data_from_wb,
stb_o => stb,
we_o => we
);
wb_monitor: wishbone_monitor
port map(
ack_i => ack_i,
clk_o => wclk,
dat_i => dat_i(7 downto 0),
rst_o => wreset,
adr_o => adr,
cyc_o => cyc,
dat_o => data_from_wb,
stb_o => stb,
we_o => we
);
user_configuration: user_config
port map(
config_validity => config_validity_time,
uclk_period => uclk_period,
ureset_length => ureset_length,
wclk_period => wclk_period,
wreset_length => wreset_length,
preset_length => preset_length
);
uclk_o <= uclk;
urstn_to_nf <= not(ureset);
rstpon_o <= not(preset);
adr_o <= adr;
cyc_o <= cyc;
rst_o <= wreset;
wclk_o <= wclk;
stb_o <= stb;
we_o <= we;
dat_o <= data_from_slone when slone_output
else x"00" & data_from_wb when memory_output
else (others=>'0');
end archi;
sim/spec/testbench/user_sequencer.vhd 0 → 100644
View file @ aae395c5
-- Created by : G. Penacoba
-- Creation Date: March 2010
-- Description: Orders the sequence of actions of the user
-- Modified by: G. Penacoba
-- Modification Date: 23/08/2010
-- Modification consisted on: Name change
-- + addition of the other user interface signals
-- Modification Date: October 2010
-- Modification consisted on: Addition of access to schedule from a text file + reporting
-- + addition of user access error and freshness status signals
-- Modification Date: 1 November 2010
-- Modification consisted on: Management of user_access signals and errors and freshness status
-- moved to a different file.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_textio.all;
use std.textio.all;
use work.tb_package.all;
entity user_sequencer is
port(
uclk_period : in time;
wclk_period : in time;
block_size : out std_logic_vector(6 downto 0);
launch_slone_read : out std_logic;
launch_slone_write : out std_logic;
launch_wb_read : out std_logic;
launch_wb_write : out std_logic;
transfer_length : out std_logic_vector(6 downto 0);
transfer_offset : out std_logic_vector(6 downto 0);
var_id : out std_logic_vector(1 downto 0)
);
end user_sequencer;
architecture archi of user_sequencer is
signal blck_sze : integer:=0;
signal launch_slone_rd : std_logic:='0';
signal launch_slone_wr : std_logic:='0';
signal launch_wb_rd : std_logic:='0';
signal launch_wb_wr : std_logic:='0';
signal transfer_lgth : integer:=0;
signal transfer_offst : integer:=0;
signal var : integer:=0;
begin
-- process retrieving the sequence of actions performed by the user logic from a text file
------------------------------------------------------------------------------------------
sequence: process
file sequence_file : text open read_mode is "../../sim/spec/data_vectors/user_sequence.txt";
variable sequence_line : line;
file config_file : text;
variable config_line : line;
variable stand_by_time : time;
variable coma : string(1 to 1);
variable block_size_tmp : integer;
variable rd_wr : std_logic;
variable slone_cfig_tmp : std_logic_vector(0 downto 0);
variable trfer_lgth_tmp : integer;
variable trfer_ofst_tmp : integer;
variable var_id_tmp : integer;
begin
wait for 0 us;
readline (sequence_file, sequence_line);
readline (sequence_file, sequence_line);
readline (sequence_file, sequence_line);
wait for wclk_period;
loop
launch_slone_rd <= '0';
launch_slone_wr <= '0';
launch_wb_rd <= '0';
launch_wb_wr <= '0';
file_open(config_file,"../../sim/spec/data_vectors/tmp_board_config.txt",read_mode);
readline (config_file, config_line);
read (config_line, slone_cfig_tmp);
file_close(config_file);
-- report " FIRST slone config " & integer'image(to_integer(unsigned(slone_cfig_tmp)));
readline (sequence_file, sequence_line);
read (sequence_line, stand_by_time);
if not(endfile(sequence_file)) then
readline (sequence_file, sequence_line);
read (sequence_line, rd_wr);
read (sequence_line, coma);
read (sequence_line, var_id_tmp);
read (sequence_line, coma);
read (sequence_line, trfer_lgth_tmp);
read (sequence_line, coma);
read (sequence_line, trfer_ofst_tmp);
read (sequence_line, coma);
read (sequence_line, block_size_tmp);
else
file_close(sequence_file);
end if;
if slone_cfig_tmp ="1" then
wait for stand_by_time - uclk_period;
else
wait for stand_by_time - wclk_period;
end if;
var_id <= std_logic_vector(to_unsigned(var_id_tmp,2));
var <= var_id_tmp;
transfer_length <= std_logic_vector(to_unsigned(trfer_lgth_tmp,7));
transfer_lgth <= trfer_lgth_tmp;
transfer_offset <= std_logic_vector(to_unsigned(trfer_ofst_tmp,7));
transfer_offst <= trfer_ofst_tmp;
block_size <= std_logic_vector(to_unsigned(block_size_tmp,7));
blck_sze <= block_size_tmp;
file_open(config_file,"../../sim/spec/data_vectors/tmp_board_config.txt",read_mode);
readline (config_file, config_line);
read (config_line, slone_cfig_tmp);
file_close(config_file);
-- report " SECOND slone config " & integer'image(to_integer(unsigned(slone_cfig_tmp)));
if slone_cfig_tmp ="1" then
if rd_wr ='1' then
launch_slone_rd <= '0';
launch_slone_wr <= '1';
launch_wb_rd <= '0';
launch_wb_wr <= '0';
else
launch_slone_rd <= '1';
launch_slone_wr <= '0';
launch_wb_rd <= '0';
launch_wb_wr <= '0';
end if;
else
if rd_wr ='1' then
launch_slone_rd <= '0';
launch_slone_wr <= '0';
launch_wb_rd <= '0';
launch_wb_wr <= '1';
else
launch_slone_rd <= '0';
launch_slone_wr <= '0';
launch_wb_rd <= '1';
launch_wb_wr <= '0';
end if;
end if;
if slone_cfig_tmp ="1" then
wait for uclk_period;
else
wait for wclk_period;
end if;
end loop;
end process;
launch_slone_read <= launch_slone_rd;
launch_slone_write <= launch_slone_wr;
launch_wb_read <= launch_wb_rd;
launch_wb_write <= launch_wb_wr;
reporting: process(launch_slone_rd, launch_slone_wr, launch_wb_rd, launch_wb_wr)
begin
if launch_slone_rd ='1' then
report LF & " User logic reads 2 bytes from the 16-bit stand-alone bus"& LF;
elsif launch_slone_wr ='1' then
report LF & " User logic writes 2 bytes on the 16-bit stand-alone bus"& LF;
elsif launch_wb_rd ='1' then
if transfer_offst = 0 then
report LF & " User logic reads " & integer'image(transfer_lgth) &
" bytes of user data plus the length byte and the PDU type byte" &
" between address " & integer'image(transfer_offst+transfer_lgth+1) & " and address 0" &
" from variable " & integer'image(var) & " in nanoFIP memory" & LF;
else
report LF & " User logic reads " & integer'image(transfer_lgth) &
" bytes of user data" &
" between address " & integer'image(transfer_offst+transfer_lgth+1) &
" and address " & integer'image(transfer_offst+2) &
" from variable " & integer'image(var) & " in nanoFIP memory" & LF;
end if;
elsif launch_wb_wr ='1' then
report LF & " User logic writes " & integer'image(transfer_lgth) &
" bytes on variable " & integer'image(var) &
" in nanoFIP memory between address " & integer'image(transfer_offst+transfer_lgth+1) &
" and address " & integer'image(transfer_offst+2) & LF;
end if;
end process;
end archi;
sim/spec/testbench/wishbone_interface.vhd 0 → 100644
View file @ aae395c5
-- Created by : G. Penacoba
-- Creation Date: February 2010
-- Description: Module to perform wishbone cycles (read/write in single or block transfer)
-- Modified by: G. Penacoba
-- Modification Date: October 2010
-- Modification consisted on: Memory counters on read adapted to include Length and PDU type bytes.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_textio.all;
use std.textio.all;
use work.tb_package.all;
entity wishbone_interface is
port(
block_size : in std_logic_vector(6 downto 0);
launch_wb_read : in std_logic;
launch_wb_write : in std_logic;
transfer_length : in std_logic_vector(6 downto 0);
transfer_offset : in std_logic_vector(6 downto 0);
var_id : in std_logic_vector(1 downto 0);
ack_i : in std_logic;
clk_i : in std_logic;
dat_i : in std_logic_vector(7 downto 0);
rst_i : in std_logic;
adr_o : out std_logic_vector(9 downto 0);
cyc_o : out std_logic;
dat_o : out std_logic_vector(7 downto 0);
stb_o : out std_logic;
we_o : out std_logic
);
end wishbone_interface;
architecture archi of wishbone_interface is
component encounter
generic(
width : integer:=16
);
port(
clk : in std_logic;
en : in std_logic;
reset : in std_logic;
start_value : in std_logic_vector(width-1 downto 0);
count : out std_logic_vector(width-1 downto 0);
count_done : out std_logic
);
end component;
constant zero : std_logic_vector(6 downto 0):=(others =>'0');
type wb_st_type is (idle, single, burst, rest);
signal wb_state, nxt_wb_state : wb_st_type:=idle;
signal add_count : std_logic_vector(9 downto 0);
signal burst_done : std_logic;
signal burst_size : std_logic_vector(6 downto 0):=(others=>'0');
signal cyc : std_logic;
signal data_for_mem : std_logic_vector(7 downto 0);
signal mem_count : std_logic_vector(6 downto 0);
signal mem_done : std_logic;
signal mem_length : std_logic_vector(6 downto 0):=(others=>'0');
signal mem_offset : std_logic_vector(6 downto 0):=(others=>'0');
signal reset_burst : std_logic;
signal reset_mem : std_logic;
signal stb : std_logic;
signal valid_bus_cycle : std_logic;
signal var_adr : std_logic_vector(1 downto 0):=(others=>'0');
signal we : std_logic:='0';
begin
-- wishbone interface state machine (sequential section)
-----------------------------------------------------------------------------
wb_fsm_seq: process
begin
if rst_i = '1' then
wb_state <= idle;
else
wb_state <= nxt_wb_state;
end if;
wait until clk_i ='1';
end process;
-- wishbone interface state machine (combinatorial section)
-----------------------------------------------------------------------------------
wb_fsm_comb: process (wb_state, launch_wb_read, launch_wb_write,
burst_size, ack_i, burst_done, mem_done)
begin
case wb_state is
when idle =>
cyc <= '0';
reset_burst <= '1';
reset_mem <= '1';
stb <= '0';
if (launch_wb_read /='0' or launch_wb_write /='0') then
if burst_size > zero then
nxt_wb_state <= burst;
else
nxt_wb_state <= single;
end if;
else
nxt_wb_state <= idle;
end if;
when single =>
cyc <= '1';
reset_burst <= '1';
reset_mem <= '0';
stb <= '1';
if ack_i ='0' then
nxt_wb_state <= single;
elsif mem_done ='1' then
nxt_wb_state <= idle;
else
nxt_wb_state <= rest;
end if;
when burst =>
cyc <= '1';
reset_burst <= '0';
reset_mem <= '0';
stb <= '1';
if ack_i ='0' then
nxt_wb_state <= burst;
elsif mem_done ='1' then
nxt_wb_state <= idle;
elsif burst_done ='1' then
nxt_wb_state <= rest;
else
nxt_wb_state <= burst;
end if;
when rest =>
cyc <= '1';
reset_burst <= '1';
reset_mem <= '0';
stb <= '0';
if burst_size > zero then
nxt_wb_state <= burst;
else
nxt_wb_state <= single;
end if;
when others =>
cyc <= '0';
reset_burst <= '1';
reset_mem <= '1';
stb <= '0';
nxt_wb_state <= idle;
end case;
end process;
-- latches for identifying the type of the memory access cycle
--------------------------------------------------------------
latch_inference: process (launch_wb_read, launch_wb_write)
begin
if launch_wb_read ='1' then
if block_size = zero then
burst_size <= zero;
else
burst_size <= block_size - ("000" & x"1");
end if;
if transfer_offset = zero then
mem_length <= transfer_length + ("000" & x"1");
mem_offset <= (others=>'0');
else
mem_length <= transfer_length - ("000" & x"1");
mem_offset <= transfer_offset + ("000" & x"2");
end if;
var_adr <= var_id -"01";
we <= '0';
elsif launch_wb_write ='1' then
if block_size = zero then
burst_size <= zero;
else
burst_size <= block_size - ("000" & x"1");
end if;
mem_length <= transfer_length - ("000" & x"1");
mem_offset <= transfer_offset + ("000" & x"2");
var_adr <= var_id -"01";
we <= '1';
end if;
end process;
add_count <= "0" & var_adr & (mem_count + mem_offset);
valid_bus_cycle <= stb and cyc and ack_i;
-- output signals
-----------------------
adr_o <= add_count;
cyc_o <= cyc;
dat_o <= data_for_mem;
stb_o <= stb;
we_o <= we;
-- process reading bytes from random data file
---------------------------------------------
read_store: process
file data_file: text open read_mode is "../../sim/spec/data_vectors/data_store.txt";
variable data_line: line;
variable data_byte: std_logic_vector(7 downto 0);
begin
readline (data_file, data_line);
hread (data_line, data_byte);
data_for_mem <= data_byte;
wait until clk_i ='1';
end process;
burst_counter: encounter
generic map(
width => 7
)
port map(
clk => clk_i,
en => valid_bus_cycle,
reset => reset_burst,
start_value => burst_size,
count => open,
count_done => burst_done
);
mem_counter: encounter
generic map(
width => 7
)
port map(
clk => clk_i,
en => valid_bus_cycle,
reset => reset_mem,
start_value => mem_length,
count => mem_count,
count_done => mem_done
);
end archi;
sim/spec/testbench/wishbone_monitor.vhd 0 → 100644
View file @ aae395c5
-- Created by : G. Penacoba
-- Creation Date: October 2010
-- Description: Block performing the validity check of the exchanged data from the user side.
-- Monitors only the contents of the memory through the wishbone interface signals.
-- Modified by:
-- Modification Date:
-- Modification consisted on:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_textio.all;
use std.textio.all;
use work.tb_package.all;
entity wishbone_monitor is
port(
ack_i : in std_logic;
clk_o : in std_logic;
dat_i : in std_logic_vector(7 downto 0);
rst_o : in std_logic;
adr_o : in std_logic_vector(9 downto 0);
cyc_o : in std_logic;
dat_o : in std_logic_vector(7 downto 0);
stb_o : in std_logic;
we_o : in std_logic
);
end wishbone_monitor;
architecture archi of wishbone_monitor is
signal adr : byte_count_type;
signal errct : byte_count_type;
signal errct_trig : std_logic:='0';
signal in_broadcast : vector_type;
signal in_consumed : vector_type;
signal out_produced : vector_type;
signal valid_bus_cycle : boolean;
signal var_id : integer:=0;
signal writing_produced : boolean;
begin
-- process reading from a text file the data sent by FIP for consumption
------------------------------------------------------------------------
read_incoming: process(cyc_o, var_id)
file data_file : text;
variable data_line : line;
variable data_byte : std_logic_vector(7 downto 0);
variable data_vector : vector_type;
variable i : integer:=0;
begin
if cyc_o ='1' then
if var_id = 1 then
data_vector := (others => x"00");
file_open(data_file,"../../sim/spec/data_vectors/tmp_var1_mem.txt",read_mode);
while not(endfile(data_file)) loop
readline (data_file, data_line);
hread (data_line, data_byte);
data_vector(i) := data_byte;
i := i+1;
end loop;
file_close(data_file);
i := 0;
in_consumed <= data_vector;
elsif var_id = 2 then
data_vector := (others => x"00");
file_open(data_file,"../../sim/spec/data_vectors/tmp_var2_mem.txt",read_mode);
while not(endfile(data_file)) loop
readline (data_file, data_line);
hread (data_line, data_byte);
data_vector(i) := data_byte;
i := i+1;
end loop;
file_close(data_file);
i := 0;
in_broadcast <= data_vector;
end if;
end if;
end process;
-- process checking the validity of the incoming consumed data as they are retrieved from nanoFIP memory
--------------------------------------------------------------------------------------------------------
check_consumed_and_broadcast: process
begin
if valid_bus_cycle then
if var_id = 1 then
if in_consumed(adr) /= dat_i then
report LF & " #### check NOT OK #### Value retrieved from memory DAT_I::::" & integer'image(to_integer(unsigned(dat_i))) &
"in address " & integer'image(adr) &
" of the Consumed variable does not match the corresponding one sent from FIP by the BA" & LF
severity warning;
errct_trig <= '1';
end if;
elsif var_id = 2 then
if in_broadcast(adr) /= dat_i then
report " #### check NOT OK #### Value retrieved from memory in address " &
integer'image(adr) & " of the Broadcast variable does not match the corresponding one sent from FIP by the BA" & LF
severity warning;
errct_trig <= '1';
end if;
end if;
else
errct_trig <= '0';
end if;
wait until clk_o ='1';
end process;
count_errors: process
begin
if cyc_o ='1' then
if errct_trig ='1' then
errct <= errct + 1;
end if;
else
errct <= 0;
end if;
wait until clk_o ='1';
end process;
report_errors: process (cyc_o)
begin
if cyc_o'event and cyc_o= '0' then
if errct = 0 and we_o = '0' and now /= 0 fs then
report " __ check OK __ All values found in memory match the ones sent from FIP" & LF & LF
severity note;
end if;
end if;
end process;
-- process building an image of the nanoFIP memory for the produced variable
----------------------------------------------------------------------------
produced_memory:process
begin
if writing_produced and valid_bus_cycle then
out_produced(adr) <= dat_o;
end if;
wait until clk_o ='1';
end process;
-- process transcribing to a text file the image of the nanoFIP memory for the produced variable
------------------------------------------------------------------------------------------------
write_outgoing: process(writing_produced)
file data_file : text;
variable data_line : line;
begin
if writing_produced'event and writing_produced = FALSE then
file_open(data_file,"../../sim/spec/data_vectors/tmp_var3_mem.txt",write_mode);
for i in 0 to max_frame_length-1 loop
hwrite (data_line, out_produced(i));
writeline (data_file, data_line);
end loop;
file_close(data_file);
end if;
end process;
var_id <= to_integer(unsigned(adr_o(8 downto 7)))+1;
adr <= to_integer(unsigned(adr_o(6 downto 0)));
valid_bus_cycle <= cyc_o ='1' and stb_o ='1' and ack_i ='1';
writing_produced <= cyc_o ='1' and var_id = 3 and we_o ='1';
end archi;
syn/spec/spec_masterFIP.xise
View file @ aae395c5
This diff is collapsed.
top/spec/spec_masterFIP.vhd
View file @ aae395c5
......@@ -230,7 +230,7 @@ architecture rtl of spec_masterFIP is
signal clk_40m_sys, rst_sys : std_logic;
signal rst_sys_n : std_logic;
signal pllout_clk_sys, pllout_clk_sys_fb : std_logic;
signal sys_locked, pll_status : std_logic;
signal sys_locked : std_logic;
-- WISHBONE from crossbar master port
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
......@@ -243,7 +243,7 @@ architecture rtl of spec_masterFIP is
-- Carrier 1-wire
signal carrier_owr_en, carrier_owr_i : std_logic_vector(c_FMC_ONEWIRE_NB - 1 downto 0);
-- VIC
signal fmc_eic_irq, irq_to_gn4124 : std_logic;
signal fmc_eic_irq : std_logic;
signal fmc_eic_irq_synch : std_logic_vector (1 downto 0);
-- EEPROM on mezzanine
signal tdc_scl_out, tdc_scl_in, tdc_sda_out, tdc_sda_in: std_logic;
......@@ -312,7 +312,7 @@ begin
---------------------------------------------------------------------------------------------------
-- Reset for 62.5 MHz clk domain --
-- Reset for 40 MHz clk domain --
---------------------------------------------------------------------------------------------------
cmp_spec_rst_gen : spec_reset_gen
......@@ -385,8 +385,8 @@ begin
vc_rdy_i => vc_rdy_i,
-- Interrupt interface
dma_irq_o => open,
irq_p_i => irq_to_gn4124,
irq_p_o => irq_p_o,
irq_p_i => '0',
irq_p_o => open,
-- CSR WISHBONE interface (master pipelined)
csr_clk_i => clk_40m_sys,
csr_adr_o => gn_wb_adr,
......@@ -562,7 +562,7 @@ begin
carrier_info_carrier_type_i => c_CARRIER_TYPE,
carrier_info_stat_fmc_pres_i => prsnt_m2c_n_i,
carrier_info_stat_p2l_pll_lck_i => gn4124_status(0),
carrier_info_stat_sys_pll_lck_i => pll_status,
carrier_info_stat_sys_pll_lck_i => '0',
carrier_info_stat_ddr3_cal_done_i => '0',
carrier_info_stat_reserved_i => (others => '0'),
carrier_info_ctrl_led_green_o => open,
......
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