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MasterFIP - Gateware
Commit a54c8d19 authored by Evangelia Gousiou's avatar Evangelia Gousiou Committed by Evangelia Gousiou
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cleanup

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rtl/masterfip_rx.vhd
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......@@ -71,16 +71,16 @@
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- SOLDERPAD LICENSE |
-- Copyright CERN 2014-2018 |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
-- Copyright and related rights are licensed under the Solderpad Hardware License, Version 2.0 |
-- (the "License"); you may not use this file except in compliance with the License. |
-- You may obtain a copy of the License at http://solderpad.org/licenses/SHL-2.0. |
-- Unless required by applicable law or agreed to in writing, software, hardware and materials |
-- distributed under this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR |
-- CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language |
-- governing permissions and limitations under the License. |
---------------------------------------------------------------------------------------------------
......
rtl/masterfip_wbgen2_pkg.vhd
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syn/spec/spec_masterfip_mt.par
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Release 14.7 par P.20131013 (nt64)
Release 14.7 par P.20131013 (nt)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
PCBE13457:: Wed Jul 26 12:07:41 2017
PCBE13457:: Thu Jan 17 18:18:19 2019
par -w -intstyle ise -ol high -xe n -mt off spec_masterfip_mt_map.ncd
spec_masterfip_mt.ncd spec_masterfip_mt.pcf
Constraints file: spec_masterfip_mt.pcf.
Loading device for application Rf_Device from file '6slx45t.nph' in environment C:\EDA\Xilinx\14.7\ISE_DS\ISE\.
Loading device for application Rf_Device from file '6slx45t.nph' in environment C:\Xilinx\14.7\ISE_DS\ISE\.
"spec_masterfip_mt" is an NCD, version 3.2, device xc6slx45t, package fgg484, speed -3
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
......@@ -111,7 +111,7 @@ Router effort level (-rl): High
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
Starting initial Timing Analysis. REAL time: 18 secs
Finished initial Timing Analysis. REAL time: 19 secs
Finished initial Timing Analysis. REAL time: 18 secs
WARNING:Par:288 - The signal vc_rdy_i<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal vc_rdy_i<1>_IBUF has no load. PAR will not attempt to route this signal.
......@@ -189,25 +189,25 @@ Phase 1 : 110289 unrouted; REAL time: 20 secs
Phase 2 : 101662 unrouted; REAL time: 23 secs
Phase 3 : 51539 unrouted; REAL time: 1 mins 7 secs
Phase 3 : 51539 unrouted; REAL time: 1 mins 12 secs
Phase 4 : 53338 unrouted; (Setup:0, Hold:3107, Component Switching Limit:0) REAL time: 1 mins 23 secs
Phase 4 : 53338 unrouted; (Setup:0, Hold:3107, Component Switching Limit:0) REAL time: 1 mins 29 secs
Updating file: spec_masterfip_mt.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:2602, Component Switching Limit:0) REAL time: 7 mins 42 secs
Phase 5 : 0 unrouted; (Setup:0, Hold:2602, Component Switching Limit:0) REAL time: 8 mins 40 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:2602, Component Switching Limit:0) REAL time: 7 mins 42 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:2602, Component Switching Limit:0) REAL time: 8 mins 40 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:2602, Component Switching Limit:0) REAL time: 7 mins 42 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:2602, Component Switching Limit:0) REAL time: 8 mins 40 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:2602, Component Switching Limit:0) REAL time: 7 mins 42 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:2602, Component Switching Limit:0) REAL time: 8 mins 40 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 7 mins 43 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 8 mins 41 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 7 mins 49 secs
Total REAL time to Router completion: 7 mins 49 secs
Total CPU time to Router completion: 7 mins 58 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 8 mins 47 secs
Total REAL time to Router completion: 8 mins 47 secs
Total CPU time to Router completion: 8 mins 55 secs
Partition Implementation Status
-------------------------------
......@@ -367,10 +367,10 @@ All signals are completely routed.
WARNING:Par:283 - There are 29 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 7 mins 56 secs
Total CPU time to PAR completion: 8 mins 5 secs
Total REAL time to PAR completion: 8 mins 55 secs
Total CPU time to PAR completion: 9 mins 3 secs
Peak Memory Usage: 889 MB
Peak Memory Usage: 666 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
......
syn/spec/spec_masterfip_mt.syr
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syn/spec/spec_masterfip_mt.twr
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--------------------------------------------------------------------------------
Release 14.7 Trace (nt64)
Release 14.7 Trace (nt)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
C:\EDA\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s
3 -n 3 -fastpaths -xml spec_masterfip_mt.twx spec_masterfip_mt.ncd -o
C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 3 -n
3 -fastpaths -xml spec_masterfip_mt.twx spec_masterfip_mt.ncd -o
spec_masterfip_mt.twr spec_masterfip_mt.pcf
Design file: spec_masterfip_mt.ncd
......@@ -1397,14 +1397,14 @@ Design statistics:
------------------------------------Footnotes-----------------------------------
1) The minimum period statistic assumes all single cycle delays.
Analysis completed Wed Jul 26 12:16:14 2017
Analysis completed Thu Jan 17 18:27:56 2019
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 702 MB
Peak Memory Usage: 502 MB
syn/spec/spec_masterfip_mt_map.mrp
View file @ a54c8d19
Release 14.7 Map P.20131013 (nt64)
Release 14.7 Map P.20131013 (nt)
Xilinx Mapping Report File for Design 'spec_masterfip_mt'
Design Information
......@@ -11,7 +11,7 @@ Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Wed Jul 26 11:57:23 2017
Mapped Date : Thu Jan 17 18:07:58 2019
Design Summary
--------------
......@@ -103,9 +103,9 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 5.30
Peak Memory Usage: 932 MB
Total REAL time to MAP completion: 10 mins 15 secs
Total CPU time to MAP completion (all processors): 12 mins 13 secs
Peak Memory Usage: 698 MB
Total REAL time to MAP completion: 10 mins 18 secs
Total CPU time to MAP completion (all processors): 12 mins 34 secs
Table of Contents
-----------------
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