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MasterFIP - Gateware
Commit 92060d6f authored by Evangelia Gousiou's avatar Evangelia Gousiou
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small code cleanup

parent 1783cf48
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Showing with 281 additions and 163 deletions
rtl/fmc_masterFIP_core.vhd
View file @ 92060d6f
......@@ -119,8 +119,10 @@ architecture rtl of fmc_masterFIP_core is
signal core_sw_rst_p, core_sw_rst_n, fd_sw_rst_n : std_logic;
signal core_sw_rstn_lock : std_logic_vector (15 downto 0);
-- counters
signal macrocyc_lgth, turnar_lgth, silen_lgth : std_logic_vector (31 downto 0);
signal macrocyc_cnt, turnar_cnt, silen_cnt : std_logic_vector (31 downto 0);
signal macrocyc_lgth, turnar_lgth, silen_lgth : std_logic_vector (30 downto 0);
signal macrocyc_sw_load, turnar_sw_load, silen_sw_load : std_logic;
signal macrocyc_sw_load_p, turnar_sw_load_p, silen_sw_load_p : std_logic;
signal macrocyc_cnt, turnar_cnt, silen_cnt : std_logic_vector (30 downto 0);
signal macrocyc_cnt_zero_p, turnar_cnt_zero_p, silen_cnt_zero_p : std_logic;
-- tx
signal tx_rst, tx_start, tx_start_p : std_logic;
......@@ -163,7 +165,7 @@ begin
---------------------------------------------------------------------------------------------------
-- REGISTERS --
---------------------------------------------------------------------------------------------------
reg_control_block: fmc_masterfip_csr
cmp_masterfip_csr: fmc_masterfip_csr
port map(
-- wishbone
rst_n_i => rst_n,
......@@ -188,13 +190,17 @@ begin
mf_config_host_subs_o => open,
mf_config_fmc_bitrate_i => "01",
mf_config_fmc_bitrate_ok_i => '1',
-- counters
-- counters outputs
mf_macrocyc_lgth_o => macrocyc_lgth,
mf_macrocyc_start_o => macrocyc_sw_load,
mf_turnar_lgth_o => turnar_lgth,
mf_turnar_start_o => turnar_sw_load,
mf_silen_lgth_o => silen_lgth,
mf_macrocyc_time_cnt_i => macrocyc_cnt,
mf_turnar_time_cnt_i => turnar_cnt,
mf_silen_time_cnt_i => silen_cnt,
mf_silen_start_o => silen_sw_load,
-- counters inputs
mf_macrocyc_time_cnt_i => (macrocyc_cnt_zero_p or macrocyc_sw_load_p) & macrocyc_cnt,
mf_turnar_time_cnt_i => (tx_completed_p or turnar_sw_load_p) & turnar_cnt,
mf_silen_time_cnt_i => (tx_completed_p or silen_sw_load_p) & silen_cnt,
-- external sync pulse termination
mf_ext_sync_tstamp_i => "00000000000000000000000000000000",
-- tx control/status
......@@ -284,7 +290,7 @@ begin
---------------------------------------------------------------------------------------------------
-- resets --
---------------------------------------------------------------------------------------------------
sw_reset : process(clk_i)
cmp_sw_reset : process(clk_i)
begin
if rising_edge(clk_i) then
if(rst_n = '0') then
......@@ -307,46 +313,74 @@ begin
---------------------------------------------------------------------------------------------------
-- macrocycle counter --
---------------------------------------------------------------------------------------------------
macrocycle_cnt: decr_counter
generic map(width => 32)
cmp_macrocycle_cnt: decr_counter
generic map(width => 31)
port map(
clk_i => clk_i,
rst_i => core_rst,
counter_load_i => macrocyc_cnt_zero_p,
counter_load_i => macrocyc_cnt_zero_p or macrocyc_sw_load_p,
counter_top_i => macrocyc_lgth,
counter_o => macrocyc_cnt,
counter_is_zero_o => macrocyc_cnt_zero_p);
cmp_macrocyc_sw_load_p_detect: gc_sync_ffs
generic map(g_sync_edge => "positive")
port map(
clk_i => clk_i,
rst_n_i => rst_n,
data_i => macrocyc_sw_load,
ppulse_o => macrocyc_sw_load_p);
---------------------------------------------------------------------------------------------------
-- tournaround counter --
---------------------------------------------------------------------------------------------------
turnaround_cnt: decr_counter
generic map(width => 32)
cmp_turnaround_cnt: decr_counter
generic map(width => 31)
port map(
clk_i => clk_i,
rst_i => core_rst,
counter_load_i => tx_completed_p,
counter_load_i => tx_completed_p or turnar_sw_load_p,
counter_top_i => turnar_lgth,
counter_o => turnar_cnt,
counter_is_zero_o => turnar_cnt_zero_p);
turnar_sw_load_p_detect: gc_sync_ffs
generic map(g_sync_edge => "positive")
port map(
clk_i => clk_i,
rst_n_i => rst_n,
data_i => turnar_sw_load,
ppulse_o => turnar_sw_load_p);
--------------------------------------------------------------------------------------------------
-- silence counter --
--------------------------------------------------------------------------------------------------
silence_cnt: decr_counter
generic map(width => 32)
-- silence time: maximum amount of time that the masterFIP waits for a response frame.
-- the counting starts after an ID_DAT sent by the master (therefore loaded upon tx_completed_p)
-- or by the FES of an RP_DAT_MSG as a RP_FIN is expected afterwards
cmp_silence_cnt: decr_counter
generic map(width => 31)
port map(
clk_i => clk_i,
rst_i => core_rst,
counter_load_i => rx_fss_received_p,
counter_load_i => tx_completed_p or rx_frame_ok_p or silen_sw_load_p,
counter_top_i => silen_lgth,
counter_o => silen_cnt,
counter_is_zero_o => silen_cnt_zero_p);
cmp_silen_sw_load_p_detect: gc_sync_ffs
generic map(g_sync_edge => "positive")
port map(
clk_i => clk_i,
rst_n_i => rst_n,
data_i => silen_sw_load,
ppulse_o => silen_sw_load_p);
--------------------------------------------------------------------------------------------------
-- signals for tx --
--------------------------------------------------------------------------------------------------
tx_start_pulse_detect: gc_sync_ffs
cmp_tx_start_p_detect: gc_sync_ffs
generic map(g_sync_edge => "positive")
port map(
clk_i => clk_i,
......@@ -358,7 +392,7 @@ begin
--------------------------------------------------------------------------------------------------
-- signals for rx --
--------------------------------------------------------------------------------------------------
rx_extend_pulses : gc_extend_pulse
cmp_rx_extend_p : gc_extend_pulse
generic map (
g_width => 5000000)
port map (
......@@ -380,7 +414,7 @@ begin
---------------------------------------------------------------------------------------------------
-- rx --
---------------------------------------------------------------------------------------------------
FIELDRIVE_Receiver: masterfip_rx
cmp_masterfip_rx: masterfip_rx
port map(
uclk_i => clk_i,
core_rst_i => core_rst,
......@@ -403,7 +437,7 @@ begin
-- tx --
---------------------------------------------------------------------------------------------------
FIELDRIVE_Transmitter: masterfip_tx
cmp_masterfip_tx: masterfip_tx
port map(
uclk_i => clk_i,
core_rst_i => (core_rst or tx_rst),
......
rtl/fmc_masterFIP_mezzanine.vhd → rtl/fmc_masterFIP_mezz.vhd
View file @ 92060d6f
......@@ -7,10 +7,10 @@
---------------------------------------------------------------------------------------------------
-- |
-- fmc_masterFIP_mezzanine |
-- fmc_masterFIP_mezz |
-- |
---------------------------------------------------------------------------------------------------
-- File fmc_masterFIP_mezzanine.vhd |
-- File fmc_masterFIP_mezz.vhd |
-- |
-- Description The unit combines |
-- o the masterFIP core |
......@@ -89,9 +89,9 @@ use work.wishbone_pkg.all;
--=================================================================================================
-- Entity declaration for fmc_masterFIP_mezzanine
-- Entity declaration for fmc_masterFIP_mezz
--=================================================================================================
entity fmc_masterFIP_mezzanine is
entity fmc_masterFIP_mezz is
generic
(g_with_wrabbit_core : boolean := FALSE;
g_span : integer := 32;
......@@ -125,13 +125,13 @@ entity fmc_masterFIP_mezzanine is
wb_irq_o : out std_logic;
-- Aux
aux_o : out std_logic_vector(7 downto 0));
end fmc_masterFIP_mezzanine;
end fmc_masterFIP_mezz;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of fmc_masterFIP_mezzanine is
architecture rtl of fmc_masterFIP_mezz is
---------------------------------------------------------------------------------------------------
-- SDB CONSTANTS --
......@@ -201,7 +201,7 @@ begin
-- 0x13000 -> mezzanine board EEPROM I2C -not used
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_sdb_crossbar : xwb_sdb_crossbar
sdb_crossbar : xwb_sdb_crossbar
generic map
(g_num_masters => c_NUM_WB_SLAVES,
g_num_slaves => c_NUM_WB_MASTERS,
......@@ -234,7 +234,7 @@ begin
---------------------------------------------------------------------------------------------------
-- masterFIP CORE --
---------------------------------------------------------------------------------------------------
cmp_masterfip_core: fmc_masterFIP_core
masterfip_core: fmc_masterFIP_core
generic map
(g_span => g_span,
g_width => g_width,
......@@ -282,7 +282,7 @@ begin
-- WBGEN2 EMBEDDED INTERRUPTS CONTROLLER --
---------------------------------------------------------------------------------------------------
cmp_masterfip_eic : fmc_masterfip_eic
eic : fmc_masterfip_eic
port map
(clk_sys_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
......
rtl/fmc_masterfip_csr.vhd
View file @ 92060d6f
......@@ -2,11 +2,11 @@
-- Title : Wishbone slave core for FMC masterFIP core registers
---------------------------------------------------------------------------------------
-- File : fmc_masterfip_csr.vhd
-- Author : auto-generated by wbgen2 from masterfip.wb
-- Created : 07/17/15 11:34:40
-- Author : auto-generated by wbgen2 from fmc_masterfip_csr.wb
-- Created : 07/21/15 11:01:11
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE masterfip.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_masterfip_csr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
......@@ -45,11 +45,17 @@ entity fmc_masterfip_csr is
-- Port for BIT field: 'bit rate match' in reg: 'config from fmc'
mf_config_fmc_bitrate_ok_i : in std_logic;
-- Port for std_logic_vector field: 'macrocycle lgth' in reg: 'macrocycle lgth'
mf_macrocyc_lgth_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'turnaround time' in reg: 'turnaround time'
mf_turnar_lgth_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'silence time' in reg: 'silence time'
mf_silen_lgth_o : out std_logic_vector(31 downto 0);
mf_macrocyc_lgth_o : out std_logic_vector(30 downto 0);
-- Port for BIT field: 'macrocycle cnt start' in reg: 'macrocycle lgth'
mf_macrocyc_start_o : out std_logic;
-- Port for std_logic_vector field: 'turnaround time' in reg: 'turnaround lgth'
mf_turnar_lgth_o : out std_logic_vector(30 downto 0);
-- Port for BIT field: 'turnaround cnt start' in reg: 'turnaround lgth'
mf_turnar_start_o : out std_logic;
-- Port for std_logic_vector field: 'silence time' in reg: 'silence lgth'
mf_silen_lgth_o : out std_logic_vector(30 downto 0);
-- Port for BIT field: 'silence cnt start' in reg: 'silence lgth'
mf_silen_start_o : out std_logic;
-- Port for std_logic_vector field: 'macrocycle time counter' in reg: 'macrocycle time cnt'
mf_macrocyc_time_cnt_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'turnaround time counter' in reg: 'turnaround time cnt'
......@@ -224,9 +230,12 @@ signal mf_rst_fd_int : std_logic ;
signal mf_config_host_bitrate_int : std_logic_vector(1 downto 0);
signal mf_config_host_ext_sync_term_en_n_int : std_logic ;
signal mf_config_host_subs_int : std_logic_vector(7 downto 0);
signal mf_macrocyc_lgth_int : std_logic_vector(31 downto 0);
signal mf_turnar_lgth_int : std_logic_vector(31 downto 0);
signal mf_silen_lgth_int : std_logic_vector(31 downto 0);
signal mf_macrocyc_lgth_int : std_logic_vector(30 downto 0);
signal mf_macrocyc_start_int : std_logic ;
signal mf_turnar_lgth_int : std_logic_vector(30 downto 0);
signal mf_turnar_start_int : std_logic ;
signal mf_silen_lgth_int : std_logic_vector(30 downto 0);
signal mf_silen_start_int : std_logic ;
signal mf_tx_rst_int : std_logic ;
signal mf_tx_start_int : std_logic ;
signal mf_tx_bytes_num_int : std_logic_vector(8 downto 0);
......@@ -297,9 +306,12 @@ begin
mf_config_host_bitrate_int <= "00";
mf_config_host_ext_sync_term_en_n_int <= '0';
mf_config_host_subs_int <= "00000000";
mf_macrocyc_lgth_int <= "00000000000000000000000000000000";
mf_turnar_lgth_int <= "00000000000000000000000000000000";
mf_silen_lgth_int <= "00000000000000000000000000000000";
mf_macrocyc_lgth_int <= "0000000000000000000000000000000";
mf_macrocyc_start_int <= '0';
mf_turnar_lgth_int <= "0000000000000000000000000000000";
mf_turnar_start_int <= '0';
mf_silen_lgth_int <= "0000000000000000000000000000000";
mf_silen_start_int <= '0';
mf_tx_rst_int <= '0';
mf_tx_start_int <= '0';
mf_tx_bytes_num_int <= "000000000";
......@@ -467,23 +479,29 @@ begin
ack_in_progress <= '1';
when "0000100" =>
if (wb_we_i = '1') then
mf_macrocyc_lgth_int <= wrdata_reg(31 downto 0);
mf_macrocyc_lgth_int <= wrdata_reg(30 downto 0);
mf_macrocyc_start_int <= wrdata_reg(31);
end if;
rddata_reg(31 downto 0) <= mf_macrocyc_lgth_int;
rddata_reg(30 downto 0) <= mf_macrocyc_lgth_int;
rddata_reg(31) <= mf_macrocyc_start_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0000101" =>
if (wb_we_i = '1') then
mf_turnar_lgth_int <= wrdata_reg(31 downto 0);
mf_turnar_lgth_int <= wrdata_reg(30 downto 0);
mf_turnar_start_int <= wrdata_reg(31);
end if;
rddata_reg(31 downto 0) <= mf_turnar_lgth_int;
rddata_reg(30 downto 0) <= mf_turnar_lgth_int;
rddata_reg(31) <= mf_turnar_start_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0000110" =>
if (wb_we_i = '1') then
mf_silen_lgth_int <= wrdata_reg(31 downto 0);
mf_silen_lgth_int <= wrdata_reg(30 downto 0);
mf_silen_start_int <= wrdata_reg(31);
end if;
rddata_reg(31 downto 0) <= mf_silen_lgth_int;
rddata_reg(30 downto 0) <= mf_silen_lgth_int;
rddata_reg(31) <= mf_silen_start_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0000111" =>
......@@ -1188,10 +1206,16 @@ begin
-- bit rate match
-- macrocycle lgth
mf_macrocyc_lgth_o <= mf_macrocyc_lgth_int;
-- macrocycle cnt start
mf_macrocyc_start_o <= mf_macrocyc_start_int;
-- turnaround time
mf_turnar_lgth_o <= mf_turnar_lgth_int;
-- turnaround cnt start
mf_turnar_start_o <= mf_turnar_start_int;
-- silence time
mf_silen_lgth_o <= mf_silen_lgth_int;
-- silence cnt start
mf_silen_start_o <= mf_silen_start_int;
-- macrocycle time counter
-- turnaround time counter
-- silence time counter
......
rtl/masterFIP_pkg.vhd
View file @ 92060d6f
......@@ -193,7 +193,7 @@ package masterFIP_pkg is
---------------------------------------------------------------------------------------------------
component fmc_masterFIP_mezzanine is
component fmc_masterFIP_mezz is
generic
(g_with_wrabbit_core: boolean := FALSE;
g_span : integer := 32;
......@@ -248,9 +248,12 @@ package masterFIP_pkg is
mf_config_host_subs_o : out std_logic_vector(7 downto 0);
mf_config_fmc_bitrate_i : in std_logic_vector(1 downto 0);
mf_config_fmc_bitrate_ok_i : in std_logic;
mf_macrocyc_lgth_o : out std_logic_vector(31 downto 0);
mf_turnar_lgth_o : out std_logic_vector(31 downto 0);
mf_silen_lgth_o : out std_logic_vector(31 downto 0);
mf_macrocyc_lgth_o : out std_logic_vector(30 downto 0);
mf_macrocyc_start_o : out std_logic;
mf_turnar_lgth_o : out std_logic_vector(30 downto 0);
mf_turnar_start_o : out std_logic;
mf_silen_lgth_o : out std_logic_vector(30 downto 0);
mf_silen_start_o : out std_logic;
mf_macrocyc_time_cnt_i : in std_logic_vector(31 downto 0);
mf_turnar_time_cnt_i : in std_logic_vector(31 downto 0);
mf_silen_time_cnt_i : in std_logic_vector(31 downto 0);
......
rtl/masterfip_rx.vhd
View file @ 92060d6f
......@@ -160,7 +160,7 @@ begin
-- Deglitcher --
---------------------------------------------------------------------------------------------------
FIELDRIVE_Receiver_Deglitcher: wf_rx_deglitcher
cmp_rx_deglitcher: wf_rx_deglitcher
port map(
uclk_i => uclk_i,
nfip_rst_i => core_rst_i,
......@@ -179,7 +179,7 @@ begin
-- Oscillator --
---------------------------------------------------------------------------------------------------
FIELDRIVE_Receiver_Oscillator: wf_rx_osc
cmp_rx_osc: wf_rx_osc
port map(
uclk_i => uclk_i,
rate_i => rate_i,
......@@ -199,7 +199,7 @@ begin
-- Deserializer --
---------------------------------------------------------------------------------------------------
FIELDRIVE_Receiver_Deserializer: wf_rx_deserializer
cmp_rx_deserializer: wf_rx_deserializer
port map(
uclk_i => uclk_i,
nfip_rst_i => core_rst_i,
......@@ -226,7 +226,7 @@ begin
---------------------------------------------------------------------------------------------------
-- bytes counter --
---------------------------------------------------------------------------------------------------
Rx_Bytes_Counter: wf_incr_counter
cmp_rx_bytes_cnt: wf_incr_counter
generic map(g_counter_lgth => 8)
port map(
uclk_i => uclk_i,
......@@ -276,7 +276,7 @@ begin
---------------------------------------------------------------------------------------------------
-- Synchronous process Data_Transfer_To_Regs: transfer 32bit words to the cons_frame registers
Data_Transfer_To_Regs: process (uclk_i)
data_transfer_to_regs: process (uclk_i)
begin
if rising_edge (uclk_i) then
if core_rst_i = '1' or rx_rst_i = '1' then
......
rtl/masterfip_tx.vhd
View file @ 92060d6f
......@@ -163,7 +163,7 @@ begin
-- Copy of the frame data --
---------------------------------------------------------------------------------------------------
-- Copying of the data so that they are kept static locally upon the tx_start_p_i.
Data_copy: process (uclk_i)
copy_data: process (uclk_i)
begin
if rising_edge (uclk_i) then
if core_rst_i = '1' then
......@@ -183,7 +183,7 @@ begin
---------------------------------------------------------------------------------------------------
-- Select the right byte --
---------------------------------------------------------------------------------------------------
Bytes_selection: process (uclk_i)
select_byte: process (uclk_i)
begin
if rising_edge (uclk_i) then
if core_rst_i = '1' then
......@@ -210,7 +210,7 @@ begin
-- being produced. The same counter is used for the question (ID) and response (RP) frames that
-- are being produced.
Prod_Bytes_Counter: wf_incr_counter
cmp_tx_bytes_cnt: wf_incr_counter
generic map(g_counter_lgth => 8)
port map(
uclk_i => uclk_i,
......@@ -226,7 +226,7 @@ begin
tx_byte_index_o <= std_logic_vector(prod_bytes_c);
process (uclk_i)
synch_signals: process (uclk_i)
begin
if rising_edge (uclk_i) then
if core_rst_i = '1' then
......@@ -255,7 +255,7 @@ begin
-- Oscillator --
---------------------------------------------------------------------------------------------------
tx_oscillator: wf_tx_osc
cmp_tx_osc: wf_tx_osc
port map(
uclk_i => uclk_i,
rate_i => rate_i,
......@@ -271,7 +271,7 @@ begin
-- Serializer --
---------------------------------------------------------------------------------------------------
tx_serializer: wf_tx_serializer
cmp_tx_serializer: wf_tx_serializer
port map(
uclk_i => uclk_i,
nfip_rst_i => core_rst_i,
......
rtl/wbgen/masterfip_csr.wb → rtl/wbgen/fmc_masterfip_csr.wb
View file @ 92060d6f
......@@ -140,44 +140,71 @@ peripheral {
-------------------------------------------------------------------------------
reg {
name = "macrocycle lgth";
prefix = "macrocyc_lgth";
prefix = "macrocyc";
field {
name = "macrocycle lgth";
description = "duration of the macrocycle in number of clk ticks";
description = "duration of the macrocycle in number of 25ns-clk-ticks";
prefix = "lgth";
type = SLV;
size = 32;
size = 31;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "macrocycle cnt start";
description = "initiates the counting of the macrocycle counter";
prefix = "start";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "turnaround time";
prefix = "turnar_lgth";
name = "turnaround lgth";
prefix = "turnar";
field {
name = "turnaround time";
description = "turnaround time (i.e. time between two frames sent by the masterFIP) in clk ticks";
description = "turnaround time (i.e. time between two frames sent by the masterFIP) in number of 25ns-clk-ticks";
prefix = "lgth";
type = SLV;
size = 32;
size = 31;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
field {
name = "turnaround cnt start";
description = "initiates the counting of the turnaround counter";
prefix = "start";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "silence time";
prefix = "silen_lgth";
name = "silence lgth";
prefix = "silen";
field {
name = "silence time";
description = "silence time (i.e. time that the masterFIP waits for a response frame) in clk ticks";
description = "silence time (i.e. time that the masterFIP waits for a response frame) number of 25ns-clk-ticks";
prefix = "lgth";
type = SLV;
size = 32;
size = 31;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
field {
name = "silence cnt start";
description = "initiates the counting of the silence counter";
prefix = "start";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
......
sim/spec/data_vectors/masterFIP_test.vec
View file @ 92060d6f
......@@ -27,8 +27,7 @@ wait %d900
-------------------------------------------------------------------------------
-- Access the tdc core register space
-------------------------------------------------------------------------------
--------------- RESETS ---------------
-- reset inactive
wr 0000000000050000 F CAFE0003
wait %d20
......@@ -41,6 +40,20 @@ wait %d20
wr 0000000000050000 F CAFE0003
wait %d20
----- CHECK COUNTERS FUNCTINALITY -----
-- turnar counter top
wr 0000000000050014 F 000007D0
wait %d20
-- silen counter top
wr 0000000000050018 F 00000FA0
wait %d20
-- macrocycle cnt start
wr 0000000000050010 F 80007D00
wait %d20
--------------- ID_DAT ---------------
-- control byte of id_dat
wr 00000000000500C0 F 00000003
......@@ -101,6 +114,9 @@ wait %d20
wr 000000000005002C F 00000202
wait %d20
-- deactivate tx_start
wr 000000000005002C F 00000000
-- release rx_rst
wr 0000000000050038 F 00000000
wait %d40000
......@@ -109,3 +125,17 @@ wait %d40000
rd 0000000000050040 F 00000002
wait %d20
rd 0000000000050044 F 00000050
--------------- RP_FIN ---------------
-- control byte of rp_fin
wr 00000000000500C4 F 00000040
wait %d20
-- rx_rst
wr 0000000000050038 F 00000001
wait %d20
-- tx_start
wr 000000000005002C F 00000002
wait %d20000
\ No newline at end of file
syn/spec/spec_masterFIP.xise
View file @ 92060d6f
This diff is collapsed.
top/spec/spec_masterFIP.vhd
View file @ 92060d6f
......@@ -251,7 +251,7 @@ begin
-- 125 MHz clk and Reset for TDC core --
---------------------------------------------------------------------------------------------------
spec_clk_ibuf : IBUFG
cmp_spec_clk_ibuf : IBUFG
port map
(I => clk_20m_vcxo_i,
O => clk_20m_vcxo_buf);
......@@ -289,7 +289,7 @@ begin
CLKFBIN => pllout_clk_sys_fb,
CLKIN => clk_20m_vcxo_buf);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_clk_sys_buf : BUFG
cmp_sys_clk_buf : BUFG
port map
(O => clk_40m_sys,
I => pllout_clk_sys);
......@@ -299,7 +299,7 @@ begin
-- Reset for 62.5 MHz clk domain --
---------------------------------------------------------------------------------------------------
U_Reset_Generator : spec_reset_gen
cmp_spec_rst_gen : spec_reset_gen
port map
(clk_sys_i => clk_40m_sys,
rst_pcie_n_a_i => rst_n_a_i,
......@@ -414,7 +414,7 @@ begin
---------------------------------------------------------------------------------------------------
-- masterFIP BOARD --
---------------------------------------------------------------------------------------------------
cmp_masterFIP_mezz : fmc_masterFIP_mezzanine
cmp_masterFIP_mezz : fmc_masterFIP_mezz
generic map
(g_span => g_span,
g_width => g_width,
......@@ -499,7 +499,7 @@ begin
---------------------------------------------------------------------------------------------------
-- Information on carrier type, mezzanine presence, pcb version
cmp_carrier_info : carrier_info
cmp_carrier_csr : carrier_info
port map
(rst_n_i => rst_sys_n,
clk_sys_i => clk_40m_sys,
......@@ -558,7 +558,7 @@ begin
led_green_o <= led_clk_40m_aux(0);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_drive_SPEC_red_led: gc_extend_pulse
spec_red_led: gc_extend_pulse
generic map
(g_width => 5000000)
port map
......
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