folders cleanup; renamed masterFIP to masterfip

8aa9f25a · Evangelia Gousiou · 0cd00619 · 0cd00619 · 8aa9f25a · 8aa9f25a
Commit 8aa9f25a authored Jan 29, 2016 by Evangelia Gousiou
9 changed files
--- a/rtl/fmc_masterfip_eic.vhd
+++ b/rtl/fmc_masterfip_eic.vhd
--- a/rtl/wbgen/fmc_masterfip_csr.h
+++ b/rtl/wbgen/fmc_masterfip_csr.h
--- a/rtl/wbgen/fmc_masterfip_csr.htm
+++ b/rtl/wbgen/fmc_masterfip_csr.htm
--- a/rtl/wbgen/fmc_masterfip_eic.wb
+++ b/rtl/wbgen/fmc_masterfip_eic.wb
-peripheral {
-    name = "masterFIP EIC";
-    description = "FMC masterfip embedded interrrupt controller.";
-    hdl_entity = "fmc_masterfip_eic";
-    prefix = "fmc_masterfip_eic";
-
-
-    irq {
-            name = "start new macrocycle";
-            description = "start new macrocycle either because there is a new sync pulse or because the counter expired (rising edge sensitive).";
-            prefix = "macrocy_start";
-            trigger = EDGE_RISING;
-        };
-		
-    irq {
-            name = "silence time expired";
-            description = "silence time expired(rising edge sensitive).";
-            prefix = "silen_time_expire";
-            trigger = EDGE_RISING;
-        };
-
-    irq {
-            name = "turnaround time expired";
-            description = "turnaround time expired(rising edge sensitive).";
-            prefix = "turnar_time_expire";
-            trigger = EDGE_RISING;
-        };
-
-    irq {
-            name = "end of frame transmission";
-            description = "end of frame transmission(rising edge sensitive).";
-            prefix = "tx_completed";
-            trigger = EDGE_RISING;
-        };
-
-    irq {
-            name = "reception of a new fss";
-            description = "reception of a new fss(rising edge sensitive).";
-            prefix = "rx_fss_ok";
-            trigger = EDGE_RISING;
-        };
-		
-    irq {
-            name = "reception of a new complete frame";
-            description = "reception of a new complete frame(rising edge sensitive).";
-            prefix = "rx_frame_ok";
-            trigger = EDGE_RISING;
-        };
-		
-    irq {
-            name = "reception of a frame with wrong crc";
-            description = "reception of a frame with wrong crc(rising edge sensitive).";
-            prefix = "rx_crc_wrong";
-            trigger = EDGE_RISING;
-        };		
-};
--- a/syn/spec/spec_masterFIP.xise
+++ b/syn/spec/spec_masterFIP.xise
--- a/syn/spec_mt/spec_masterfip_wrnode.xise
+++ b/syn/spec_mt/spec_masterfip_wrnode.xise
--- a/top/spec/spec_masterFIP.ucf
+++ b/top/spec/spec_masterFIP.ucf
--- a/top/spec/spec_masterFIP.vhd
+++ b/top/spec/spec_masterFIP.vhd
@@ -7,10 +7,10 @@

 ---------------------------------------------------------------------------------------------------
 --                                                                                                |
--                                        spec_masterFIP                                          |
+--                                        spec_masterfip                                          |
 --                                                                                                |
 ---------------------------------------------------------------------------------------------------
-- File         spec_masterFIP.vhd                                                                |
+-- File         spec_masterfip.vhd                                                                |
 --                                                                                                |
 -- Description  Top level of a simple masterFIP on a SPEC carrier.                                |
 --              Figure 1 shows the architecture of the unit.                                      |
@@ -95,9 +95,9 @@ library UNISIM;
 use UNISIM.vcomponents.all;

 --=================================================================================================
--                            Entity declaration for spec_masterFIP
+--                            Entity declaration for spec_masterfip
 --=================================================================================================
-entity spec_masterFIP is
+entity spec_masterfip is
  generic
    (g_span             : integer := 32;                      -- address span in bus interfaces
     g_width            : integer := 32;                      -- data width in bus interfaces
@@ -176,12 +176,12 @@ entity spec_masterFIP is
     led_rx_err_n_o     : out   std_logic;
     led_rx_act_n_o     : out   std_logic);

-end spec_masterFIP;
+end spec_masterfip;

 --=================================================================================================
 --                                    architecture declaration
 --=================================================================================================
-architecture rtl of spec_masterFIP is
+architecture rtl of spec_masterfip is

 ---------------------------------------------------------------------------------------------------
 --                                         SDB CONSTANTS                                         --

--- a/top/spec_mt/spec_masterfip_mt.vhd
+++ b/top/spec_mt/spec_masterfip_mt.vhd
@@ -2,7 +2,7 @@
 -- Title      : WR Node Core Example Design (SPEC)
 -- Project    : WR Node Core
 -------------------------------------------------------------------------------
-- File       : spec_top.vhd
+-- File       : spec_masterfip_mt.vhd
 -- Author     : Tomasz Włostowski
 -- Company    : CERN BE-CO-HT
 -- Created    : 2014-04-01
@@ -58,7 +58,7 @@ use work.gencores_pkg.all;
 library unisim;
 use unisim.vcomponents.all;

-entity spec_top is
+entity spec_masterfip_mt is
  generic (g_simulation : boolean := false);

  port
@@ -143,9 +143,9 @@ entity spec_top is
     led_rx_act_n_o      : out   std_logic;
     led_out_of_sync_n_o : out   std_logic;
     led_sync_n_o        : out   std_logic);
-end spec_top;
+end spec_masterfip_mt;

-architecture rtl of spec_top is
+architecture rtl of spec_masterfip_mt is

  -- TODO: check comments on the WRNC..