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MasterFIP - Gateware
Commit 89953bc8 authored by Evangelia Gousiou's avatar Evangelia Gousiou
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added 1-wire temperature and unique id reading

parent 462ce06a
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rtl/fmc_masterFIP_core.vhd
View file @ 89953bc8
......@@ -121,6 +121,7 @@
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.masterFIP_pkg.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
......@@ -139,14 +140,17 @@ entity fmc_masterFIP_core is
values_for_simul : boolean := FALSE); -- this generic is set to TRUE when instantiated in a test-bench
port
(-- Clock and reset
clk_i : in std_logic; -- 40 MHz clock
clk_i : in std_logic; -- 100 MHz clock
clk_40m_i : in std_logic; -- 40 MHz clock
rst_i : in std_logic; -- PoR or PCIe reset, synched with the clk_i
-- Bus Speed -- 31.25 Kbps: speed_b1 = 0, speed_b0 = 0
speed_b0_i : in std_logic; -- 1 Mbps : speed_b1 = 0, speed_b0 = 1
speed_b1_i : in std_logic; -- 2.5 Mbps : speed_b1 = 1, speed_b0 = 0
-- 5 Mbps : speed_b1 = 1, speed_b0 = 1
-- One wire DS18B20U+
carrier_onewire_b : inout std_logic; -- 1-wire
-- External synchronisation pulse transceiver
ext_sync_term_en_o : out std_logic; -- enable 50 Ohms termination of the pulse
ext_sync_dir_o : out std_logic; -- transceiver direction
......@@ -250,6 +254,14 @@ architecture rtl of fmc_masterFIP_core is
signal mf_dbg : std_logic_vector(31 downto 0);
signal mf_dbg_p, mf_dbg_p_ext : std_logic;
-- prescaler should be (clock_speed/desired_clock_speed)/2 because you want a rising edge every period
signal prescaler : STD_LOGIC_VECTOR(25 downto 0) := "10111110101111000010000000"; -- 12,500,000 in binary
signal prescaler_counter : STD_LOGIC_VECTOR(25 downto 0) := (others => '0');
signal clk_1m : std_logic;
signal temper, temp_temper : std_logic_vector(15 downto 0);
signal id, temp_id : std_logic_vector(63 downto 0);
signal onewire_read_p, pps_is_zero, pps_load_p : std_logic;
-- chipscope
-- component chipscope_ila
-- port (
......@@ -490,7 +502,10 @@ begin
mf_tx_data_reg64_o => tx_frame(63),
mf_tx_data_reg65_o => tx_frame(64),
mf_tx_data_reg66_o => tx_frame(65),
mf_tx_data_reg67_o => tx_frame(66));
mf_tx_data_reg67_o => tx_frame(66),
mf_onewire_temper_i => temper,
mf_onewire_id_lsb_i => id(31 downto 0),
mf_onewire_id_msb_i => id(63 downto 32));
adc_sec_conn_n_o <= '0' when adc_sec_conn_n = '0' else 'Z';
adc_prim_conn_n_o <= '0' when adc_prim_conn_n = '0' else 'Z';
......@@ -860,7 +875,86 @@ begin
dac_sclk_o => dac_sclk_o,
dac_din_o => dac_din_o);
---------------------------------------------------------------------------------------------------
-- one wire --
---------------------------------------------------------------------------------------------------
cmp_temper_onewire: serialIdTempInt
generic map(FREQ => 40)
port map(
Clk => clk_40m_i,
RstN => core_rst_n,
SerialId => carrier_onewire_b,
Id => temp_id,
Temp => temp_temper,
IdRead => onewire_read_p,
Pps => pps_is_zero);
-- generate_1m_clk: process(clk_i, clk_1m)
-- begin
-- if rising_edge(clk_i) then
-- prescaler_counter <= prescaler_counter + 1;
-- if(prescaler_counter > prescaler) then
-- -- -- Iterate
-- clk_1m <= not clk_1m;
-- prescaler_counter <= (others => '0');
-- end if;
-- end if;
-- end process;
cmp_pps_gen: wf_decr_counter
generic map(g_counter_lgth => 26)
port map
(uclk_i => clk_40m_i,
counter_rst_i => core_rst,
counter_decr_i => '1',
counter_load_i => pps_load_p,
counter_top_i => "10011000100101101000000000", -- 40000000 * 25 ns = 1s
counter_o => open,
counter_is_zero_o => pps_is_zero);
-- -- -- -- -- -- -- -- -- -- --
pps_load_p <= pps_is_zero or core_rst;
latch: process(clk_i)
begin
if rising_edge(clk_i) then
temper <= (others => '0');
id <= (others => '0');
if(onewire_read_p = '1') then
temper <= temp_temper;
id <= temp_id;
end if;
end if;
end process;
cmp_ow_read_p: gc_extend_pulse
generic map
(g_width => 1000000) -- ns -> ms
port map
(clk_i => clk_40m_i,
rst_n_i => core_rst_n,
pulse_i => onewire_read_p,
extended_o => aux_o(2));
cmp_ow_pps_p: gc_extend_pulse
generic map
(g_width => 1000000) -- ns -> ms
port map
(clk_i => clk_40m_i,
rst_n_i => core_rst_n,
pulse_i => pps_is_zero,
extended_o => aux_o(3));
-- cmp_temper_onewire: temperature
-- port map
-- (clk1m => clk_1m,
-- temper => temp_temper,
-- wireout=> carrier_onewire_b);
---------------------------------------------------------------------------------------------------
-- LEDs --
---------------------------------------------------------------------------------------------------
......@@ -891,10 +985,10 @@ begin
aux_o(6) <= mf_dbg_p_ext;--macrocyc_host_load_p;
aux_o(5) <= mf_dbg(5);--macrocyc_load_p;
aux_o(4) <= mf_dbg(4);--rx_byte_ready_p;
aux_o(3) <= mf_dbg(3);--macrocyc_cnt_zero_p;
aux_o(2) <= mf_dbg(2);--core_rst;--ext_sync_p;--tx_completed;
aux_o(1) <= mf_dbg(1);--tx_start;
aux_o(0) <= mf_dbg(0);--sync_led;
--aux_o(3) <= mf_dbg(3);--macrocyc_cnt_zero_p;
--aux_o(2) <= mf_dbg(2);--core_rst;--ext_sync_p;--tx_completed;
aux_o(1) <= onewire_read_p;--mf_dbg(1);--tx_start;
aux_o(0) <= pps_is_zero;--mf_dbg(0);--sync_led;
ext_sync_oe_o <= ext_sync_oe;
......
rtl/fmc_masterfip_csr.vhd
View file @ 89953bc8
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fmc_masterfip_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_masterfip_csr.wb
-- Created : 03/17/16 18:51:54
-- Created : 07/22/16 18:25:41
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_masterfip_csr.wb
......@@ -384,7 +384,13 @@ entity fmc_masterfip_csr is
-- Port for std_logic_vector field: 'reg66' in reg: 'tx data reg66'
mf_tx_data_reg66_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg67' in reg: 'tx data reg67'
mf_tx_data_reg67_o : out std_logic_vector(31 downto 0)
mf_tx_data_reg67_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'onewire temperature' in reg: 'onewire temperature'
mf_onewire_temper_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'onewire id lsb' in reg: 'onewire id lsb'
mf_onewire_id_lsb_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'onewire id msb' in reg: 'onewire id msb'
mf_onewire_id_msb_i : in std_logic_vector(31 downto 0)
);
end fmc_masterfip_csr;
......@@ -1972,6 +1978,40 @@ begin
rddata_reg(31 downto 0) <= mf_tx_data_reg67_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10011111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(15 downto 0) <= mf_onewire_temper_i;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10100000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_onewire_id_lsb_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10100001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_onewire_id_msb_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
......@@ -2356,6 +2396,9 @@ begin
mf_tx_data_reg66_o <= mf_tx_data_reg66_int;
-- reg67
mf_tx_data_reg67_o <= mf_tx_data_reg67_int;
-- onewire temperature
-- onewire id lsb
-- onewire id msb
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
......
rtl/masterFIP_pkg.vhd
View file @ 89953bc8
......@@ -381,7 +381,10 @@ package masterFIP_pkg is
mf_tx_data_reg64_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg65_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg66_o : out std_logic_vector(31 downto 0);
mf_tx_data_reg67_o : out std_logic_vector(31 downto 0));
mf_tx_data_reg67_o : out std_logic_vector(31 downto 0);
mf_onewire_temper_i : in std_logic_vector(15 downto 0);
mf_onewire_id_lsb_i : in std_logic_vector(31 downto 0);
mf_onewire_id_msb_i : in std_logic_vector(31 downto 0));
end component;
---------------------------------------------------------------------------------------------------
......@@ -392,9 +395,11 @@ package masterFIP_pkg is
values_for_simul : boolean := FALSE);
port
(clk_i : in std_logic;
clk_40m_i : in std_logic; -- 40 MHz clock
rst_i : in std_logic;
speed_b0_i : in std_logic;
speed_b1_i : in std_logic;
carrier_onewire_b : inout std_logic;
fd_rxcdn_i : in std_logic;
fd_rxd_i : in std_logic;
fd_txer_i : in std_logic;
......@@ -439,6 +444,35 @@ package masterFIP_pkg is
end component;
component temperature is
port
(
clk1m: in std_logic;
temper: out std_logic_vector(15 downto 0);
wireout: inout std_logic
);
end component;
component serialIdTempInt is
generic (
FREQ : integer := 40 --Frequency in MHz
);
port(
Clk : in std_logic;
RstN : in std_logic;
SerialId : inout std_logic; -- IO to be connected to the chip (DS1822)
Id : out std_logic_vector(63 downto 0); -- ID value
Temp : out std_logic_vector(15 downto 0); -- Temperature value (refreshed every second)
IdRead : out std_logic; -- ID value is valid
Pps : in std_logic; -- Pulse per second (for temperature read)
IdOk : out std_logic -- Same as IdRead, but not reset with RstN !!
);
end component;
---------------------------------------------------------------------------------------------------
component carrier_info
port
......
rtl/serialIdTempInt.vhd 0 → 100644
View file @ 89953bc8
This diff is collapsed.
rtl/wbgen/fmc_masterfip_csr.h
View file @ 89953bc8
......@@ -3,7 +3,7 @@
* File : fmc_masterfip_csr.h
* Author : auto-generated by wbgen2 from fmc_masterfip_csr.wb
* Created : 03/17/16 18:51:55
* Created : 07/22/16 18:25:41
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_masterfip_csr.wb
......@@ -471,6 +471,12 @@
/* definitions for register: tx data reg66 */
/* definitions for register: tx data reg67 */
/* definitions for register: onewire temperature */
/* definitions for register: onewire id lsb */
/* definitions for register: onewire id msb */
/* [0x0]: REG rst */
#define MF_REG_RST 0x00000000
/* [0x4]: REG id */
......@@ -789,4 +795,10 @@
#define MF_REG_TX_DATA_REG66 0x00000274
/* [0x278]: REG tx data reg67 */
#define MF_REG_TX_DATA_REG67 0x00000278
/* [0x27c]: REG onewire temperature */
#define MF_REG_ONEWIRE_TEMPER 0x0000027c
/* [0x280]: REG onewire id lsb */
#define MF_REG_ONEWIRE_ID_LSB 0x00000280
/* [0x284]: REG onewire id msb */
#define MF_REG_ONEWIRE_ID_MSB 0x00000284
#endif
rtl/wbgen/fmc_masterfip_csr.htm
View file @ 89953bc8
This diff is collapsed.
rtl/wbgen/fmc_masterfip_csr.wb
View file @ 89953bc8
......@@ -67,6 +67,7 @@ peripheral {
};
};
-------------------------------------------------------------------------------
-- ADC power supplies --
-------------------------------------------------------------------------------
......@@ -416,8 +417,10 @@ peripheral {
field {
name = "tx number of bytes";
description = "number of bytes to serialize; the masterFIP_core samples this upon the tx_strt;\
note that the max WorldFIP frame size = 263 bytes (without preamble, CRC, postamble)";
description = "number of bytes to serialize; the number should include all the bytes in the Control and Data fields\
of a frame and not include the bytes in the Preamble, CRC, Postamble fields; the masterFIP_core samples\
this number upon the tx_strt; note that for the max supported WorldFIP frame, which is a message of\
256 Data bytes, the number of bytes to serialize = 263 (Control byte+6 address bytes+256 Data bytes)";
prefix = "bytes_num";
type = SLV;
size = 16;
......@@ -2672,5 +2675,61 @@ peripheral {
access_dev = READ_ONLY;
};
};
-------------------------------------------------------------------------------
-- one wire --
-------------------------------------------------------------------------------
reg {
name = "onewire temperature";
description = "raw temperature data from the one wire DS18B20U+;\
the register is 2-bytes long; it translates to oC as follows:\
temp = ((byte1 << 8) | byte0) / 16.0";
prefix = "onewire_temper";
field {
name = "onewire temperature";
size = 16;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "onewire id lsb";
description = "id (lsb) read from the one wire DS18B20U+";
prefix = "onewire_id_lsb";
field {
name = "onewire id lsb";
size = 32;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "onewire id msb";
description = "id (msb) read from the one wire DS18B20U+";
prefix = "onewire_id_msb";
field {
name = "onewire id msb";
size = 32;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
\ No newline at end of file
syn/spec/spec_masterfip.xise
View file @ 89953bc8
This diff is collapsed.
syn/spec/tb_masterFIP.fdo
View file @ 89953bc8
######################################################################
##
## Filename: tb_masterFIP.fdo
## Created on: Thu Apr 21 18:04:40 W. Europe Daylight Time 2016
## Created on: Fri Jul 22 18:19:57 W. Europe Daylight Time 2016
##
## Auto generated by Project Navigator for Behavioral Simulation
##
......@@ -88,6 +88,7 @@ vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_cons_bytes_processor.vhd"
vcom -explicit -93 "../../sim/spec/testbench/gnum_model/textutil.vhd"
vcom -explicit -93 "../../sim/spec/testbench/encounter.vhd"
vcom -explicit -93 "../../rtl/serialIdTempInt.vhd"
vcom -explicit -93 "../../rtl/masterfip_tx.vhd"
vcom -explicit -93 "../../rtl/masterfip_rx.vhd"
vcom -explicit -93 "../../rtl/incr_counter.vhd"
......
top/spec/spec_masterfip.vhd
View file @ 89953bc8
......@@ -241,7 +241,7 @@ architecture rtl of spec_masterfip is
signal led_clk_100m_aux : std_logic_vector(7 downto 0);
signal rx_err, rx_act, fd_txena : std_logic;
signal pllout_clk_40m, clk_40m : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
......@@ -268,7 +268,7 @@ begin
CLKOUT0_DIVIDE => 10, -- 100 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 8,
CLKOUT1_DIVIDE => 25,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 16,
......@@ -279,7 +279,7 @@ begin
port map
(CLKFBOUT => pllout_clk_sys_fb,
CLKOUT0 => pllout_clk_sys,
CLKOUT1 => open,
CLKOUT1 => pllout_clk_40m,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
......@@ -290,11 +290,15 @@ begin
CLKIN => clk_20m_vcxo_buf);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_sys_clk_buf : BUFG
cmp_clk_sys_100m_buf : BUFG
port map
(O => clk_100m_sys,
I => pllout_clk_sys);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_clk_40m_buf : BUFG
port map
(O => clk_40m,
I => pllout_clk_40m);
---------------------------------------------------------------------------------------------------
-- RESET --
......@@ -428,10 +432,13 @@ begin
values_for_simul => FALSE)
port map
(clk_i => clk_100m_sys,
clk_40m_i => clk_40m,
rst_i => rst_sys,
-- Bus speed
speed_b0_i => speed_b0_i,
speed_b1_i => speed_b1_i,
-- One Wire
carrier_onewire_b => carrier_onewire_b,
-- FielDrive
fd_rxcdn_i => fd_rxcdn_i,
fd_rxd_i => fd_rxd_i,
......@@ -477,10 +484,10 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- LEDs font panel
led_tx_err_n_o <= fd_txer_i;
led_tx_act_n_o <= fd_txena;
led_rx_err_n_o <= rx_err;
led_rx_act_n_o <= rx_act;
-- led_tx_err_n_o <= fd_txer_i;
-- led_tx_act_n_o <= fd_txena;
-- led_rx_err_n_o <= rx_err;
-- led_rx_act_n_o <= rx_act;
cmp_rx_err_extend_p: gc_extend_pulse
generic map (g_width => 50000)
......@@ -601,7 +608,13 @@ begin
pulse_i => (aux(0)),
extended_o => led_red_o);
led_tx_act_n_o <= aux(0); -- R5
led_tx_err_n_o <= aux(1); -- R8
led_rx_act_n_o <= aux(2); -- R6
led_rx_err_n_o <= aux(3); -- R9
end rtl;
----------------------------------------------------------------------------------------------------
-- architecture ends
......
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