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M
MasterFIP - Gateware
Commit 2cb72689 authored by Evangelia Gousiou's avatar Evangelia Gousiou Committed by Evangelia Gousiou
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changed to gitlab mockturtle submodule

parent 03524e4d
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.gitmodules
View file @ 2cb72689
......@@ -12,4 +12,7 @@
url = git://ohwr.org/hdl-core-lib/wr-cores.git
[submodule "ip_cores/etherbone-core"]
path = ip_cores/etherbone-core
url = git://ohwr.org/hdl-core-lib/etherbone-core.git
\ No newline at end of file
url = git://ohwr.org/hdl-core-lib/etherbone-core.git
[submodule "ip_cores/mockturtle"]
path = ip_cores/mockturtle
url = https://gitlab.cern.ch/coht/mockturtle.git
mockturtle @ bb80c5b3
Subproject commit bb80c5b3009265db7d3fc595d859350a68cdf881
syn/spec/spec_masterfip_mt.par
View file @ 2cb72689
......@@ -3,7 +3,7 @@ Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
PCBE13457:: Thu Jan 17 18:18:19 2019
par -w -intstyle ise -ol high -xe n -mt off spec_masterfip_mt_map.ncd
par -w -intstyle ise -ol high -xe n -mt off spec_masterfip_mt_map.ncd
spec_masterfip_mt.ncd spec_masterfip_mt.pcf
......@@ -108,7 +108,7 @@ Specific Feature Utilization:
Overall effort level (-ol): High
Router effort level (-rl): High
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
Starting initial Timing Analysis. REAL time: 18 secs
Finished initial Timing Analysis. REAL time: 18 secs
......@@ -122,65 +122,65 @@ WARNING:Par:288 - The signal fmc_prsnt_m2c_n_i_IBUF has no load. PAR will not a
WARNING:Par:288 - The signal l2p_rdy_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal l_wr_rdy_i<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal l_wr_rdy_i<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
/Mram_ram2_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
/Mram_ram5_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
/Mram_ram2_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
/Mram_ram1_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
/Mram_ram5_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
/Mram_ram4_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
/Mram_ram2_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
/Mram_ram1_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
/Mram_ram3_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
/Mram_ram1_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
/Mram_ram4_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
/Mram_ram3_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
/Mram_ram3_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
/Mram_ram1_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
/Mram_ram3_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
/Mram_ram2_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
/Mram_ram4_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
/Mram_ram5_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
/Mram_ram5_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
/Mram_ram4_RAMD_D1_O has no load. PAR will not attempt to route this signal.
Starting Router
......
syn/spec/spec_masterfip_mt.twr
View file @ 2cb72689
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syn/spec/spec_masterfip_mt.xise
View file @ 2cb72689
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syn/spec/spec_masterfip_mt_map.mrp
View file @ 2cb72689
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