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-- Title          : Wishbone slave core for FMC masterFIP core registers
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-- File           : fmc_masterfip_csr.vhd
-- Author         : auto-generated by wbgen2 from masterfip.wb
-- Created        : 07/17/15 11:34:40
-- Standard       : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE masterfip.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity fmc_masterfip_csr is
  port (
    rst_n_i                                  : in     std_logic;
    clk_sys_i                                : in     std_logic;
    wb_adr_i                                 : in     std_logic_vector(6 downto 0);
    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
    wb_cyc_i                                 : in     std_logic;
    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
    wb_stb_i                                 : in     std_logic;
    wb_we_i                                  : in     std_logic;
    wb_ack_o                                 : out    std_logic;
    wb_stall_o                               : out    std_logic;
-- Port for BIT field: 'reset of the masterFIP core' in reg: 'rst'
    mf_rst_core_o                            : out    std_logic;
-- Port for BIT field: 'reset of the fieldrive chip (FD_RSTN)' in reg: 'rst'
    mf_rst_fd_o                              : out    std_logic;
-- Ports for PASS_THROUGH field: 'reset magic value' in reg: 'rst'
    mf_rst_lock_o                            : out    std_logic_vector(15 downto 0);
    mf_rst_lock_wr_o                         : out    std_logic;
-- Port for std_logic_vector field: 'bit rate' in reg: 'config from host'
    mf_config_host_bitrate_o                 : out    std_logic_vector(1 downto 0);
-- Port for BIT field: 'termination enable on the external synch input' in reg: 'config from host'
    mf_config_host_ext_sync_term_en_n_o      : out    std_logic;
-- Port for std_logic_vector field: 'station address' in reg: 'config from host'
    mf_config_host_subs_o                    : out    std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'bit rate' in reg: 'config from fmc'
    mf_config_fmc_bitrate_i                  : in     std_logic_vector(1 downto 0);
-- Port for BIT field: 'bit rate match' in reg: 'config from fmc'
    mf_config_fmc_bitrate_ok_i               : in     std_logic;
-- Port for std_logic_vector field: 'macrocycle lgth' in reg: 'macrocycle lgth'
    mf_macrocyc_lgth_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'turnaround time' in reg: 'turnaround time'
    mf_turnar_lgth_o                         : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'silence time' in reg: 'silence time'
    mf_silen_lgth_o                          : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'macrocycle time counter' in reg: 'macrocycle time cnt'
    mf_macrocyc_time_cnt_i                   : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'turnaround time counter' in reg: 'turnaround time cnt'
    mf_turnar_time_cnt_i                     : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'silence time counter' in reg: 'silence time cnt'
    mf_silen_time_cnt_i                      : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'ext_sync_tstamp' in reg: 'ext sync tstamp'
    mf_ext_sync_tstamp_i                     : in     std_logic_vector(31 downto 0);
-- Port for BIT field: 'tx rst' in reg: 'tx ctrl'
    mf_tx_rst_o                              : out    std_logic;
-- Port for BIT field: 'tx strt' in reg: 'tx ctrl'
    mf_tx_start_o                            : out    std_logic;
-- Port for std_logic_vector field: 'tx number of bytes' in reg: 'tx ctrl'
    mf_tx_bytes_num_o                        : out    std_logic_vector(8 downto 0);
-- Port for BIT field: 'tx stopped' in reg: 'tx status'
    mf_tx_stop_i                             : in     std_logic;
-- Port for BIT field: 'fd watchdog' in reg: 'fieldrive status'
    mf_fd_wdgn_i                             : in     std_logic;
-- Port for BIT field: 'fd transmitter error' in reg: 'fieldrive status'
    mf_fd_txer_i                             : in     std_logic;
-- Port for BIT field: 'rx rst' in reg: 'rx ctrl'
    mf_rx_rst_o                              : out    std_logic;
-- Port for BIT field: 'rx preamble detected' in reg: 'rx status'
    mf_rx_pream_ok_i                         : in     std_logic;
-- Port for BIT field: 'rx frame ok' in reg: 'rx status'
    mf_rx_frame_ok_i                         : in     std_logic;
-- Port for BIT field: 'rx frame error' in reg: 'rx status'
    mf_rx_frame_err_i                        : in     std_logic;
-- Port for std_logic_vector field: 'rx frame error code' in reg: 'rx status'
    mf_rx_frame_err_code_i                   : in     std_logic_vector(2 downto 0);
-- Port for std_logic_vector field: 'rx number of data bytes' in reg: 'rx status'
    mf_rx_bytes_num_i                        : in     std_logic_vector(8 downto 0);
-- Port for std_logic_vector field: 'rx ctrl byte' in reg: 'rx ctrl byte'
    mf_rx_data_ctrl_i                        : in     std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'reg 1' in reg: 'rx data reg1'
    mf_rx_data_reg1_i                        : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg2' in reg: 'rx data reg2'
    mf_rx_data_reg2_i                        : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg3' in reg: 'rx data reg3'
    mf_rx_data_reg3_i                        : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg4' in reg: 'rx data reg4'
    mf_rx_data_reg4_i                        : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg5' in reg: 'rx data reg5'
    mf_rx_data_reg5_i                        : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg6' in reg: 'rx data reg6'
    mf_rx_data_reg6_i                        : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg7' in reg: 'rx data reg7'
    mf_rx_data_reg7_i                        : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg8' in reg: 'rx data reg8'
    mf_rx_data_reg8_i                        : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg9' in reg: 'rx data reg9'
    mf_rx_data_reg9_i                        : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg10' in reg: 'rx data reg10'
    mf_rx_data_reg10_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg11' in reg: 'rx data reg11'
    mf_rx_data_reg11_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg12' in reg: 'rx data reg12'
    mf_rx_data_reg12_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg13' in reg: 'rx data reg13'
    mf_rx_data_reg13_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg14' in reg: 'rx data reg14'
    mf_rx_data_reg14_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg15' in reg: 'rx data reg15'
    mf_rx_data_reg15_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg16' in reg: 'rx data reg16'
    mf_rx_data_reg16_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg17' in reg: 'rx data reg17'
    mf_rx_data_reg17_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg18' in reg: 'rx data reg18'
    mf_rx_data_reg18_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg19' in reg: 'rx data reg19'
    mf_rx_data_reg19_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg20' in reg: 'rx data reg20'
    mf_rx_data_reg20_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg21' in reg: 'rx data reg21'
    mf_rx_data_reg21_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg22' in reg: 'rx data reg22'
    mf_rx_data_reg22_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg23' in reg: 'rx data reg23'
    mf_rx_data_reg23_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg24' in reg: 'rx data reg24'
    mf_rx_data_reg24_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg25' in reg: 'rx data reg25'
    mf_rx_data_reg25_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg26' in reg: 'rx data reg26'
    mf_rx_data_reg26_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg27' in reg: 'rx data reg27'
    mf_rx_data_reg27_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg28' in reg: 'rx data reg28'
    mf_rx_data_reg28_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg29' in reg: 'rx data reg29'
    mf_rx_data_reg29_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg30' in reg: 'rx data reg30'
    mf_rx_data_reg30_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg31' in reg: 'rx data reg31'
    mf_rx_data_reg31_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg32' in reg: 'rx data reg32'
    mf_rx_data_reg32_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'tx ctrl byte' in reg: 'tx ctrl byte'
    mf_tx_data_ctrl_o                        : out    std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'reg1' in reg: 'tx data reg1'
    mf_tx_data_reg1_o                        : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg2' in reg: 'tx data reg2'
    mf_tx_data_reg2_o                        : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg3' in reg: 'tx data reg3'
    mf_tx_data_reg3_o                        : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg4' in reg: 'tx data reg4'
    mf_tx_data_reg4_o                        : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg5' in reg: 'tx data reg5'
    mf_tx_data_reg5_o                        : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg6' in reg: 'tx data reg6'
    mf_tx_data_reg6_o                        : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg7' in reg: 'tx data reg7'
    mf_tx_data_reg7_o                        : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg8' in reg: 'tx data reg8'
    mf_tx_data_reg8_o                        : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg9' in reg: 'tx data reg9'
    mf_tx_data_reg9_o                        : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg10' in reg: 'tx data reg10'
    mf_tx_data_reg10_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg11' in reg: 'tx data reg11'
    mf_tx_data_reg11_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg12' in reg: 'tx data reg12'
    mf_tx_data_reg12_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg13' in reg: 'tx data reg13'
    mf_tx_data_reg13_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg14' in reg: 'tx data reg14'
    mf_tx_data_reg14_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg15' in reg: 'tx data reg15'
    mf_tx_data_reg15_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg16' in reg: 'tx data reg16'
    mf_tx_data_reg16_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg17' in reg: 'tx data reg17'
    mf_tx_data_reg17_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg18' in reg: 'tx data reg18'
    mf_tx_data_reg18_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg19' in reg: 'tx data reg19'
    mf_tx_data_reg19_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg20' in reg: 'tx data reg20'
    mf_tx_data_reg20_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg21' in reg: 'tx data reg21'
    mf_tx_data_reg21_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg22' in reg: 'tx data reg22'
    mf_tx_data_reg22_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg23' in reg: 'tx data reg23'
    mf_tx_data_reg23_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg24' in reg: 'tx data reg24'
    mf_tx_data_reg24_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg25' in reg: 'tx data reg25'
    mf_tx_data_reg25_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg26' in reg: 'tx data reg26'
    mf_tx_data_reg26_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg27' in reg: 'tx data reg27'
    mf_tx_data_reg27_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg28' in reg: 'tx data reg28'
    mf_tx_data_reg28_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg29' in reg: 'tx data reg29'
    mf_tx_data_reg29_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg30' in reg: 'tx data reg30'
    mf_tx_data_reg30_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg31' in reg: 'tx data reg31'
    mf_tx_data_reg31_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg32' in reg: 'tx data reg32'
    mf_tx_data_reg32_o                       : out    std_logic_vector(31 downto 0)
  );
end fmc_masterfip_csr;

architecture syn of fmc_masterfip_csr is

signal mf_rst_core_int                          : std_logic      ;
signal mf_rst_fd_int                            : std_logic      ;
signal mf_config_host_bitrate_int               : std_logic_vector(1 downto 0);
signal mf_config_host_ext_sync_term_en_n_int    : std_logic      ;
signal mf_config_host_subs_int                  : std_logic_vector(7 downto 0);
signal mf_macrocyc_lgth_int                     : std_logic_vector(31 downto 0);
signal mf_turnar_lgth_int                       : std_logic_vector(31 downto 0);
signal mf_silen_lgth_int                        : std_logic_vector(31 downto 0);
signal mf_tx_rst_int                            : std_logic      ;
signal mf_tx_start_int                          : std_logic      ;
signal mf_tx_bytes_num_int                      : std_logic_vector(8 downto 0);
signal mf_rx_rst_int                            : std_logic      ;
signal mf_tx_data_ctrl_int                      : std_logic_vector(7 downto 0);
signal mf_tx_data_reg1_int                      : std_logic_vector(31 downto 0);
signal mf_tx_data_reg2_int                      : std_logic_vector(31 downto 0);
signal mf_tx_data_reg3_int                      : std_logic_vector(31 downto 0);
signal mf_tx_data_reg4_int                      : std_logic_vector(31 downto 0);
signal mf_tx_data_reg5_int                      : std_logic_vector(31 downto 0);
signal mf_tx_data_reg6_int                      : std_logic_vector(31 downto 0);
signal mf_tx_data_reg7_int                      : std_logic_vector(31 downto 0);
signal mf_tx_data_reg8_int                      : std_logic_vector(31 downto 0);
signal mf_tx_data_reg9_int                      : std_logic_vector(31 downto 0);
signal mf_tx_data_reg10_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg11_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg12_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg13_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg14_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg15_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg16_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg17_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg18_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg19_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg20_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg21_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg22_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg23_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg24_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg25_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg26_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg27_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg28_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg29_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg30_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg31_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg32_int                     : std_logic_vector(31 downto 0);
signal ack_sreg                                 : std_logic_vector(9 downto 0);
signal rddata_reg                               : std_logic_vector(31 downto 0);
signal wrdata_reg                               : std_logic_vector(31 downto 0);
signal bwsel_reg                                : std_logic_vector(3 downto 0);
signal rwaddr_reg                               : std_logic_vector(6 downto 0);
signal ack_in_progress                          : std_logic      ;
signal wr_int                                   : std_logic      ;
signal rd_int                                   : std_logic      ;
signal allones                                  : std_logic_vector(31 downto 0);
signal allzeros                                 : std_logic_vector(31 downto 0);

begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
  wrdata_reg <= wb_dat_i;
  bwsel_reg <= wb_sel_i;
  rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
  wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
  allones <= (others => '1');
  allzeros <= (others => '0');
-- 
-- Main register bank access process.
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      ack_sreg <= "0000000000";
      ack_in_progress <= '0';
      rddata_reg <= "00000000000000000000000000000000";
      mf_rst_core_int <= '0';
      mf_rst_fd_int <= '0';
      mf_rst_lock_wr_o <= '0';
      mf_config_host_bitrate_int <= "00";
      mf_config_host_ext_sync_term_en_n_int <= '0';
      mf_config_host_subs_int <= "00000000";
      mf_macrocyc_lgth_int <= "00000000000000000000000000000000";
      mf_turnar_lgth_int <= "00000000000000000000000000000000";
      mf_silen_lgth_int <= "00000000000000000000000000000000";
      mf_tx_rst_int <= '0';
      mf_tx_start_int <= '0';
      mf_tx_bytes_num_int <= "000000000";
      mf_rx_rst_int <= '0';
      mf_tx_data_ctrl_int <= "00000000";
      mf_tx_data_reg1_int <= "00000000000000000000000000000000";
      mf_tx_data_reg2_int <= "00000000000000000000000000000000";
      mf_tx_data_reg3_int <= "00000000000000000000000000000000";
      mf_tx_data_reg4_int <= "00000000000000000000000000000000";
      mf_tx_data_reg5_int <= "00000000000000000000000000000000";
      mf_tx_data_reg6_int <= "00000000000000000000000000000000";
      mf_tx_data_reg7_int <= "00000000000000000000000000000000";
      mf_tx_data_reg8_int <= "00000000000000000000000000000000";
      mf_tx_data_reg9_int <= "00000000000000000000000000000000";
      mf_tx_data_reg10_int <= "00000000000000000000000000000000";
      mf_tx_data_reg11_int <= "00000000000000000000000000000000";
      mf_tx_data_reg12_int <= "00000000000000000000000000000000";
      mf_tx_data_reg13_int <= "00000000000000000000000000000000";
      mf_tx_data_reg14_int <= "00000000000000000000000000000000";
      mf_tx_data_reg15_int <= "00000000000000000000000000000000";
      mf_tx_data_reg16_int <= "00000000000000000000000000000000";
      mf_tx_data_reg17_int <= "00000000000000000000000000000000";
      mf_tx_data_reg18_int <= "00000000000000000000000000000000";
      mf_tx_data_reg19_int <= "00000000000000000000000000000000";
      mf_tx_data_reg20_int <= "00000000000000000000000000000000";
      mf_tx_data_reg21_int <= "00000000000000000000000000000000";
      mf_tx_data_reg22_int <= "00000000000000000000000000000000";
      mf_tx_data_reg23_int <= "00000000000000000000000000000000";
      mf_tx_data_reg24_int <= "00000000000000000000000000000000";
      mf_tx_data_reg25_int <= "00000000000000000000000000000000";
      mf_tx_data_reg26_int <= "00000000000000000000000000000000";
      mf_tx_data_reg27_int <= "00000000000000000000000000000000";
      mf_tx_data_reg28_int <= "00000000000000000000000000000000";
      mf_tx_data_reg29_int <= "00000000000000000000000000000000";
      mf_tx_data_reg30_int <= "00000000000000000000000000000000";
      mf_tx_data_reg31_int <= "00000000000000000000000000000000";
      mf_tx_data_reg32_int <= "00000000000000000000000000000000";
    elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
      ack_sreg(9) <= '0';
      if (ack_in_progress = '1') then
        if (ack_sreg(0) = '1') then
          mf_rst_lock_wr_o <= '0';
          ack_in_progress <= '0';
        else
          mf_rst_lock_wr_o <= '0';
        end if;
      else
        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
          case rwaddr_reg(6 downto 0) is
          when "0000000" => 
            if (wb_we_i = '1') then
              mf_rst_core_int <= wrdata_reg(0);
              mf_rst_fd_int <= wrdata_reg(1);
              mf_rst_lock_wr_o <= '1';
            end if;
            rddata_reg(0) <= mf_rst_core_int;
            rddata_reg(1) <= mf_rst_fd_int;
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0000001" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= "11000000000000001111111111101110";
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0000010" => 
            if (wb_we_i = '1') then
              mf_config_host_bitrate_int <= wrdata_reg(1 downto 0);
              mf_config_host_ext_sync_term_en_n_int <= wrdata_reg(2);
              mf_config_host_subs_int <= wrdata_reg(15 downto 8);
            end if;
            rddata_reg(1 downto 0) <= mf_config_host_bitrate_int;
            rddata_reg(2) <= mf_config_host_ext_sync_term_en_n_int;
            rddata_reg(15 downto 8) <= mf_config_host_subs_int;
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0000011" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(1 downto 0) <= mf_config_fmc_bitrate_i;
            rddata_reg(31) <= mf_config_fmc_bitrate_ok_i;
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0000100" => 
            if (wb_we_i = '1') then
              mf_macrocyc_lgth_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_macrocyc_lgth_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0000101" => 
            if (wb_we_i = '1') then
              mf_turnar_lgth_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_turnar_lgth_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0000110" => 
            if (wb_we_i = '1') then
              mf_silen_lgth_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_silen_lgth_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0000111" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_macrocyc_time_cnt_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0001000" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_turnar_time_cnt_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0001001" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_silen_time_cnt_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0001010" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_ext_sync_tstamp_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0001011" => 
            if (wb_we_i = '1') then
              mf_tx_rst_int <= wrdata_reg(0);
              mf_tx_start_int <= wrdata_reg(1);
              mf_tx_bytes_num_int <= wrdata_reg(16 downto 8);
            end if;
            rddata_reg(0) <= mf_tx_rst_int;
            rddata_reg(1) <= mf_tx_start_int;
            rddata_reg(16 downto 8) <= mf_tx_bytes_num_int;
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0001100" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(0) <= mf_tx_stop_i;
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0001101" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(0) <= mf_fd_wdgn_i;
            rddata_reg(1) <= mf_fd_txer_i;
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0001110" => 
            if (wb_we_i = '1') then
              mf_rx_rst_int <= wrdata_reg(0);
            end if;
            rddata_reg(0) <= mf_rx_rst_int;
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0001111" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(0) <= mf_rx_pream_ok_i;
            rddata_reg(1) <= mf_rx_frame_ok_i;
            rddata_reg(2) <= mf_rx_frame_err_i;
            rddata_reg(5 downto 3) <= mf_rx_frame_err_code_i;
            rddata_reg(16 downto 8) <= mf_rx_bytes_num_i;
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0010000" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(7 downto 0) <= mf_rx_data_ctrl_i;
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0010001" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg1_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0010010" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg2_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0010011" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg3_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0010100" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg4_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0010101" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg5_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0010110" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg6_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0010111" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg7_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0011000" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg8_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0011001" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg9_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0011010" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg10_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0011011" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg11_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0011100" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg12_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0011101" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg13_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0011110" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg14_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0011111" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg15_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0100000" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg16_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0100001" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg17_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0100010" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg18_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0100011" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg19_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0100100" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg20_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0100101" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg21_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0100110" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg22_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0100111" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg23_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0101000" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg24_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0101001" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg25_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0101010" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg26_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0101011" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg27_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0101100" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg28_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0101101" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg29_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0101110" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg30_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0101111" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg31_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0110000" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg32_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0110001" => 
            if (wb_we_i = '1') then
              mf_tx_data_ctrl_int <= wrdata_reg(7 downto 0);
            end if;
            rddata_reg(7 downto 0) <= mf_tx_data_ctrl_int;
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0110010" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg1_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg1_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0110011" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg2_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg2_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0110100" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg3_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg3_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0110101" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg4_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg4_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0110110" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg5_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg5_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0110111" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg6_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg6_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0111000" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg7_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg7_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0111001" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg8_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg8_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0111010" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg9_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg9_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0111011" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg10_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg10_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0111100" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg11_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg11_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0111101" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg12_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg12_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0111110" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg13_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg13_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0111111" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg14_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg14_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "1000000" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg15_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg15_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "1000001" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg16_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg16_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "1000010" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg17_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg17_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "1000011" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg18_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg18_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "1000100" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg19_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg19_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "1000101" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg20_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg20_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "1000110" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg21_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg21_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "1000111" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg22_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg22_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "1001000" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg23_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg23_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "1001001" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg24_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg24_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "1001010" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg25_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg25_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "1001011" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg26_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg26_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "1001100" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg27_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg27_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "1001101" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg28_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg28_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "1001110" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg29_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg29_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "1001111" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg30_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg30_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "1010000" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg31_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg31_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "1010001" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg32_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg32_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when others =>
-- prevent the slave from hanging the bus on invalid address
            ack_in_progress <= '1';
            ack_sreg(0) <= '1';
          end case;
        end if;
      end if;
    end if;
  end process;
  
  
-- Drive the data output bus
  wb_dat_o <= rddata_reg;
-- reset of the masterFIP core
  mf_rst_core_o <= mf_rst_core_int;
-- reset of the fieldrive chip (FD_RSTN)
  mf_rst_fd_o <= mf_rst_fd_int;
-- reset magic value
-- pass-through field: reset magic value in register: rst
  mf_rst_lock_o <= wrdata_reg(31 downto 16);
-- bit rate
  mf_config_host_bitrate_o <= mf_config_host_bitrate_int;
-- termination enable on the external synch input
  mf_config_host_ext_sync_term_en_n_o <= mf_config_host_ext_sync_term_en_n_int;
-- station address
  mf_config_host_subs_o <= mf_config_host_subs_int;
-- bit rate
-- bit rate match
-- macrocycle lgth
  mf_macrocyc_lgth_o <= mf_macrocyc_lgth_int;
-- turnaround time
  mf_turnar_lgth_o <= mf_turnar_lgth_int;
-- silence time
  mf_silen_lgth_o <= mf_silen_lgth_int;
-- macrocycle time counter
-- turnaround time counter
-- silence time counter
-- ext_sync_tstamp
-- tx rst
  mf_tx_rst_o <= mf_tx_rst_int;
-- tx strt
  mf_tx_start_o <= mf_tx_start_int;
-- tx number of bytes
  mf_tx_bytes_num_o <= mf_tx_bytes_num_int;
-- tx stopped
-- fd watchdog
-- fd transmitter error
-- rx rst
  mf_rx_rst_o <= mf_rx_rst_int;
-- rx preamble detected
-- rx frame ok
-- rx frame error
-- rx frame error code
-- rx number of data bytes
-- rx ctrl byte
-- reg 1
-- reg2
-- reg3
-- reg4
-- reg5
-- reg6
-- reg7
-- reg8
-- reg9
-- reg10
-- reg11
-- reg12
-- reg13
-- reg14
-- reg15
-- reg16
-- reg17
-- reg18
-- reg19
-- reg20
-- reg21
-- reg22
-- reg23
-- reg24
-- reg25
-- reg26
-- reg27
-- reg28
-- reg29
-- reg30
-- reg31
-- reg32
-- tx ctrl byte
  mf_tx_data_ctrl_o <= mf_tx_data_ctrl_int;
-- reg1
  mf_tx_data_reg1_o <= mf_tx_data_reg1_int;
-- reg2
  mf_tx_data_reg2_o <= mf_tx_data_reg2_int;
-- reg3
  mf_tx_data_reg3_o <= mf_tx_data_reg3_int;
-- reg4
  mf_tx_data_reg4_o <= mf_tx_data_reg4_int;
-- reg5
  mf_tx_data_reg5_o <= mf_tx_data_reg5_int;
-- reg6
  mf_tx_data_reg6_o <= mf_tx_data_reg6_int;
-- reg7
  mf_tx_data_reg7_o <= mf_tx_data_reg7_int;
-- reg8
  mf_tx_data_reg8_o <= mf_tx_data_reg8_int;
-- reg9
  mf_tx_data_reg9_o <= mf_tx_data_reg9_int;
-- reg10
  mf_tx_data_reg10_o <= mf_tx_data_reg10_int;
-- reg11
  mf_tx_data_reg11_o <= mf_tx_data_reg11_int;
-- reg12
  mf_tx_data_reg12_o <= mf_tx_data_reg12_int;
-- reg13
  mf_tx_data_reg13_o <= mf_tx_data_reg13_int;
-- reg14
  mf_tx_data_reg14_o <= mf_tx_data_reg14_int;
-- reg15
  mf_tx_data_reg15_o <= mf_tx_data_reg15_int;
-- reg16
  mf_tx_data_reg16_o <= mf_tx_data_reg16_int;
-- reg17
  mf_tx_data_reg17_o <= mf_tx_data_reg17_int;
-- reg18
  mf_tx_data_reg18_o <= mf_tx_data_reg18_int;
-- reg19
  mf_tx_data_reg19_o <= mf_tx_data_reg19_int;
-- reg20
  mf_tx_data_reg20_o <= mf_tx_data_reg20_int;
-- reg21
  mf_tx_data_reg21_o <= mf_tx_data_reg21_int;
-- reg22
  mf_tx_data_reg22_o <= mf_tx_data_reg22_int;
-- reg23
  mf_tx_data_reg23_o <= mf_tx_data_reg23_int;
-- reg24
  mf_tx_data_reg24_o <= mf_tx_data_reg24_int;
-- reg25
  mf_tx_data_reg25_o <= mf_tx_data_reg25_int;
-- reg26
  mf_tx_data_reg26_o <= mf_tx_data_reg26_int;
-- reg27
  mf_tx_data_reg27_o <= mf_tx_data_reg27_int;
-- reg28
  mf_tx_data_reg28_o <= mf_tx_data_reg28_int;
-- reg29
  mf_tx_data_reg29_o <= mf_tx_data_reg29_int;
-- reg30
  mf_tx_data_reg30_o <= mf_tx_data_reg30_int;
-- reg31
  mf_tx_data_reg31_o <= mf_tx_data_reg31_int;
-- reg32
  mf_tx_data_reg32_o <= mf_tx_data_reg32_int;
  rwaddr_reg <= wb_adr_i;
  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
  wb_ack_o <= ack_sreg(0);
end syn;
