--_________________________________________________________________________________________________
--                                                                                                |
--                                           |TDC core|                                           |
--                                                                                                |
--                                         CERN,BE/CO-HT                                          |
--________________________________________________________________________________________________|

---------------------------------------------------------------------------------------------------
--                                                                                                |
--                                    fmc_masterFIP_mezzanine                                     |
--                                                                                                |
---------------------------------------------------------------------------------------------------
-- File         fmc_masterFIP_mezzanine.vhd                                                       |
--                                                                                                |
-- Description  The unit combines                                                                 |
--                o the masterFIP core                                                            |
--                o the I2C core for the communication with the TDC board EEPROM                  |
--                o the OneWire core for the communication with the TDC board UniqueID&Thermeter  |
--                o the Embedded Interrupt Controller core that concentrates several interrupt    |
--                  sources into one WISHBONE interrupt request line.                             |
--                                                                                                |
--              For the interconnection between the GN4124/VME core and the different cores (TDC, |
--              I2C, 1W, EIC, timestamps memory) the unit instantiates an SDB crossbar.           |
--                                                                                                |
--              Note that the TDC core uses word addressing, whereas the GN4124/VME cores use byte|
--              addressing                                                                        |
--                                   _______________________________                              |
--                                 |       FMC TDC mezzanine        |                             |
--                                 |                                |                             |
--                                 | |   ________________    ___    |                             |
--                                 | |->|                |  |   |   |                             |
--                 ACAM chip <-->  |    | masterFIP core |  |   |   |   <-->                      |
--                                 | |--|________________|  | S |   |                             |
--                                 | |   ________________   |   |   |                             |
--                                 | |  |                |  |   |   |                             |
--               EEPROM chip <-->  | |  |    I2C core    |  |   |   |   <-->                      |
--                                 | |  |________________|  |   |   |                             |
--                                 | |   ________________   | D |   |          GN4124/VME core    |
--                                 | |  |                |  |   |   |                             |
--                   1W chip <-->  | |  |     1W core    |  |   |   |   <-->                      |
--                                 | |  |________________|  |   |   |                             |
--                                 | |   ________________   |   |   |                             |
--                                 | |  |                |  | B |   |                             |
--                                 | |->|       EIC      |  |   |   |   <-->                      |
--                                 |    |________________|  |___|   |                             |
--                                 |                                |                             |
--                                 |________________________________|                             |
--                                     ^                       ^                                  |
--                                     | 40 MHz            rst |                                  |
--                                                                                                |
--                         Figure 1: FMC masterFIP mezzanine architecture and                     |
--                          connection with the clks_rsts_manager unit                            |
--                                                                                                |
--                                                                                                |
--                                                                                                |
-- Authors      Evangelia Gousiou (Evangelia.Gousiou@cern.ch)                                     |
-- Date         07/2014                                                                           |
-- Version      v2                                                                                |
-- Depends on                                                                                     |
--                                                                                                |
----------------                                                                                  |
-- Last changes                                                                                   |
--     07/2014  v1  EG  First version                                                             |
--                                                                                                |
---------------------------------------------------------------------------------------------------

---------------------------------------------------------------------------------------------------
--                               GNU LESSER GENERAL PUBLIC LICENSE                                |
--                              ------------------------------------                              |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either     |
-- version 2.1 of the License, or (at your option) any later version.                             |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;       |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.      |
-- See the GNU Lesser General Public License for more details.                                    |
-- You should have received a copy of the GNU Lesser General Public License along with this       |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html                     |
---------------------------------------------------------------------------------------------------

--=================================================================================================
--                                       Libraries & Packages
--=================================================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.masterFIP_pkg.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;


--=================================================================================================
--                           Entity declaration for fmc_masterFIP_mezzanine
--=================================================================================================
entity fmc_masterFIP_mezzanine is
  generic
    (g_with_wrabbit_core : boolean := FALSE;
     g_span              : integer := 32;
     g_width             : integer := 32;
     values_for_simul    : boolean := FALSE);
  port
    -- TDC core
    (-- Clock & reset 40MHz
     clk_sys_i           : in    std_logic; -- 40 MHz clock
     rst_sys_n_i         : in    std_logic; -- reset for 40 MHz logic
     -- FielDrive
     fd_rxcdn_i          : in    std_logic;
     fd_rxd_i            : in    std_logic;
     fd_txer_i           : in    std_logic;
     fd_wdgn_i           : in    std_logic;
     fd_rstn_o           : out   std_logic;
     fd_txck_o           : out   std_logic;
     fd_txd_o            : out   std_logic;
     fd_txena_o          : out   std_logic;
     -- WISHBONE interface with the GN4124/VME_core
     -- for the core configuration | data retrieval | core interrupts | 1Wire | I2C 
     wb_adr_i           : in    std_logic_vector(31 downto 0);
     wb_dat_i           : in    std_logic_vector(31 downto 0);
     wb_cyc_i           : in    std_logic;
     wb_sel_i           : in    std_logic_vector(3 downto 0);
     wb_stb_i           : in    std_logic;
     wb_we_i            : in    std_logic;
     wb_dat_o           : out   std_logic_vector(31 downto 0);
     wb_ack_o           : out   std_logic;
     wb_stall_o         : out   std_logic;
     wb_irq_o           : out   std_logic;
    -- I2C EEPROM interface
     i2c_scl_o          : out   std_logic;
     i2c_scl_oen_o      : out   std_logic;
     i2c_scl_i          : in    std_logic;
     i2c_sda_oen_o      : out   std_logic;
     i2c_sda_o          : out   std_logic;
     i2c_sda_i          : in    std_logic;
    -- 1-Wire interface
     onewire_b          : inout std_logic;
     -- Aux
     aux_o              : out   std_logic_vector(7 downto 0));
end fmc_masterFIP_mezzanine;


--=================================================================================================
--                                    architecture declaration
--=================================================================================================
architecture rtl of fmc_masterFIP_mezzanine is

---------------------------------------------------------------------------------------------------
--                                         SDB CONSTANTS                                         --
---------------------------------------------------------------------------------------------------
  -- Note: All address in sdb and crossbar are BYTE addresses!

  -- Master ports on the wishbone crossbar
  constant c_NUM_WB_MASTERS       : integer := 2;
  constant c_WB_SLAVE_CSR         : integer := 0;  -- core configuration and data registers
  constant c_WB_SLAVE_EIC         : integer := 1;  -- interrupts

  -- Slave port on the wishbone crossbar
  constant c_NUM_WB_SLAVES            : integer := 1;

  -- Wishbone master(s)
  constant c_WB_MASTER                : integer := 0;

  -- sdb header address
  constant c_SDB_ADDRESS              : t_wishbone_address := x"00000000";

  -- WISHBONE crossbar layout
  constant c_INTERCONNECT_LAYOUT      : t_sdb_record_array(1 downto 0) :=
    (0 => f_sdb_embed_device(c_MASTERFIP_CSR_SDB_DEVICE, x"00010000"),
     1 => f_sdb_embed_device(c_MASTERFIP_EIC_SDB_DEVICE, x"00011000"));


---------------------------------------------------------------------------------------------------
--                                            Signals                                            --
---------------------------------------------------------------------------------------------------
  -- resets
  signal general_rst_n, rst_ref_0_n: std_logic;
  -- Wishbone buse(s) from crossbar master port(s)
  signal cnx_master_out            : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
  signal cnx_master_in             : t_wishbone_master_in_array (c_NUM_WB_MASTERS-1 downto 0);
  -- Wishbone buse(s) to crossbar slave port(s)
  signal cnx_slave_out             : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
  signal cnx_slave_in              : t_wishbone_slave_in_array (c_NUM_WB_SLAVES-1 downto 0);
  -- Wishbone bus from additional registers
  signal xreg_slave_out            : t_wishbone_slave_out;
  signal xreg_slave_in             : t_wishbone_slave_in;
  -- WISHBONE addresses
  signal wb_adr                    : std_logic_vector(31 downto 0);
  signal tdc_mem_wb_adr            : std_logic_vector(31 downto 0);
  -- 1-wire
  signal mezz_owr_en, mezz_owr_i   : std_logic_vector(0 downto 0);
  -- I2C
  signal sys_scl_in, sys_scl_out   : std_logic;
  signal sys_scl_oe_n, sys_sda_in  : std_logic;
  signal sys_sda_out, sys_sda_oe_n : std_logic;
  -- IRQ
  signal irq_p                     : std_logic_vector(7 downto 0);


--=================================================================================================
--                                       architecture begin
--=================================================================================================
begin


---------------------------------------------------------------------------------------------------
--                                     CSR WISHBONE CROSSBAR                                     --
---------------------------------------------------------------------------------------------------
-- CSR wishbone address decoder
--   0x10000 -> mezzanine board 1-Wire -not used
--   0x11000 -> masterFIP core configuration and data
--   0x12000 -> EIC
--   0x13000 -> mezzanine board EEPROM I2C -not used

 --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
  cmp_sdb_crossbar : xwb_sdb_crossbar
  generic map
    (g_num_masters  => c_NUM_WB_SLAVES,
     g_num_slaves   => c_NUM_WB_MASTERS,
     g_registered   => true,
     g_wraparound   => true,
     g_layout       => c_INTERCONNECT_LAYOUT,
     g_sdb_addr     => c_SDB_ADDRESS)
  port map
    (clk_sys_i      => clk_sys_i,
     rst_n_i        => rst_sys_n_i,
     slave_i        => cnx_slave_in,
     slave_o        => cnx_slave_out,
     master_i       => cnx_master_in,
     master_o       => cnx_master_out);

  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
  -- Unused wishbone signals
  wb_dat_o   <= cnx_slave_out(c_WB_MASTER).dat;
  wb_ack_o   <= cnx_slave_out(c_WB_MASTER).ack;
  wb_stall_o <= cnx_slave_out(c_WB_MASTER).stall;
  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
  -- Connect crossbar slave port to entity port
  cnx_slave_in(c_WB_MASTER).adr <= wb_adr_i;
  cnx_slave_in(c_WB_MASTER).dat <= wb_dat_i;
  cnx_slave_in(c_WB_MASTER).sel <= wb_sel_i;
  cnx_slave_in(c_WB_MASTER).stb <= wb_stb_i;
  cnx_slave_in(c_WB_MASTER).we  <= wb_we_i;
  cnx_slave_in(c_WB_MASTER).cyc <= wb_cyc_i;
  
---------------------------------------------------------------------------------------------------
--                                         masterFIP CORE                                        --
---------------------------------------------------------------------------------------------------
  cmp_masterfip_core: fmc_masterFIP_core
  generic map
    (g_span           => g_span,
     g_width          => g_width,
     values_for_simul => FALSE)
  port map
    (-- clks, rst
     clk_i            => clk_sys_i,
     rst_i            => not (rst_sys_n_i),
     -- FielDrive
     fd_rxcdn_i       => fd_rxcdn_i,
     fd_rxd_i         => fd_rxd_i,
     fd_txer_i        => fd_txer_i,
     fd_wdgn_i        => fd_wdgn_i,
     fd_rstn_o        => fd_rstn_o,
     fd_txck_o        => fd_txck_o,
     fd_txd_o         => fd_txd_o,
     fd_txena_o       => fd_txena_o,
     -- Interrupts
     irq_p_o          => irq_p,
     -- WISHBONE CSR for core configuration
     wb_adr_i         => wb_adr,
     wb_dat_i         => cnx_master_out(c_WB_SLAVE_CSR).dat,
     wb_stb_i         => cnx_master_out(c_WB_SLAVE_CSR).stb,
     wb_sel_i         => cnx_master_out(c_WB_SLAVE_CSR).sel,
     wb_we_i          => cnx_master_out(c_WB_SLAVE_CSR).we,
     wb_cyc_i         => cnx_master_out(c_WB_SLAVE_CSR).cyc,
     wb_stall_o       => cnx_master_in(c_WB_SLAVE_CSR).stall,
     wb_dat_o         => cnx_master_in(c_WB_SLAVE_CSR).dat,
     wb_ack_o         => cnx_master_in(c_WB_SLAVE_CSR).ack,
     -- Aux
     aux_o            => aux_o);

  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
  -- Convert byte address into word address
  wb_adr <= "00" & cnx_master_out(c_WB_SLAVE_CSR).adr(31 downto 2);

  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
  -- Unused wishbone signals
  cnx_master_in(c_WB_SLAVE_CSR).err   <= '0';
  cnx_master_in(c_WB_SLAVE_CSR).rty   <= '0';
  cnx_master_in(c_WB_SLAVE_CSR).int   <= '0';


---------------------------------------------------------------------------------------------------
--                             WBGEN2 EMBEDDED INTERRUPTS CONTROLLER                             --
---------------------------------------------------------------------------------------------------

  cmp_masterfip_eic : fmc_masterfip_eic
  port map
    (clk_sys_i                => clk_sys_i,
     rst_n_i                  => rst_sys_n_i,
     wb_adr_i                 => cnx_master_out(c_WB_SLAVE_EIC).adr(3 downto 2),
     wb_dat_i                 => cnx_master_out(c_WB_SLAVE_EIC).dat,
     wb_dat_o                 => cnx_master_in(c_WB_SLAVE_EIC).dat,
     wb_cyc_i                 => cnx_master_out(c_WB_SLAVE_EIC).cyc,
     wb_sel_i                 => cnx_master_out(c_WB_SLAVE_EIC).sel,
     wb_stb_i                 => cnx_master_out(c_WB_SLAVE_EIC).stb,
     wb_we_i                  => cnx_master_out(c_WB_SLAVE_EIC).we,
     wb_ack_o                 => cnx_master_in(c_WB_SLAVE_EIC).ack,
     wb_stall_o               => cnx_master_in(c_WB_SLAVE_EIC).stall,
     wb_int_o                 => wb_irq_o,
     irq_macrocy_start_i      => irq_p(0),
     irq_silen_time_expire_i  => irq_p(1),
     irq_turnar_time_expire_i => irq_p(2),
     irq_tx_completed_i       => irq_p(3),
     irq_rx_fss_ok_i          => irq_p(4),
     irq_rx_frame_ok_i        => irq_p(5),
     irq_rx_crc_wrong_i       => irq_p(6));
  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
  -- Unused wishbone signals
  cnx_master_in(c_WB_SLAVE_EIC).err <= '0';
  cnx_master_in(c_WB_SLAVE_EIC).rty <= '0';
  cnx_master_in(c_WB_SLAVE_EIC).int <= '0';



 
end rtl;
----------------------------------------------------------------------------------------------------
--  architecture ends
----------------------------------------------------------------------------------------------------