Comments for masterFIP GW review
1 Project/Synthesis/PAR
- [+] 3943 warnings during synthesis
- [+] ucf: "TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_feedback" points to non-existing node 'U_Node_Template/U_GN4124_Core/cmp_clk_in/feedback'.
[-]120+ warnings about missing/duplicates files when we first open the .xise project file, and the messages keep reappearing while we use the tool[-]Project hierarchy shows too many unused files (not under spec_masterfip_mt entity)[-]running hdlmake in syn/spec does not work[-]many (~50) synthesis-generated files not git-ignored[-]if not a build script for wbgen, at least a README with how you expect the wbgen2 command to be invoked should be provided
2 Simulation
- [!] Error: (vcom-19) Failed to access library 'nanofip_lib' at "nanofip_lib" (Modelsim SE-64 10.2a, Linux) This is due to case-sensitivity in Linux. Solution: replace "vlib nanoFIP_lib" with "vlib nanofip_lib" or, alternatively, replace "vcom -work nanofip_lib" with "vcom -work nanoFIP_lib"
- [!] Error: (vcom-7) Failed to open design unit file "../../sim/spec/testbench/nanofip_lib/*" in read mode. Again, this is due to case-sensitivity in Linux, since the folder commited in git is actually sim/spec/testbench/nanoFIP_lib
- [+] Trying to step into the code with Modelsim produces: Error opening /opt/Xilinx/14.7/ISE_DS/ISE/vhdl/src/unisims/primitive/PLL_ADV.vhd. This path does not exist in my system.
- [+] Fix warnings "numeric_std.to_integer metavalue detected, returning 0" (alternatively, use "set NumericStdNoWarnings 1" after the call to vsim in your do files, suboptimal solution because it might also hide useful metavalue warnings)
[-]After clearing the metavalue warnings, have a look also at the remaining warnings[-]Some signals are always 'X', if they are not useful in simulation, just remove them[-]group signal waveforms[-]split compilation (vcom) from running in separate "do" files, invoke them both from a top do file (eg. compile.do + run.do => sim.do)[-]many (~100) simulation-generated files not git-ignored- [?] Do you need the "vlog $env(XILINX)/verilog/src/glbl.v"? If not, remove it, otherwise users might get the error "can't read "env(XILINX)": no such variable" if they haven't set this environment variable.
3 Design
- [?] rtl: is leds_manager.vhd used at all? what about carrier_info.vhd, free_counter.vhd, and perhaps others? If not, it's better to delete them from the repository.
- [?] rtl: why is wf_package.vhd declared here AND in ip-cores/nanofip?
- [?] top: is synthesis_descriptor.vhd used?
- [*] the whole nanofip as ip-core of masterfip seems a bit counter-intuitive. If there are things used by both, the should belong to a "fip" project, and both nano- and master- should use them.
3.1 masterFIP_pkg
[-]constants should have lower case "c" (I think)
3.2 spec_masterfip_mt
3.2.1 fmc_masterFIP_core
[-]it would be nice to have a bit more hierachy in this module, with less low-level processes and modules lying around (eg. counter modules, assignments to wb registers) , to highlight the high-level structure of the core.- [?] why do you use two decreasing counter modules (wf_decr_counter and decr_counter)?
- [?] why is speed_X_i not a 2-bit vector?
- [?] would it be interesting for diagnostics to monitor if/when counters overflow?
- [?] why is reg_to_mt.fd_wdg_tstamp_i one bit larger than macrocyc_cnt?
- [*] cmp_ext_sync_deglitch_p_detect and cmp_fd_wdgn_deglitch_p_detect introduce one unnecessary FF/latency cycle
- [*] we should introduce generic up/down counters to general-cores
- masterfip_tx
[-]synch_signals process could be replaced by 2x gc_sync_ffs- [?] more importantly, why do you resync these two signals?
- masterfip_rx
- [?] can't you use general-cores for cmp_rx_deglitcher? (perhaps think about it also in nanofip project)
- [?] did you make up your mind about what to connect to nfip_rst_i port of cmp_rx_deglitcher? if yes, remove the inline comment
4 Legend
- [!] = fatal
- [+] = important
[-]= minor- [?] = question
- [*] = note