fmc_masterfip_csr

FMC masterFIP core registers

Wishbone slave for FMC masterFIP core

1. Memory map summary
2. HDL symbol
3. Register description
3.1. rst
3.2. id
3.3. dbg
3.4. mezzanine temperature
3.5. mezzanine unique id lsb
3.6. mezzanine unique id msb
3.7. adc
3.8. dac
3.9. ext sync
3.10. ext sync pulses cnt
3.11. bus speed
3.12. macrocycle lgth
3.13. turnaround lgth
3.14. silence lgth
3.15. macrocycle time cnt
3.16. macrocycles number cnt
3.17. turnaround time cnt
3.18. silence time cnt
3.19. tx ctrl
3.20. tx status
3.21. fieldrive wdgn, cdn
3.22. fieldrive wdg timestamp
3.23. fieldrive txer cnt
3.24. fieldrive txer tstamp
3.25. rx ctrl
3.26. rx status
3.27. rx current word index
3.28. rx number of frames with CRC error
3.29. rx payload ctrl byte
3.30. rx payload reg1
3.31. rx payload reg2
3.32. rx payload reg3
3.33. rx payload reg4
3.34. rx payload reg5
3.35. rx payload reg6
3.36. rx payload reg7
3.37. rx payload reg8
3.38. rx payload reg9
3.39. rx payload reg10
3.40. rx payload reg11
3.41. rx payload reg12
3.42. rx payload reg13
3.43. rx payload reg14
3.44. rx payload reg15
3.45. rx payload reg16
3.46. rx payload reg17
3.47. rx payload reg18
3.48. rx payload reg19
3.49. rx payload reg20
3.50. rx payload reg21
3.51. rx payload reg22
3.52. rx payload reg23
3.53. rx payload reg24
3.54. rx payload reg25
3.55. rx payload reg26
3.56. rx payload reg27
3.57. rx payload reg28
3.58. rx payload reg29
3.59. rx payload reg30
3.60. rx payload reg31
3.61. rx payload reg32
3.62. rx payload reg33
3.63. rx payload reg34
3.64. rx payload reg35
3.65. rx payload reg36
3.66. rx payload reg37
3.67. rx payload reg38
3.68. rx payload reg39
3.69. rx payload reg40
3.70. rx payload reg41
3.71. rx payload reg42
3.72. rx payload reg43
3.73. rx payload reg44
3.74. rx payload reg45
3.75. rx payload reg46
3.76. rx payload reg47
3.77. rx payload reg48
3.78. rx payload reg49
3.79. rx payload reg50
3.80. rx payload reg51
3.81. rx payload reg52
3.82. rx payload reg53
3.83. rx payload reg54
3.84. rx payload reg55
3.85. rx payload reg56
3.86. rx payload reg57
3.87. rx payload reg58
3.88. rx payload reg59
3.89. rx payload reg60
3.90. rx payload reg61
3.91. rx payload reg62
3.92. rx payload reg63
3.93. rx payload reg64
3.94. rx payload reg65
3.95. rx payload reg66
3.96. rx payload reg67
3.97. tx ctrl byte
3.98. tx payload reg1
3.99. tx payload reg2
3.100. tx payload reg3
3.101. tx payload reg4
3.102. tx payload reg5
3.103. tx payload reg6
3.104. tx payload reg7
3.105. tx payload reg8
3.106. tx payload reg9
3.107. tx payload reg10
3.108. tx payload reg11
3.109. tx payload reg12
3.110. tx payload reg13
3.111. tx payload reg14
3.112. tx payload reg15
3.113. tx payload reg16
3.114. tx payload reg17
3.115. tx payload reg18
3.116. tx payload reg19
3.117. tx payload reg20
3.118. tx payload reg21
3.119. tx payload reg22
3.120. tx payload reg23
3.121. tx payload reg24
3.122. tx payload reg25
3.123. tx payload reg26
3.124. tx payload reg27
3.125. tx payload reg28
3.126. tx payload reg29
3.127. tx payload reg30
3.128. tx payload reg31
3.129. tx payload reg32
3.130. tx payload reg33
3.131. tx payload reg34
3.132. tx payload reg35
3.133. tx payload reg36
3.134. tx payload reg37
3.135. tx payload reg38
3.136. tx payload reg39
3.137. tx payload reg40
3.138. tx payload reg41
3.139. tx payload reg42
3.140. tx payload reg43
3.141. tx payload reg44
3.142. tx payload reg45
3.143. tx payload reg46
3.144. tx payload reg47
3.145. tx payload reg48
3.146. tx payload reg49
3.147. tx payload reg50
3.148. tx payload reg51
3.149. tx payload reg52
3.150. tx payload reg53
3.151. tx payload reg54
3.152. tx payload reg55
3.153. tx payload reg56
3.154. tx payload reg57
3.155. tx payload reg58
3.156. tx payload reg59
3.157. tx payload reg60
3.158. tx payload reg61
3.159. tx payload reg62
3.160. tx payload reg63
3.161. tx payload reg64
3.162. tx payload reg65
3.163. tx payload reg66
3.164. tx payload reg67

1. Memory map summary

H/W Address	Type	Name	VHDL/Verilog prefix	C prefix
0x0	REG	rst	mrfip_rst	RST
0x1	REG	id	mrfip_id	ID
0x2	REG	dbg	mrfip_dbg	DBG
0x3	REG	mezzanine temperature	mrfip_ds1820_temper	DS1820_TEMPER
0x4	REG	mezzanine unique id lsb	mrfip_ds1820_id_lsb	DS1820_ID_LSB
0x5	REG	mezzanine unique id msb	mrfip_ds1820_id_msb	DS1820_ID_MSB
0x6	REG	adc	mrfip_adc	ADC
0x7	REG	dac	mrfip_dac_config	DAC_CONFIG
0x8	REG	ext sync	mrfip_ext_sync	EXT_SYNC
0x9	REG	ext sync pulses cnt	mrfip_ext_sync_p_cnt	EXT_SYNC_P_CNT
0xa	REG	bus speed	mrfip_speed	SPEED
0xb	REG	macrocycle lgth	mrfip_macrocyc	MACROCYC
0xc	REG	turnaround lgth	mrfip_turnar	TURNAR
0xd	REG	silence lgth	mrfip_silen	SILEN
0xe	REG	macrocycle time cnt	mrfip_macrocyc_time_cnt	MACROCYC_TIME_CNT
0xf	REG	macrocycles number cnt	mrfip_macrocyc_num_cnt	MACROCYC_NUM_CNT
0x10	REG	turnaround time cnt	mrfip_turnar_time_cnt	TURNAR_TIME_CNT
0x11	REG	silence time cnt	mrfip_silen_time_cnt	SILEN_TIME_CNT
0x12	REG	tx ctrl	mrfip_tx_ctrl	TX_CTRL
0x13	REG	tx status	mrfip_tx_stat	TX_STAT
0x14	REG	fieldrive wdgn, cdn	mrfip_fd	FD
0x15	REG	fieldrive wdg timestamp	mrfip_fd_wdg_tstamp	FD_WDG_TSTAMP
0x16	REG	fieldrive txer cnt	mrfip_fd_txer_cnt	FD_TXER_CNT
0x17	REG	fieldrive txer tstamp	mrfip_fd_txer_tstamp	FD_TXER_TSTAMP
0x18	REG	rx ctrl	mrfip_rx_ctrl	RX_CTRL
0x19	REG	rx status	mrfip_rx_stat	RX_STAT
0x1a	REG	rx current word index	mrfip_rx_stat_curr_word_indx	RX_STAT_CURR_WORD_INDX
0x1b	REG	rx number of frames with CRC error	mrfip_rx_stat_crc_err_cnt	RX_STAT_CRC_ERR_CNT
0x1c	REG	rx payload ctrl byte	mrfip_rx_payld_ctrl	RX_PAYLD_CTRL
0x1d	REG	rx payload reg1	mrfip_rx_payld_reg1	RX_PAYLD_REG1
0x1e	REG	rx payload reg2	mrfip_rx_payld_reg2	RX_PAYLD_REG2
0x1f	REG	rx payload reg3	mrfip_rx_payld_reg3	RX_PAYLD_REG3
0x20	REG	rx payload reg4	mrfip_rx_payld_reg4	RX_PAYLD_REG4
0x21	REG	rx payload reg5	mrfip_rx_payld_reg5	RX_PAYLD_REG5
0x22	REG	rx payload reg6	mrfip_rx_payld_reg6	RX_PAYLD_REG6
0x23	REG	rx payload reg7	mrfip_rx_payld_reg7	RX_PAYLD_REG7
0x24	REG	rx payload reg8	mrfip_rx_payld_reg8	RX_PAYLD_REG8
0x25	REG	rx payload reg9	mrfip_rx_payld_reg9	RX_PAYLD_REG9
0x26	REG	rx payload reg10	mrfip_rx_payld_reg10	RX_PAYLD_REG10
0x27	REG	rx payload reg11	mrfip_rx_payld_reg11	RX_PAYLD_REG11
0x28	REG	rx payload reg12	mrfip_rx_payld_reg12	RX_PAYLD_REG12
0x29	REG	rx payload reg13	mrfip_rx_payld_reg13	RX_PAYLD_REG13
0x2a	REG	rx payload reg14	mrfip_rx_payld_reg14	RX_PAYLD_REG14
0x2b	REG	rx payload reg15	mrfip_rx_payld_reg15	RX_PAYLD_REG15
0x2c	REG	rx payload reg16	mrfip_rx_payld_reg16	RX_PAYLD_REG16
0x2d	REG	rx payload reg17	mrfip_rx_payld_reg17	RX_PAYLD_REG17
0x2e	REG	rx payload reg18	mrfip_rx_payld_reg18	RX_PAYLD_REG18
0x2f	REG	rx payload reg19	mrfip_rx_payld_reg19	RX_PAYLD_REG19
0x30	REG	rx payload reg20	mrfip_rx_payld_reg20	RX_PAYLD_REG20
0x31	REG	rx payload reg21	mrfip_rx_payld_reg21	RX_PAYLD_REG21
0x32	REG	rx payload reg22	mrfip_rx_payld_reg22	RX_PAYLD_REG22
0x33	REG	rx payload reg23	mrfip_rx_payld_reg23	RX_PAYLD_REG23
0x34	REG	rx payload reg24	mrfip_rx_payld_reg24	RX_PAYLD_REG24
0x35	REG	rx payload reg25	mrfip_rx_payld_reg25	RX_PAYLD_REG25
0x36	REG	rx payload reg26	mrfip_rx_payld_reg26	RX_PAYLD_REG26
0x37	REG	rx payload reg27	mrfip_rx_payld_reg27	RX_PAYLD_REG27
0x38	REG	rx payload reg28	mrfip_rx_payld_reg28	RX_PAYLD_REG28
0x39	REG	rx payload reg29	mrfip_rx_payld_reg29	RX_PAYLD_REG29
0x3a	REG	rx payload reg30	mrfip_rx_payld_reg30	RX_PAYLD_REG30
0x3b	REG	rx payload reg31	mrfip_rx_payld_reg31	RX_PAYLD_REG31
0x3c	REG	rx payload reg32	mrfip_rx_payld_reg32	RX_PAYLD_REG32
0x3d	REG	rx payload reg33	mrfip_rx_payld_reg33	RX_PAYLD_REG33
0x3e	REG	rx payload reg34	mrfip_rx_payld_reg34	RX_PAYLD_REG34
0x3f	REG	rx payload reg35	mrfip_rx_payld_reg35	RX_PAYLD_REG35
0x40	REG	rx payload reg36	mrfip_rx_payld_reg36	RX_PAYLD_REG36
0x41	REG	rx payload reg37	mrfip_rx_payld_reg37	RX_PAYLD_REG37
0x42	REG	rx payload reg38	mrfip_rx_payld_reg38	RX_PAYLD_REG38
0x43	REG	rx payload reg39	mrfip_rx_payld_reg39	RX_PAYLD_REG39
0x44	REG	rx payload reg40	mrfip_rx_payld_reg40	RX_PAYLD_REG40
0x45	REG	rx payload reg41	mrfip_rx_payld_reg41	RX_PAYLD_REG41
0x46	REG	rx payload reg42	mrfip_rx_payld_reg42	RX_PAYLD_REG42
0x47	REG	rx payload reg43	mrfip_rx_payld_reg43	RX_PAYLD_REG43
0x48	REG	rx payload reg44	mrfip_rx_payld_reg44	RX_PAYLD_REG44
0x49	REG	rx payload reg45	mrfip_rx_payld_reg45	RX_PAYLD_REG45
0x4a	REG	rx payload reg46	mrfip_rx_payld_reg46	RX_PAYLD_REG46
0x4b	REG	rx payload reg47	mrfip_rx_payld_reg47	RX_PAYLD_REG47
0x4c	REG	rx payload reg48	mrfip_rx_payld_reg48	RX_PAYLD_REG48
0x4d	REG	rx payload reg49	mrfip_rx_payld_reg49	RX_PAYLD_REG49
0x4e	REG	rx payload reg50	mrfip_rx_payld_reg50	RX_PAYLD_REG50
0x4f	REG	rx payload reg51	mrfip_rx_payld_reg51	RX_PAYLD_REG51
0x50	REG	rx payload reg52	mrfip_rx_payld_reg52	RX_PAYLD_REG52
0x51	REG	rx payload reg53	mrfip_rx_payld_reg53	RX_PAYLD_REG53
0x52	REG	rx payload reg54	mrfip_rx_payld_reg54	RX_PAYLD_REG54
0x53	REG	rx payload reg55	mrfip_rx_payld_reg55	RX_PAYLD_REG55
0x54	REG	rx payload reg56	mrfip_rx_payld_reg56	RX_PAYLD_REG56
0x55	REG	rx payload reg57	mrfip_rx_payld_reg57	RX_PAYLD_REG57
0x56	REG	rx payload reg58	mrfip_rx_payld_reg58	RX_PAYLD_REG58
0x57	REG	rx payload reg59	mrfip_rx_payld_reg59	RX_PAYLD_REG59
0x58	REG	rx payload reg60	mrfip_rx_payld_reg60	RX_PAYLD_REG60
0x59	REG	rx payload reg61	mrfip_rx_payld_reg61	RX_PAYLD_REG61
0x5a	REG	rx payload reg62	mrfip_rx_payld_reg62	RX_PAYLD_REG62
0x5b	REG	rx payload reg63	mrfip_rx_payld_reg63	RX_PAYLD_REG63
0x5c	REG	rx payload reg64	mrfip_rx_payld_reg64	RX_PAYLD_REG64
0x5d	REG	rx payload reg65	mrfip_rx_payld_reg65	RX_PAYLD_REG65
0x5e	REG	rx payload reg66	mrfip_rx_payld_reg66	RX_PAYLD_REG66
0x5f	REG	rx payload reg67	mrfip_rx_payld_reg67	RX_PAYLD_REG67
0x60	REG	tx ctrl byte	mrfip_tx_payld_ctrl	TX_PAYLD_CTRL
0x61	REG	tx payload reg1	mrfip_tx_payld_reg1	TX_PAYLD_REG1
0x62	REG	tx payload reg2	mrfip_tx_payld_reg2	TX_PAYLD_REG2
0x63	REG	tx payload reg3	mrfip_tx_payld_reg3	TX_PAYLD_REG3
0x64	REG	tx payload reg4	mrfip_tx_payld_reg4	TX_PAYLD_REG4
0x65	REG	tx payload reg5	mrfip_tx_payld_reg5	TX_PAYLD_REG5
0x66	REG	tx payload reg6	mrfip_tx_payld_reg6	TX_PAYLD_REG6
0x67	REG	tx payload reg7	mrfip_tx_payld_reg7	TX_PAYLD_REG7
0x68	REG	tx payload reg8	mrfip_tx_payld_reg8	TX_PAYLD_REG8
0x69	REG	tx payload reg9	mrfip_tx_payld_reg9	TX_PAYLD_REG9
0x6a	REG	tx payload reg10	mrfip_tx_payld_reg10	TX_PAYLD_REG10
0x6b	REG	tx payload reg11	mrfip_tx_payld_reg11	TX_PAYLD_REG11
0x6c	REG	tx payload reg12	mrfip_tx_payld_reg12	TX_PAYLD_REG12
0x6d	REG	tx payload reg13	mrfip_tx_payld_reg13	TX_PAYLD_REG13
0x6e	REG	tx payload reg14	mrfip_tx_payld_reg14	TX_PAYLD_REG14
0x6f	REG	tx payload reg15	mrfip_tx_payld_reg15	TX_PAYLD_REG15
0x70	REG	tx payload reg16	mrfip_tx_payld_reg16	TX_PAYLD_REG16
0x71	REG	tx payload reg17	mrfip_tx_payld_reg17	TX_PAYLD_REG17
0x72	REG	tx payload reg18	mrfip_tx_payld_reg18	TX_PAYLD_REG18
0x73	REG	tx payload reg19	mrfip_tx_payld_reg19	TX_PAYLD_REG19
0x74	REG	tx payload reg20	mrfip_tx_payld_reg20	TX_PAYLD_REG20
0x75	REG	tx payload reg21	mrfip_tx_payld_reg21	TX_PAYLD_REG21
0x76	REG	tx payload reg22	mrfip_tx_payld_reg22	TX_PAYLD_REG22
0x77	REG	tx payload reg23	mrfip_tx_payld_reg23	TX_PAYLD_REG23
0x78	REG	tx payload reg24	mrfip_tx_payld_reg24	TX_PAYLD_REG24
0x79	REG	tx payload reg25	mrfip_tx_payld_reg25	TX_PAYLD_REG25
0x7a	REG	tx payload reg26	mrfip_tx_payld_reg26	TX_PAYLD_REG26
0x7b	REG	tx payload reg27	mrfip_tx_payld_reg27	TX_PAYLD_REG27
0x7c	REG	tx payload reg28	mrfip_tx_payld_reg28	TX_PAYLD_REG28
0x7d	REG	tx payload reg29	mrfip_tx_payld_reg29	TX_PAYLD_REG29
0x7e	REG	tx payload reg30	mrfip_tx_payld_reg30	TX_PAYLD_REG30
0x7f	REG	tx payload reg31	mrfip_tx_payld_reg31	TX_PAYLD_REG31
0x80	REG	tx payload reg32	mrfip_tx_payld_reg32	TX_PAYLD_REG32
0x81	REG	tx payload reg33	mrfip_tx_payld_reg33	TX_PAYLD_REG33
0x82	REG	tx payload reg34	mrfip_tx_payld_reg34	TX_PAYLD_REG34
0x83	REG	tx payload reg35	mrfip_tx_payld_reg35	TX_PAYLD_REG35
0x84	REG	tx payload reg36	mrfip_tx_payld_reg36	TX_PAYLD_REG36
0x85	REG	tx payload reg37	mrfip_tx_payld_reg37	TX_PAYLD_REG37
0x86	REG	tx payload reg38	mrfip_tx_payld_reg38	TX_PAYLD_REG38
0x87	REG	tx payload reg39	mrfip_tx_payld_reg39	TX_PAYLD_REG39
0x88	REG	tx payload reg40	mrfip_tx_payld_reg40	TX_PAYLD_REG40
0x89	REG	tx payload reg41	mrfip_tx_payld_reg41	TX_PAYLD_REG41
0x8a	REG	tx payload reg42	mrfip_tx_payld_reg42	TX_PAYLD_REG42
0x8b	REG	tx payload reg43	mrfip_tx_payld_reg43	TX_PAYLD_REG43
0x8c	REG	tx payload reg44	mrfip_tx_payld_reg44	TX_PAYLD_REG44
0x8d	REG	tx payload reg45	mrfip_tx_payld_reg45	TX_PAYLD_REG45
0x8e	REG	tx payload reg46	mrfip_tx_payld_reg46	TX_PAYLD_REG46
0x8f	REG	tx payload reg47	mrfip_tx_payld_reg47	TX_PAYLD_REG47
0x90	REG	tx payload reg48	mrfip_tx_payld_reg48	TX_PAYLD_REG48
0x91	REG	tx payload reg49	mrfip_tx_payld_reg49	TX_PAYLD_REG49
0x92	REG	tx payload reg50	mrfip_tx_payld_reg50	TX_PAYLD_REG50
0x93	REG	tx payload reg51	mrfip_tx_payld_reg51	TX_PAYLD_REG51
0x94	REG	tx payload reg52	mrfip_tx_payld_reg52	TX_PAYLD_REG52
0x95	REG	tx payload reg53	mrfip_tx_payld_reg53	TX_PAYLD_REG53
0x96	REG	tx payload reg54	mrfip_tx_payld_reg54	TX_PAYLD_REG54
0x97	REG	tx payload reg55	mrfip_tx_payld_reg55	TX_PAYLD_REG55
0x98	REG	tx payload reg56	mrfip_tx_payld_reg56	TX_PAYLD_REG56
0x99	REG	tx payload reg57	mrfip_tx_payld_reg57	TX_PAYLD_REG57
0x9a	REG	tx payload reg58	mrfip_tx_payld_reg58	TX_PAYLD_REG58
0x9b	REG	tx payload reg59	mrfip_tx_payld_reg59	TX_PAYLD_REG59
0x9c	REG	tx payload reg60	mrfip_tx_payld_reg60	TX_PAYLD_REG60
0x9d	REG	tx payload reg61	mrfip_tx_payld_reg61	TX_PAYLD_REG61
0x9e	REG	tx payload reg62	mrfip_tx_payld_reg62	TX_PAYLD_REG62
0x9f	REG	tx payload reg63	mrfip_tx_payld_reg63	TX_PAYLD_REG63
0xa0	REG	tx payload reg64	mrfip_tx_payld_reg64	TX_PAYLD_REG64
0xa1	REG	tx payload reg65	mrfip_tx_payld_reg65	TX_PAYLD_REG65
0xa2	REG	tx payload reg66	mrfip_tx_payld_reg66	TX_PAYLD_REG66
0xa3	REG	tx payload reg67	mrfip_tx_payld_reg67	TX_PAYLD_REG67

2. HDL symbol

→	rst_n_i	rst:
→	clk_sys_i	mrfip_rst_core_o	→
⇒	wb_adr_i[7:0]	mrfip_rst_fd_o	→
⇒	wb_dat_i[31:0]
⇐	wb_dat_o[31:0]	id:
→	wb_cyc_i
⇒	wb_sel_i[3:0]	dbg:
→	wb_stb_i	mrfip_dbg_o[31:0]	⇒
→	wb_we_i
←	wb_ack_o	mezzanine temperature:
←	wb_stall_o	mrfip_ds1820_temper_i[15:0]	⇐

		mezzanine unique id lsb:
		mrfip_ds1820_id_lsb_i[31:0]	⇐

		mezzanine unique id msb:
		mrfip_ds1820_id_msb_i[31:0]	⇐

		adc:
		mrfip_adc_1v8_shdn_n_o	→
		mrfip_adc_m5v_shdn_n_o	→
		mrfip_adc_5v_en_n_o	→
		mrfip_adc_prim_conn_n_o	→
		mrfip_adc_sec_conn_n_o	→

		dac:
		mrfip_dac_config_value_o[15:0]	⇒
		mrfip_dac_config_load_o	→

		ext sync:
		mrfip_ext_sync_term_en_o	→
		mrfip_ext_sync_dir_o	→
		mrfip_ext_sync_oe_n_o	→
		mrfip_ext_sync_tst_n_o	→
		mrfip_ext_sync_p_cnt_rst_o	→

		ext sync pulses cnt:
		mrfip_ext_sync_p_cnt_i[31:0]	⇐

		bus speed:
		mrfip_speed_i[1:0]	⇐

		macrocycle lgth:
		mrfip_macrocyc_lgth_o[30:0]	⇒
		mrfip_macrocyc_start_o	→

		turnaround lgth:
		mrfip_turnar_lgth_o[30:0]	⇒
		mrfip_turnar_start_o	→

		silence lgth:
		mrfip_silen_lgth_o[30:0]	⇒
		mrfip_silen_start_o	→

		macrocycle time cnt:
		mrfip_macrocyc_time_cnt_i[30:0]	⇐

		macrocycles number cnt:
		mrfip_macrocyc_num_cnt_i[31:0]	⇐

		turnaround time cnt:
		mrfip_turnar_time_cnt_i[30:0]	⇐

		silence time cnt:
		mrfip_silen_time_cnt_i[30:0]	⇐

		tx ctrl:
		mrfip_tx_ctrl_rst_o	→
		mrfip_tx_ctrl_start_o	→
		mrfip_tx_ctrl_bytes_num_o[15:0]	⇒

		tx status:
		mrfip_tx_stat_stop_i	←
		mrfip_tx_stat_ena_i	←
		mrfip_tx_stat_curr_byte_indx_i[15:0]	⇐

		fieldrive wdgn, cdn:
		mrfip_fd_wdg_i	←
		mrfip_fd_cd_i	←

		fieldrive wdg timestamp:
		mrfip_fd_wdg_tstamp_i[31:0]	⇐

		fieldrive txer cnt:
		mrfip_fd_txer_cnt_i[31:0]	⇐

		fieldrive txer tstamp:
		mrfip_fd_txer_tstamp_i[31:0]	⇐

		rx ctrl:
		mrfip_rx_ctrl_rst_o	→

		rx status:
		mrfip_rx_stat_pream_ok_i	←
		mrfip_rx_stat_frame_ok_i	←
		mrfip_rx_stat_frame_crc_err_i	←
		mrfip_rx_stat_bytes_num_i[15:0]	⇐

		rx current word index:
		mrfip_rx_stat_curr_word_indx_i[6:0]	⇐

		rx number of frames with CRC error:
		mrfip_rx_stat_crc_err_cnt_i[31:0]	⇐

		rx payload ctrl byte:
		mrfip_rx_payld_ctrl_i[7:0]	⇐

		rx payload reg1:
		mrfip_rx_payld_reg1_i[31:0]	⇐

		rx payload reg2:
		mrfip_rx_payld_reg2_i[31:0]	⇐

		rx payload reg3:
		mrfip_rx_payld_reg3_i[31:0]	⇐

		rx payload reg4:
		mrfip_rx_payld_reg4_i[31:0]	⇐

		rx payload reg5:
		mrfip_rx_payld_reg5_i[31:0]	⇐

		rx payload reg6:
		mrfip_rx_payld_reg6_i[31:0]	⇐

		rx payload reg7:
		mrfip_rx_payld_reg7_i[31:0]	⇐

		rx payload reg8:
		mrfip_rx_payld_reg8_i[31:0]	⇐

		rx payload reg9:
		mrfip_rx_payld_reg9_i[31:0]	⇐

		rx payload reg10:
		mrfip_rx_payld_reg10_i[31:0]	⇐

		rx payload reg11:
		mrfip_rx_payld_reg11_i[31:0]	⇐

		rx payload reg12:
		mrfip_rx_payld_reg12_i[31:0]	⇐

		rx payload reg13:
		mrfip_rx_payld_reg13_i[31:0]	⇐

		rx payload reg14:
		mrfip_rx_payld_reg14_i[31:0]	⇐

		rx payload reg15:
		mrfip_rx_payld_reg15_i[31:0]	⇐

		rx payload reg16:
		mrfip_rx_payld_reg16_i[31:0]	⇐

		rx payload reg17:
		mrfip_rx_payld_reg17_i[31:0]	⇐

		rx payload reg18:
		mrfip_rx_payld_reg18_i[31:0]	⇐

		rx payload reg19:
		mrfip_rx_payld_reg19_i[31:0]	⇐

		rx payload reg20:
		mrfip_rx_payld_reg20_i[31:0]	⇐

		rx payload reg21:
		mrfip_rx_payld_reg21_i[31:0]	⇐

		rx payload reg22:
		mrfip_rx_payld_reg22_i[31:0]	⇐

		rx payload reg23:
		mrfip_rx_payld_reg23_i[31:0]	⇐

		rx payload reg24:
		mrfip_rx_payld_reg24_i[31:0]	⇐

		rx payload reg25:
		mrfip_rx_payld_reg25_i[31:0]	⇐

		rx payload reg26:
		mrfip_rx_payld_reg26_i[31:0]	⇐

		rx payload reg27:
		mrfip_rx_payld_reg27_i[31:0]	⇐

		rx payload reg28:
		mrfip_rx_payld_reg28_i[31:0]	⇐

		rx payload reg29:
		mrfip_rx_payld_reg29_i[31:0]	⇐

		rx payload reg30:
		mrfip_rx_payld_reg30_i[31:0]	⇐

		rx payload reg31:
		mrfip_rx_payld_reg31_i[31:0]	⇐

		rx payload reg32:
		mrfip_rx_payld_reg32_i[31:0]	⇐

		rx payload reg33:
		mrfip_rx_payld_reg33_i[31:0]	⇐

		rx payload reg34:
		mrfip_rx_payld_reg34_i[31:0]	⇐

		rx payload reg35:
		mrfip_rx_payld_reg35_i[31:0]	⇐

		rx payload reg36:
		mrfip_rx_payld_reg36_i[31:0]	⇐

		rx payload reg37:
		mrfip_rx_payld_reg37_i[31:0]	⇐

		rx payload reg38:
		mrfip_rx_payld_reg38_i[31:0]	⇐

		rx payload reg39:
		mrfip_rx_payld_reg39_i[31:0]	⇐

		rx payload reg40:
		mrfip_rx_payld_reg40_i[31:0]	⇐

		rx payload reg41:
		mrfip_rx_payld_reg41_i[31:0]	⇐

		rx payload reg42:
		mrfip_rx_payld_reg42_i[31:0]	⇐

		rx payload reg43:
		mrfip_rx_payld_reg43_i[31:0]	⇐

		rx payload reg44:
		mrfip_rx_payld_reg44_i[31:0]	⇐

		rx payload reg45:
		mrfip_rx_payld_reg45_i[31:0]	⇐

		rx payload reg46:
		mrfip_rx_payld_reg46_i[31:0]	⇐

		rx payload reg47:
		mrfip_rx_payld_reg47_i[31:0]	⇐

		rx payload reg48:
		mrfip_rx_payld_reg48_i[31:0]	⇐

		rx payload reg49:
		mrfip_rx_payld_reg49_i[31:0]	⇐

		rx payload reg50:
		mrfip_rx_payld_reg50_i[31:0]	⇐

		rx payload reg51:
		mrfip_rx_payld_reg51_i[31:0]	⇐

		rx payload reg52:
		mrfip_rx_payld_reg52_i[31:0]	⇐

		rx payload reg53:
		mrfip_rx_payld_reg53_i[31:0]	⇐

		rx payload reg54:
		mrfip_rx_payld_reg54_i[31:0]	⇐

		rx payload reg55:
		mrfip_rx_payld_reg55_i[31:0]	⇐

		rx payload reg56:
		mrfip_rx_payld_reg56_i[31:0]	⇐

		rx payload reg57:
		mrfip_rx_payld_reg57_i[31:0]	⇐

		rx payload reg58:
		mrfip_rx_payld_reg58_i[31:0]	⇐

		rx payload reg59:
		mrfip_rx_payld_reg59_i[31:0]	⇐

		rx payload reg60:
		mrfip_rx_payld_reg60_i[31:0]	⇐

		rx payload reg61:
		mrfip_rx_payld_reg61_i[31:0]	⇐

		rx payload reg62:
		mrfip_rx_payld_reg62_i[31:0]	⇐

		rx payload reg63:
		mrfip_rx_payld_reg63_i[31:0]	⇐

		rx payload reg64:
		mrfip_rx_payld_reg64_i[31:0]	⇐

		rx payload reg65:
		mrfip_rx_payld_reg65_i[31:0]	⇐

		rx payload reg66:
		mrfip_rx_payld_reg66_i[31:0]	⇐

		rx payload reg67:
		mrfip_rx_payld_reg67_i[31:0]	⇐

		tx ctrl byte:
		mrfip_tx_payld_ctrl_o[7:0]	⇒

		tx payload reg1:
		mrfip_tx_payld_reg1_o[31:0]	⇒

		tx payload reg2:
		mrfip_tx_payld_reg2_o[31:0]	⇒

		tx payload reg3:
		mrfip_tx_payld_reg3_o[31:0]	⇒

		tx payload reg4:
		mrfip_tx_payld_reg4_o[31:0]	⇒

		tx payload reg5:
		mrfip_tx_payld_reg5_o[31:0]	⇒

		tx payload reg6:
		mrfip_tx_payld_reg6_o[31:0]	⇒

		tx payload reg7:
		mrfip_tx_payld_reg7_o[31:0]	⇒

		tx payload reg8:
		mrfip_tx_payld_reg8_o[31:0]	⇒

		tx payload reg9:
		mrfip_tx_payld_reg9_o[31:0]	⇒

		tx payload reg10:
		mrfip_tx_payld_reg10_o[31:0]	⇒

		tx payload reg11:
		mrfip_tx_payld_reg11_o[31:0]	⇒

		tx payload reg12:
		mrfip_tx_payld_reg12_o[31:0]	⇒

		tx payload reg13:
		mrfip_tx_payld_reg13_o[31:0]	⇒

		tx payload reg14:
		mrfip_tx_payld_reg14_o[31:0]	⇒

		tx payload reg15:
		mrfip_tx_payld_reg15_o[31:0]	⇒

		tx payload reg16:
		mrfip_tx_payld_reg16_o[31:0]	⇒

		tx payload reg17:
		mrfip_tx_payld_reg17_o[31:0]	⇒

		tx payload reg18:
		mrfip_tx_payld_reg18_o[31:0]	⇒

		tx payload reg19:
		mrfip_tx_payld_reg19_o[31:0]	⇒

		tx payload reg20:
		mrfip_tx_payld_reg20_o[31:0]	⇒

		tx payload reg21:
		mrfip_tx_payld_reg21_o[31:0]	⇒

		tx payload reg22:
		mrfip_tx_payld_reg22_o[31:0]	⇒

		tx payload reg23:
		mrfip_tx_payld_reg23_o[31:0]	⇒

		tx payload reg24:
		mrfip_tx_payld_reg24_o[31:0]	⇒

		tx payload reg25:
		mrfip_tx_payld_reg25_o[31:0]	⇒

		tx payload reg26:
		mrfip_tx_payld_reg26_o[31:0]	⇒

		tx payload reg27:
		mrfip_tx_payld_reg27_o[31:0]	⇒

		tx payload reg28:
		mrfip_tx_payld_reg28_o[31:0]	⇒

		tx payload reg29:
		mrfip_tx_payld_reg29_o[31:0]	⇒

		tx payload reg30:
		mrfip_tx_payld_reg30_o[31:0]	⇒

		tx payload reg31:
		mrfip_tx_payld_reg31_o[31:0]	⇒

		tx payload reg32:
		mrfip_tx_payld_reg32_o[31:0]	⇒

		tx payload reg33:
		mrfip_tx_payld_reg33_o[31:0]	⇒

		tx payload reg34:
		mrfip_tx_payld_reg34_o[31:0]	⇒

		tx payload reg35:
		mrfip_tx_payld_reg35_o[31:0]	⇒

		tx payload reg36:
		mrfip_tx_payld_reg36_o[31:0]	⇒

		tx payload reg37:
		mrfip_tx_payld_reg37_o[31:0]	⇒

		tx payload reg38:
		mrfip_tx_payld_reg38_o[31:0]	⇒

		tx payload reg39:
		mrfip_tx_payld_reg39_o[31:0]	⇒

		tx payload reg40:
		mrfip_tx_payld_reg40_o[31:0]	⇒

		tx payload reg41:
		mrfip_tx_payld_reg41_o[31:0]	⇒

		tx payload reg42:
		mrfip_tx_payld_reg42_o[31:0]	⇒

		tx payload reg43:
		mrfip_tx_payld_reg43_o[31:0]	⇒

		tx payload reg44:
		mrfip_tx_payld_reg44_o[31:0]	⇒

		tx payload reg45:
		mrfip_tx_payld_reg45_o[31:0]	⇒

		tx payload reg46:
		mrfip_tx_payld_reg46_o[31:0]	⇒

		tx payload reg47:
		mrfip_tx_payld_reg47_o[31:0]	⇒

		tx payload reg48:
		mrfip_tx_payld_reg48_o[31:0]	⇒

		tx payload reg49:
		mrfip_tx_payld_reg49_o[31:0]	⇒

		tx payload reg50:
		mrfip_tx_payld_reg50_o[31:0]	⇒

		tx payload reg51:
		mrfip_tx_payld_reg51_o[31:0]	⇒

		tx payload reg52:
		mrfip_tx_payld_reg52_o[31:0]	⇒

		tx payload reg53:
		mrfip_tx_payld_reg53_o[31:0]	⇒

		tx payload reg54:
		mrfip_tx_payld_reg54_o[31:0]	⇒

		tx payload reg55:
		mrfip_tx_payld_reg55_o[31:0]	⇒

		tx payload reg56:
		mrfip_tx_payld_reg56_o[31:0]	⇒

		tx payload reg57:
		mrfip_tx_payld_reg57_o[31:0]	⇒

		tx payload reg58:
		mrfip_tx_payld_reg58_o[31:0]	⇒

		tx payload reg59:
		mrfip_tx_payld_reg59_o[31:0]	⇒

		tx payload reg60:
		mrfip_tx_payld_reg60_o[31:0]	⇒

		tx payload reg61:
		mrfip_tx_payld_reg61_o[31:0]	⇒

		tx payload reg62:
		mrfip_tx_payld_reg62_o[31:0]	⇒

		tx payload reg63:
		mrfip_tx_payld_reg63_o[31:0]	⇒

		tx payload reg64:
		mrfip_tx_payld_reg64_o[31:0]	⇒

		tx payload reg65:
		mrfip_tx_payld_reg65_o[31:0]	⇒

		tx payload reg66:
		mrfip_tx_payld_reg66_o[31:0]	⇒

		tx payload reg67:
		mrfip_tx_payld_reg67_o[31:0]	⇒

3. Register description

3.1. rst

HW prefix:	mrfip_rst
HW address:	0x0
C prefix:	RST
C offset:	0x0

software reset of the masterFIP core

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-

7	6	5	4	3	2	1	0
-	-	-	-	-	-	FD	CORE

CORE [write-only]: reset of the masterFIP core
write 1: generates a 1-tick-long (10ns) masterFIP core reset;
note: there is no need to clear the field before writing another '1'
FD [write-only]: reset of the fieldrive chip
write 1: to generate a fieldrive reset;
upon writing, the masterFIP_core generates a 1-WorldFIP-tick-long FD RSTN;
note: there is no need to clear the field before writing another '1'

3.2. id

HW prefix:	mrfip_id
HW address:	0x1
C prefix:	ID
C offset:	0x4

constant identification value: COOOFFEE

31	30	29	28	27	26	25	24
ID[31:24]

23	22	21	20	19	18	17	16
ID[23:16]

15	14	13	12	11	10	9	8
ID[15:8]

7	6	5	4	3	2	1	0
ID[7:0]

ID [read-only]: an id value
equal to 0xc000ffee for the moment

3.3. dbg

HW prefix:	mrfip_dbg
HW address:	0x2
C prefix:	DBG
C offset:	0x8

for debugging purposes; used to pass signals to front panel LEDs

31	30	29	28	27	26	25	24
DBG[31:24]

23	22	21	20	19	18	17	16
DBG[23:16]

15	14	13	12	11	10	9	8
DBG[15:8]

7	6	5	4	3	2	1	0
DBG[7:0]

DBG [read/write]: debugging

3.4. mezzanine temperature

HW prefix:	mrfip_ds1820_temper
HW address:	0x3
C prefix:	DS1820_TEMPER
C offset:	0xc

raw temperature data from the one wire DS18B20U+;
the register is 2-bytes long; it translates to oC as follows:
temp = ((byte1 << 8) | byte0) / 16.0

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
DS1820_TEMPER[15:8]

7	6	5	4	3	2	1	0
DS1820_TEMPER[7:0]

DS1820_TEMPER [read-only]: ds1820 temperature

3.5. mezzanine unique id lsb

HW prefix:	mrfip_ds1820_id_lsb
HW address:	0x4
C prefix:	DS1820_ID_LSB
C offset:	0x10

id (lsb) read from the one wire DS18B20U+

31	30	29	28	27	26	25	24
DS1820_ID_LSB[31:24]

23	22	21	20	19	18	17	16
DS1820_ID_LSB[23:16]

15	14	13	12	11	10	9	8
DS1820_ID_LSB[15:8]

7	6	5	4	3	2	1	0
DS1820_ID_LSB[7:0]

DS1820_ID_LSB [read-only]: ds1820 id lsb

3.6. mezzanine unique id msb

HW prefix:	mrfip_ds1820_id_msb
HW address:	0x5
C prefix:	DS1820_ID_MSB
C offset:	0x14

id (msb) read from the one wire DS18B20U+

31	30	29	28	27	26	25	24
DS1820_ID_MSB[31:24]

23	22	21	20	19	18	17	16
DS1820_ID_MSB[23:16]

15	14	13	12	11	10	9	8
DS1820_ID_MSB[15:8]

7	6	5	4	3	2	1	0
DS1820_ID_MSB[7:0]

DS1820_ID_MSB [read-only]: ds1820 id msb

3.7. adc

HW prefix:	mrfip_adc
HW address:	0x6
C prefix:	ADC
C offset:	0x18

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	SEC_CONN_N	PRIM_CONN_N

7	6	5	4	3	2	1	0
-	-	-	-	-	5V_EN_N	M5V_SHDN_N	1V8_SHDN_N

1V8_SHDN_N [read/write]: 1v8_shdn_n
write 0: disable the ADC 1V8
write 1: enable the ADC 1V8
M5V_SHDN_N [read/write]: m5v_shdn_n
write 0: disable the ADC M5V
write 1: enable the ADC M5V
5V_EN_N [read/write]: 5v_en_n
write 0: enable the ADC 5V
write 1: disable the ADC 5V
PRIM_CONN_N [read/write]: prim_conn_n
write 0: connect the ADC to the primary side of the FieldTR (bus side)
write 1: disconnect the ADC from the primary side of the FieldTR (bus side)
SEC_CONN_N [read/write]: sec_conn_n
write 0: connect the ADC to the secondary side of the FieldTR (FielDrive side)
write 1: disconnect the ADC from the secondary side of the FieldTR (FielDrive side)

3.8. dac

HW prefix:	mrfip_dac_config
HW address:	0x7
C prefix:	DAC_CONFIG
C offset:	0x1c

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	LOAD

15	14	13	12	11	10	9	8
VALUE[15:8]

7	6	5	4	3	2	1	0
VALUE[7:0]

VALUE [read/write]: value
Vout= Vref (value/ 65536)
For the DAC middle range: value = 32768 = 0x8000
LOAD [read/write]: load
write 1: loads the dac with the dac_value;
note: there is no need to clear the field before writing another '1'

3.9. ext sync

HW prefix:	mrfip_ext_sync
HW address:	0x8
C prefix:	EXT_SYNC
C offset:	0x20

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	P_CNT_RST

7	6	5	4	3	2	1	0
-	-	-	-	TST_N	OE_N	DIR	TERM_EN

TERM_EN [read/write]: termination enable
write 0: disable 50ohms termination of the external sync pulse
write 1: enable 50ohms termination of the external sync pulse
DIR [read/write]: transceiver direction
write 0: normal operation
write 1: test mode where a pulse from the FPGA can be output to the front panel LEMO connector
OE_N [read/write]: transceiver output enable negative logic
write 0: normal operation, the external sync pulse arrives to the FPGA
write 1: the external sync pulse does not arrive to the FPGA
TST_N [read/write]: test pulse
emulate a pulse
P_CNT_RST [read/write]: pulses counter reset
resets the pulses counter

3.10. ext sync pulses cnt

HW prefix:	mrfip_ext_sync_p_cnt
HW address:	0x9
C prefix:	EXT_SYNC_P_CNT
C offset:	0x24

31	30	29	28	27	26	25	24
EXT_SYNC_P_CNT[31:24]

23	22	21	20	19	18	17	16
EXT_SYNC_P_CNT[23:16]

15	14	13	12	11	10	9	8
EXT_SYNC_P_CNT[15:8]

7	6	5	4	3	2	1	0
EXT_SYNC_P_CNT[7:0]

EXT_SYNC_P_CNT [read-only]: ext_sync_p_cnt
number of ext sync pulses

3.11. bus speed

HW prefix:	mrfip_speed
HW address:	0xa
C prefix:	SPEED
C offset:	0x28

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-

7	6	5	4	3	2	1	0
-	-	-	-	-	-	SPEED[1:0]

SPEED [read-only]: speed
WorldFIP speed: 00: 31.25Kbps
01: 1Mbps
10: 2.5 Mbps
11: 5 Mbps

3.12. macrocycle lgth

HW prefix:	mrfip_macrocyc
HW address:	0xb
C prefix:	MACROCYC
C offset:	0x2c

31	30	29	28	27	26	25	24
START	LGTH[30:24]

23	22	21	20	19	18	17	16
LGTH[23:16]

15	14	13	12	11	10	9	8
LGTH[15:8]

7	6	5	4	3	2	1	0
LGTH[7:0]

LGTH [read/write]: macrocycle lgth
duration of the macrocycle in number of 10ns-clk-ticks
START [read/write]: macrocycle cnt start
write 1: initiates the counting of the macrocycle counter
note: there is no need to clear the field before writing another '1'

3.13. turnaround lgth

HW prefix:	mrfip_turnar
HW address:	0xc
C prefix:	TURNAR
C offset:	0x30

31	30	29	28	27	26	25	24
START	LGTH[30:24]

23	22	21	20	19	18	17	16
LGTH[23:16]

15	14	13	12	11	10	9	8
LGTH[15:8]

7	6	5	4	3	2	1	0
LGTH[7:0]

LGTH [read/write]: turnaround time
turnaround time (i.e. time between two frames sent by the masterFIP) in number of 10ns-clk-ticks
START [read/write]: turnaround cnt start
write 1: initiates the counting of the turnaround counter
note: there is no need to clear the field before writing another '1'

3.14. silence lgth

HW prefix:	mrfip_silen
HW address:	0xd
C prefix:	SILEN
C offset:	0x34

31	30	29	28	27	26	25	24
START	LGTH[30:24]

23	22	21	20	19	18	17	16
LGTH[23:16]

15	14	13	12	11	10	9	8
LGTH[15:8]

7	6	5	4	3	2	1	0
LGTH[7:0]

LGTH [read/write]: silence time
silence time (i.e. time that the masterFIP waits for a response frame) number of 10ns-clk-ticks
START [read/write]: silence cnt start
initiates the counting of the silence counter
note: there is no need to clear the field before writing another '1'

3.15. macrocycle time cnt

HW prefix:	mrfip_macrocyc_time_cnt
HW address:	0xe
C prefix:	MACROCYC_TIME_CNT
C offset:	0x38

31	30	29	28	27	26	25	24
-	MACROCYC_TIME_CNT[30:24]

23	22	21	20	19	18	17	16
MACROCYC_TIME_CNT[23:16]

15	14	13	12	11	10	9	8
MACROCYC_TIME_CNT[15:8]

7	6	5	4	3	2	1	0
MACROCYC_TIME_CNT[7:0]

MACROCYC_TIME_CNT [read-only]: macrocycle time counter
current value of the macrocycle time counter

3.16. macrocycles number cnt

HW prefix:	mrfip_macrocyc_num_cnt
HW address:	0xf
C prefix:	MACROCYC_NUM_CNT
C offset:	0x3c

31	30	29	28	27	26	25	24
MACROCYC_NUM_CNT[31:24]

23	22	21	20	19	18	17	16
MACROCYC_NUM_CNT[23:16]

15	14	13	12	11	10	9	8
MACROCYC_NUM_CNT[15:8]

7	6	5	4	3	2	1	0
MACROCYC_NUM_CNT[7:0]

MACROCYC_NUM_CNT [read-only]: number of macrocycles
amount of macrocycles that have been counted so far

3.17. turnaround time cnt

HW prefix:	mrfip_turnar_time_cnt
HW address:	0x10
C prefix:	TURNAR_TIME_CNT
C offset:	0x40

31	30	29	28	27	26	25	24
-	TURNAR_TIME_CNT[30:24]

23	22	21	20	19	18	17	16
TURNAR_TIME_CNT[23:16]

15	14	13	12	11	10	9	8
TURNAR_TIME_CNT[15:8]

7	6	5	4	3	2	1	0
TURNAR_TIME_CNT[7:0]

TURNAR_TIME_CNT [read-only]: turnaround time counter
current value of the turnaround time counter

3.18. silence time cnt

HW prefix:	mrfip_silen_time_cnt
HW address:	0x11
C prefix:	SILEN_TIME_CNT
C offset:	0x44

31	30	29	28	27	26	25	24
-	SILEN_TIME_CNT[30:24]

23	22	21	20	19	18	17	16
SILEN_TIME_CNT[23:16]

15	14	13	12	11	10	9	8
SILEN_TIME_CNT[15:8]

7	6	5	4	3	2	1	0
SILEN_TIME_CNT[7:0]

SILEN_TIME_CNT [read-only]: silence time counter
current value of the silence time counter

3.19. tx ctrl

HW prefix:	mrfip_tx_ctrl
HW address:	0x12
C prefix:	TX_CTRL
C offset:	0x48

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
BYTES_NUM[15:8]

15	14	13	12	11	10	9	8
BYTES_NUM[7:0]

7	6	5	4	3	2	1	0
-	-	-	-	-	-	START	RST

RST [read/write]: tx rst
write 1: generates a 1-tick-long reset to the serializer
note: there is no need to clear the field before writing another '1'
START [read/write]: tx strt
write 1: initiates the serializer to send a frame of tx_ctrl_bytes_num payload bytes;
the bytes are retrieved one-by-one by the registers: tx_payld_ctrl, tx_payld_reg1..tx_payld_reg67;
the bytes: FSS, CRC and FES are generated automatically by the serializer.
note: there is no need to clear the field before writing another '1'
BYTES_NUM [read/write]: tx number of bytes
number of bytes to serialize; the number should include all the bytes in the Control and Data fields
of a frame and not include the bytes in the Preamble, CRC, Postamble fields; the masterFIP_core samples
this number upon the tx_strt; note that for the max supported WorldFIP frame, which is a message of
256 Data bytes, the number of bytes to serialize = 263 (Control byte+6 address bytes+256 Data bytes)

3.20. tx status

HW prefix:	mrfip_tx_stat
HW address:	0x13
C prefix:	TX_STAT
C offset:	0x4c

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	CURR_BYTE_INDX[15:15]

23	22	21	20	19	18	17	16
CURR_BYTE_INDX[14:7]

15	14	13	12	11	10	9	8
CURR_BYTE_INDX[6:0]							ENA

7	6	5	4	3	2	1	0
-	-	-	-	-	-	-	STOP

STOP [read-only]: tx ended
indication that the serializer finished the delivery of a frame
the bit stays active until a rstn_core or a tx_ctrl_rst or a tx_ctrl_strt
ENA [read-only]: tx enable
fieldrive fd_txena signal;
read 0: masterFIP serializer is inactive
read 1: masterFIP serializer is active putting bits to the bus
CURR_BYTE_INDX [read-only]: tx status current byte index
index of the current byte being serialized;
the counting starts from 0 after the preamble...

3.21. fieldrive wdgn, cdn

HW prefix:	mrfip_fd
HW address:	0x14
C prefix:	FD
C offset:	0x50

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-

7	6	5	4	3	2	1	0
-	-	-	-	-	-	CD	WDG

WDG [read-only]: fieldrive watchdog
read 1: the fd_wdgn has been activated
read 0: no problemo
Note that if triggered, the fd_wdgn stays active until a fd_rstn
CD [read-only]: fieldrive carrier detect
read 1: carrier detect active
read 0: no bus traffic

3.22. fieldrive wdg timestamp

HW prefix:	mrfip_fd_wdg_tstamp
HW address:	0x15
C prefix:	FD_WDG_TSTAMP
C offset:	0x54

31	30	29	28	27	26	25	24
FD_WDG_TSTAMP[31:24]

23	22	21	20	19	18	17	16
FD_WDG_TSTAMP[23:16]

15	14	13	12	11	10	9	8
FD_WDG_TSTAMP[15:8]

7	6	5	4	3	2	1	0
FD_WDG_TSTAMP[7:0]

FD_WDG_TSTAMP [read-only]: fd_wdgn_tstamp
timestamp of the moment in the macrocycle when the fd_wdg
was activated.
The field is automatically cleared upon a new macrocycle or
upon a rstn_fd or rstn_core

3.23. fieldrive txer cnt

HW prefix:	mrfip_fd_txer_cnt
HW address:	0x16
C prefix:	FD_TXER_CNT
C offset:	0x58

31	30	29	28	27	26	25	24
FD_TXER_CNT[31:24]

23	22	21	20	19	18	17	16
FD_TXER_CNT[23:16]

15	14	13	12	11	10	9	8
FD_TXER_CNT[15:8]

7	6	5	4	3	2	1	0
FD_TXER_CNT[7:0]

FD_TXER_CNT [read-only]: fd_txer_cnt
counter of the number of fd_txer rising edges that appear in this
current macrocycle.
The field is automatically cleared upon a new macrocycle or
upon a rstn_fd or rstn_core

3.24. fieldrive txer tstamp

HW prefix:	mrfip_fd_txer_tstamp
HW address:	0x17
C prefix:	FD_TXER_TSTAMP
C offset:	0x5c

31	30	29	28	27	26	25	24
FD_TXER_TSTAMP[31:24]

23	22	21	20	19	18	17	16
FD_TXER_TSTAMP[23:16]

15	14	13	12	11	10	9	8
FD_TXER_TSTAMP[15:8]

7	6	5	4	3	2	1	0
FD_TXER_TSTAMP[7:0]

FD_TXER_TSTAMP [read-only]: fd_txer_tstamp
timestamp of the last moment in the macrocycle when the fd_txer
was activated.
The field is automatically cleared upon a new macrocycle or
upon a rstn_fd or rstn_core

3.25. rx ctrl

HW prefix:	mrfip_rx_ctrl
HW address:	0x18
C prefix:	RX_CTRL
C offset:	0x60

active high reset of the deserializer

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-

7	6	5	4	3	2	1	0
-	-	-	-	-	-	-	RST

RST [read/write]: rx rst
write 1: generates a 1-tick-long reset to the deserializer
note: there is no need to clear the field before writing another '1'
note: the deserializer is automatically hw-reset when the serializer is active

3.26. rx status

HW prefix:	mrfip_rx_stat
HW address:	0x19
C prefix:	RX_STAT
C offset:	0x64

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
BYTES_NUM[15:8]

15	14	13	12	11	10	9	8
BYTES_NUM[7:0]

7	6	5	4	3	2	1	0
-	-	-	-	-	FRAME_CRC_ERR	FRAME_OK	PREAM_OK

PREAM_OK [read-only]: rx preamble detected
indication that the deserializer has detected a preamble;
the bit stays active until a reset of the deserializer (this takes place
automatically upon the activation of the serializer, or upon a rx_ctrl_rst
or upon a core_rstn)
FRAME_OK [read-only]: rx frame ok
indication that the deserializer has finished with the reception of a complete frame;
the preamble, CRC and postambe of the frame are all ok
the bit stays high until a reset of the deserializer (this takes place
automatically upon the activation of the serializer, or upon a rx_ctrl_rst
or upon a rstn_core)
FRAME_CRC_ERR [read-only]: rx frame crc error
indication that the deserializer has detected a frame with CRC error
the bit stays high until a reset of the deserializer (this takes place
automatically upon the activation of the serializer, or upon a rx_rst)
BYTES_NUM [read-only]: rx number of payload bytes
number of payload bytes that have been received by the deserializer
upon the rx_frame_ok activation.
The counter includes all the bytes that come after the Control byte and before the CRC bytes.
note that for the max WorldFIP frame size = 262 bytes (without preamble, Control, CRC, postamble)

3.27. rx current word index

HW prefix:	mrfip_rx_stat_curr_word_indx
HW address:	0x1a
C prefix:	RX_STAT_CURR_WORD_INDX
C offset:	0x68

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-

7	6	5	4	3	2	1	0
-	RX_STAT_CURR_WORD_INDX[6:0]

RX_STAT_CURR_WORD_INDX [read-only]: current word index
index of the current 32-bit-word being deserialized;
word 1: LSB is the Control byte; the other 3 bytes are to be ignored
word 2: contains the first 4 payload bytes..etc
The max frame size is 66 words.
The last word may also include CRC bytes;
for that, upon the rx_frame_ok, the rx_bytes_num indicates the
exact number of payload bytes to be read

3.28. rx number of frames with CRC error

HW prefix:	mrfip_rx_stat_crc_err_cnt
HW address:	0x1b
C prefix:	RX_STAT_CRC_ERR_CNT
C offset:	0x6c

31	30	29	28	27	26	25	24
RX_STAT_CRC_ERR_CNT[31:24]

23	22	21	20	19	18	17	16
RX_STAT_CRC_ERR_CNT[23:16]

15	14	13	12	11	10	9	8
RX_STAT_CRC_ERR_CNT[15:8]

7	6	5	4	3	2	1	0
RX_STAT_CRC_ERR_CNT[7:0]

RX_STAT_CRC_ERR_CNT [read-only]: rx number of frames with CRC error
number of frames with CRC error since the startup or a core_rstn

3.29. rx payload ctrl byte

HW prefix:	mrfip_rx_payld_ctrl
HW address:	0x1c
C prefix:	RX_PAYLD_CTRL
C offset:	0x70

contains the 8-bits of the control field of a received frame

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-

7	6	5	4	3	2	1	0
RX_PAYLD_CTRL[7:0]

RX_PAYLD_CTRL [read-only]: rx payload ctrl byte
contains the 8-bits of the control field of a received frame

3.30. rx payload reg1

HW prefix:	mrfip_rx_payld_reg1
HW address:	0x1d
C prefix:	RX_PAYLD_REG1
C offset:	0x74

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG1[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG1[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG1[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG1[7:0]

RX_PAYLD_REG1 [read-only]: reg 1
1st 32-bit word

3.31. rx payload reg2

HW prefix:	mrfip_rx_payld_reg2
HW address:	0x1e
C prefix:	RX_PAYLD_REG2
C offset:	0x78

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG2[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG2[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG2[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG2[7:0]

RX_PAYLD_REG2 [read-only]: reg2
2nd 32-bit word

3.32. rx payload reg3

HW prefix:	mrfip_rx_payld_reg3
HW address:	0x1f
C prefix:	RX_PAYLD_REG3
C offset:	0x7c

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG3[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG3[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG3[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG3[7:0]

RX_PAYLD_REG3 [read-only]: reg3
3rd 32-bit word

3.33. rx payload reg4

HW prefix:	mrfip_rx_payld_reg4
HW address:	0x20
C prefix:	RX_PAYLD_REG4
C offset:	0x80

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG4[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG4[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG4[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG4[7:0]

RX_PAYLD_REG4 [read-only]: reg4
4th 32-bit word

3.34. rx payload reg5

HW prefix:	mrfip_rx_payld_reg5
HW address:	0x21
C prefix:	RX_PAYLD_REG5
C offset:	0x84

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG5[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG5[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG5[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG5[7:0]

RX_PAYLD_REG5 [read-only]: reg5
5th 32-bit word

3.35. rx payload reg6

HW prefix:	mrfip_rx_payld_reg6
HW address:	0x22
C prefix:	RX_PAYLD_REG6
C offset:	0x88

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG6[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG6[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG6[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG6[7:0]

RX_PAYLD_REG6 [read-only]: reg6
6th 32-bit word

3.36. rx payload reg7

HW prefix:	mrfip_rx_payld_reg7
HW address:	0x23
C prefix:	RX_PAYLD_REG7
C offset:	0x8c

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG7[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG7[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG7[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG7[7:0]

RX_PAYLD_REG7 [read-only]: reg7
7th 32-bit word

3.37. rx payload reg8

HW prefix:	mrfip_rx_payld_reg8
HW address:	0x24
C prefix:	RX_PAYLD_REG8
C offset:	0x90

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG8[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG8[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG8[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG8[7:0]

RX_PAYLD_REG8 [read-only]: reg8
8th 32-bit word

3.38. rx payload reg9

HW prefix:	mrfip_rx_payld_reg9
HW address:	0x25
C prefix:	RX_PAYLD_REG9
C offset:	0x94

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG9[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG9[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG9[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG9[7:0]

RX_PAYLD_REG9 [read-only]: reg9
9th 32-bit word

3.39. rx payload reg10

HW prefix:	mrfip_rx_payld_reg10
HW address:	0x26
C prefix:	RX_PAYLD_REG10
C offset:	0x98

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG10[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG10[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG10[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG10[7:0]

RX_PAYLD_REG10 [read-only]: reg10
10th 32-bit word

3.40. rx payload reg11

HW prefix:	mrfip_rx_payld_reg11
HW address:	0x27
C prefix:	RX_PAYLD_REG11
C offset:	0x9c

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG11[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG11[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG11[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG11[7:0]

RX_PAYLD_REG11 [read-only]: reg11
11th 32-bit word

3.41. rx payload reg12

HW prefix:	mrfip_rx_payld_reg12
HW address:	0x28
C prefix:	RX_PAYLD_REG12
C offset:	0xa0

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG12[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG12[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG12[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG12[7:0]

RX_PAYLD_REG12 [read-only]: reg12
12th 32-bit word

3.42. rx payload reg13

HW prefix:	mrfip_rx_payld_reg13
HW address:	0x29
C prefix:	RX_PAYLD_REG13
C offset:	0xa4

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG13[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG13[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG13[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG13[7:0]

RX_PAYLD_REG13 [read-only]: reg13
13th 32-bit word

3.43. rx payload reg14

HW prefix:	mrfip_rx_payld_reg14
HW address:	0x2a
C prefix:	RX_PAYLD_REG14
C offset:	0xa8

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG14[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG14[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG14[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG14[7:0]

RX_PAYLD_REG14 [read-only]: reg14
14th 32-bit word

3.44. rx payload reg15

HW prefix:	mrfip_rx_payld_reg15
HW address:	0x2b
C prefix:	RX_PAYLD_REG15
C offset:	0xac

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG15[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG15[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG15[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG15[7:0]

RX_PAYLD_REG15 [read-only]: reg15
15th 32-bit word

3.45. rx payload reg16

HW prefix:	mrfip_rx_payld_reg16
HW address:	0x2c
C prefix:	RX_PAYLD_REG16
C offset:	0xb0

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG16[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG16[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG16[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG16[7:0]

RX_PAYLD_REG16 [read-only]: reg16
16th 32-bit word

3.46. rx payload reg17

HW prefix:	mrfip_rx_payld_reg17
HW address:	0x2d
C prefix:	RX_PAYLD_REG17
C offset:	0xb4

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG17[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG17[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG17[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG17[7:0]

RX_PAYLD_REG17 [read-only]: reg17
17th 32-bit word

3.47. rx payload reg18

HW prefix:	mrfip_rx_payld_reg18
HW address:	0x2e
C prefix:	RX_PAYLD_REG18
C offset:	0xb8

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG18[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG18[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG18[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG18[7:0]

RX_PAYLD_REG18 [read-only]: reg18
18th 32-bit word

3.48. rx payload reg19

HW prefix:	mrfip_rx_payld_reg19
HW address:	0x2f
C prefix:	RX_PAYLD_REG19
C offset:	0xbc

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG19[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG19[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG19[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG19[7:0]

RX_PAYLD_REG19 [read-only]: reg19
19th 32-bit word

3.49. rx payload reg20

HW prefix:	mrfip_rx_payld_reg20
HW address:	0x30
C prefix:	RX_PAYLD_REG20
C offset:	0xc0

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG20[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG20[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG20[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG20[7:0]

RX_PAYLD_REG20 [read-only]: reg20
20th 32-bit word

3.50. rx payload reg21

HW prefix:	mrfip_rx_payld_reg21
HW address:	0x31
C prefix:	RX_PAYLD_REG21
C offset:	0xc4

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG21[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG21[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG21[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG21[7:0]

RX_PAYLD_REG21 [read-only]: reg21
21th 32-bit word

3.51. rx payload reg22

HW prefix:	mrfip_rx_payld_reg22
HW address:	0x32
C prefix:	RX_PAYLD_REG22
C offset:	0xc8

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG22[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG22[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG22[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG22[7:0]

RX_PAYLD_REG22 [read-only]: reg22
22th 32-bit word

3.52. rx payload reg23

HW prefix:	mrfip_rx_payld_reg23
HW address:	0x33
C prefix:	RX_PAYLD_REG23
C offset:	0xcc

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG23[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG23[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG23[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG23[7:0]

RX_PAYLD_REG23 [read-only]: reg23
23th 32-bit word

3.53. rx payload reg24

HW prefix:	mrfip_rx_payld_reg24
HW address:	0x34
C prefix:	RX_PAYLD_REG24
C offset:	0xd0

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG24[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG24[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG24[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG24[7:0]

RX_PAYLD_REG24 [read-only]: reg24
24th 32-bit word

3.54. rx payload reg25

HW prefix:	mrfip_rx_payld_reg25
HW address:	0x35
C prefix:	RX_PAYLD_REG25
C offset:	0xd4

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG25[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG25[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG25[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG25[7:0]

RX_PAYLD_REG25 [read-only]: reg25
25th 32-bit word

3.55. rx payload reg26

HW prefix:	mrfip_rx_payld_reg26
HW address:	0x36
C prefix:	RX_PAYLD_REG26
C offset:	0xd8

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG26[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG26[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG26[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG26[7:0]

RX_PAYLD_REG26 [read-only]: reg26
26th 32-bit word

3.56. rx payload reg27

HW prefix:	mrfip_rx_payld_reg27
HW address:	0x37
C prefix:	RX_PAYLD_REG27
C offset:	0xdc

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG27[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG27[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG27[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG27[7:0]

RX_PAYLD_REG27 [read-only]: reg27
27th 32-bit word

3.57. rx payload reg28

HW prefix:	mrfip_rx_payld_reg28
HW address:	0x38
C prefix:	RX_PAYLD_REG28
C offset:	0xe0

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG28[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG28[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG28[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG28[7:0]

RX_PAYLD_REG28 [read-only]: reg28
28th 32-bit word

3.58. rx payload reg29

HW prefix:	mrfip_rx_payld_reg29
HW address:	0x39
C prefix:	RX_PAYLD_REG29
C offset:	0xe4

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG29[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG29[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG29[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG29[7:0]

RX_PAYLD_REG29 [read-only]: reg29
29th 32-bit word

3.59. rx payload reg30

HW prefix:	mrfip_rx_payld_reg30
HW address:	0x3a
C prefix:	RX_PAYLD_REG30
C offset:	0xe8

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG30[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG30[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG30[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG30[7:0]

RX_PAYLD_REG30 [read-only]: reg30
30th 32-bit word

3.60. rx payload reg31

HW prefix:	mrfip_rx_payld_reg31
HW address:	0x3b
C prefix:	RX_PAYLD_REG31
C offset:	0xec

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG31[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG31[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG31[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG31[7:0]

RX_PAYLD_REG31 [read-only]: reg31
31th 32-bit word

3.61. rx payload reg32

HW prefix:	mrfip_rx_payld_reg32
HW address:	0x3c
C prefix:	RX_PAYLD_REG32
C offset:	0xf0

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG32[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG32[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG32[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG32[7:0]

RX_PAYLD_REG32 [read-only]: reg32
32th 32-bit word

3.62. rx payload reg33

HW prefix:	mrfip_rx_payld_reg33
HW address:	0x3d
C prefix:	RX_PAYLD_REG33
C offset:	0xf4

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG33[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG33[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG33[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG33[7:0]

RX_PAYLD_REG33 [read-only]: reg 33
33rd 32-bit word

3.63. rx payload reg34

HW prefix:	mrfip_rx_payld_reg34
HW address:	0x3e
C prefix:	RX_PAYLD_REG34
C offset:	0xf8

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG34[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG34[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG34[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG34[7:0]

RX_PAYLD_REG34 [read-only]: reg34
34th 32-bit word

3.64. rx payload reg35

HW prefix:	mrfip_rx_payld_reg35
HW address:	0x3f
C prefix:	RX_PAYLD_REG35
C offset:	0xfc

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG35[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG35[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG35[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG35[7:0]

RX_PAYLD_REG35 [read-only]: reg35
35th 32-bit word

3.65. rx payload reg36

HW prefix:	mrfip_rx_payld_reg36
HW address:	0x40
C prefix:	RX_PAYLD_REG36
C offset:	0x100

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG36[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG36[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG36[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG36[7:0]

RX_PAYLD_REG36 [read-only]: reg36
36th 32-bit word

3.66. rx payload reg37

HW prefix:	mrfip_rx_payld_reg37
HW address:	0x41
C prefix:	RX_PAYLD_REG37
C offset:	0x104

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG37[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG37[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG37[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG37[7:0]

RX_PAYLD_REG37 [read-only]: reg37
37th 32-bit word

3.67. rx payload reg38

HW prefix:	mrfip_rx_payld_reg38
HW address:	0x42
C prefix:	RX_PAYLD_REG38
C offset:	0x108

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG38[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG38[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG38[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG38[7:0]

RX_PAYLD_REG38 [read-only]: reg38
38th 32-bit word

3.68. rx payload reg39

HW prefix:	mrfip_rx_payld_reg39
HW address:	0x43
C prefix:	RX_PAYLD_REG39
C offset:	0x10c

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG39[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG39[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG39[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG39[7:0]

RX_PAYLD_REG39 [read-only]: reg39
39th 32-bit word

3.69. rx payload reg40

HW prefix:	mrfip_rx_payld_reg40
HW address:	0x44
C prefix:	RX_PAYLD_REG40
C offset:	0x110

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG40[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG40[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG40[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG40[7:0]

RX_PAYLD_REG40 [read-only]: reg40
40th 32-bit word

3.70. rx payload reg41

HW prefix:	mrfip_rx_payld_reg41
HW address:	0x45
C prefix:	RX_PAYLD_REG41
C offset:	0x114

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG41[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG41[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG41[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG41[7:0]

RX_PAYLD_REG41 [read-only]: reg41
41th 32-bit word

3.71. rx payload reg42

HW prefix:	mrfip_rx_payld_reg42
HW address:	0x46
C prefix:	RX_PAYLD_REG42
C offset:	0x118

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG42[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG42[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG42[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG42[7:0]

RX_PAYLD_REG42 [read-only]: reg42
42nd 32-bit word

3.72. rx payload reg43

HW prefix:	mrfip_rx_payld_reg43
HW address:	0x47
C prefix:	RX_PAYLD_REG43
C offset:	0x11c

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG43[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG43[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG43[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG43[7:0]

RX_PAYLD_REG43 [read-only]: reg43
43rd 32-bit word

3.73. rx payload reg44

HW prefix:	mrfip_rx_payld_reg44
HW address:	0x48
C prefix:	RX_PAYLD_REG44
C offset:	0x120

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG44[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG44[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG44[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG44[7:0]

RX_PAYLD_REG44 [read-only]: reg44
44th 32-bit word

3.74. rx payload reg45

HW prefix:	mrfip_rx_payld_reg45
HW address:	0x49
C prefix:	RX_PAYLD_REG45
C offset:	0x124

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG45[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG45[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG45[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG45[7:0]

RX_PAYLD_REG45 [read-only]: reg45
45th 32-bit word

3.75. rx payload reg46

HW prefix:	mrfip_rx_payld_reg46
HW address:	0x4a
C prefix:	RX_PAYLD_REG46
C offset:	0x128

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG46[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG46[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG46[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG46[7:0]

RX_PAYLD_REG46 [read-only]: reg46
46th 32-bit word

3.76. rx payload reg47

HW prefix:	mrfip_rx_payld_reg47
HW address:	0x4b
C prefix:	RX_PAYLD_REG47
C offset:	0x12c

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG47[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG47[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG47[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG47[7:0]

RX_PAYLD_REG47 [read-only]: reg47
47th 32-bit word

3.77. rx payload reg48

HW prefix:	mrfip_rx_payld_reg48
HW address:	0x4c
C prefix:	RX_PAYLD_REG48
C offset:	0x130

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG48[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG48[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG48[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG48[7:0]

RX_PAYLD_REG48 [read-only]: reg48
48th 32-bit word

3.78. rx payload reg49

HW prefix:	mrfip_rx_payld_reg49
HW address:	0x4d
C prefix:	RX_PAYLD_REG49
C offset:	0x134

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG49[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG49[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG49[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG49[7:0]

RX_PAYLD_REG49 [read-only]: reg49
49th 32-bit word

3.79. rx payload reg50

HW prefix:	mrfip_rx_payld_reg50
HW address:	0x4e
C prefix:	RX_PAYLD_REG50
C offset:	0x138

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG50[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG50[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG50[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG50[7:0]

RX_PAYLD_REG50 [read-only]: reg50
50th 32-bit word

3.80. rx payload reg51

HW prefix:	mrfip_rx_payld_reg51
HW address:	0x4f
C prefix:	RX_PAYLD_REG51
C offset:	0x13c

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG51[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG51[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG51[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG51[7:0]

RX_PAYLD_REG51 [read-only]: reg51
51st 32-bit word

3.81. rx payload reg52

HW prefix:	mrfip_rx_payld_reg52
HW address:	0x50
C prefix:	RX_PAYLD_REG52
C offset:	0x140

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG52[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG52[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG52[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG52[7:0]

RX_PAYLD_REG52 [read-only]: reg52
52nd 32-bit word

3.82. rx payload reg53

HW prefix:	mrfip_rx_payld_reg53
HW address:	0x51
C prefix:	RX_PAYLD_REG53
C offset:	0x144

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG53[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG53[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG53[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG53[7:0]

RX_PAYLD_REG53 [read-only]: reg53
53rd 32-bit word

3.83. rx payload reg54

HW prefix:	mrfip_rx_payld_reg54
HW address:	0x52
C prefix:	RX_PAYLD_REG54
C offset:	0x148

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG54[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG54[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG54[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG54[7:0]

RX_PAYLD_REG54 [read-only]: reg54
54th 32-bit word

3.84. rx payload reg55

HW prefix:	mrfip_rx_payld_reg55
HW address:	0x53
C prefix:	RX_PAYLD_REG55
C offset:	0x14c

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG55[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG55[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG55[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG55[7:0]

RX_PAYLD_REG55 [read-only]: reg55
55th 32-bit word

3.85. rx payload reg56

HW prefix:	mrfip_rx_payld_reg56
HW address:	0x54
C prefix:	RX_PAYLD_REG56
C offset:	0x150

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG56[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG56[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG56[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG56[7:0]

RX_PAYLD_REG56 [read-only]: reg56
56th 32-bit word

3.86. rx payload reg57

HW prefix:	mrfip_rx_payld_reg57
HW address:	0x55
C prefix:	RX_PAYLD_REG57
C offset:	0x154

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG57[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG57[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG57[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG57[7:0]

RX_PAYLD_REG57 [read-only]: reg57
57th 32-bit word

3.87. rx payload reg58

HW prefix:	mrfip_rx_payld_reg58
HW address:	0x56
C prefix:	RX_PAYLD_REG58
C offset:	0x158

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG58[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG58[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG58[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG58[7:0]

RX_PAYLD_REG58 [read-only]: reg58
58th 32-bit word

3.88. rx payload reg59

HW prefix:	mrfip_rx_payld_reg59
HW address:	0x57
C prefix:	RX_PAYLD_REG59
C offset:	0x15c

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG59[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG59[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG59[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG59[7:0]

RX_PAYLD_REG59 [read-only]: reg59
59th 32-bit word

3.89. rx payload reg60

HW prefix:	mrfip_rx_payld_reg60
HW address:	0x58
C prefix:	RX_PAYLD_REG60
C offset:	0x160

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG60[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG60[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG60[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG60[7:0]

RX_PAYLD_REG60 [read-only]: reg60
60th 32-bit word

3.90. rx payload reg61

HW prefix:	mrfip_rx_payld_reg61
HW address:	0x59
C prefix:	RX_PAYLD_REG61
C offset:	0x164

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG61[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG61[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG61[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG61[7:0]

RX_PAYLD_REG61 [read-only]: reg61
61st 32-bit word

3.91. rx payload reg62

HW prefix:	mrfip_rx_payld_reg62
HW address:	0x5a
C prefix:	RX_PAYLD_REG62
C offset:	0x168

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG62[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG62[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG62[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG62[7:0]

RX_PAYLD_REG62 [read-only]: reg62
62nd 32-bit word

3.92. rx payload reg63

HW prefix:	mrfip_rx_payld_reg63
HW address:	0x5b
C prefix:	RX_PAYLD_REG63
C offset:	0x16c

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG63[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG63[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG63[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG63[7:0]

RX_PAYLD_REG63 [read-only]: reg63
63rd 32-bit word

3.93. rx payload reg64

HW prefix:	mrfip_rx_payld_reg64
HW address:	0x5c
C prefix:	RX_PAYLD_REG64
C offset:	0x170

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG64[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG64[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG64[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG64[7:0]

RX_PAYLD_REG64 [read-only]: reg64
64th 32-bit word

3.94. rx payload reg65

HW prefix:	mrfip_rx_payld_reg65
HW address:	0x5d
C prefix:	RX_PAYLD_REG65
C offset:	0x174

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG65[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG65[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG65[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG65[7:0]

RX_PAYLD_REG65 [read-only]: reg65
65th 32-bit word

3.95. rx payload reg66

HW prefix:	mrfip_rx_payld_reg66
HW address:	0x5e
C prefix:	RX_PAYLD_REG66
C offset:	0x178

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG66[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG66[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG66[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG66[7:0]

RX_PAYLD_REG66 [read-only]: reg66
66th 32-bit word

3.96. rx payload reg67

HW prefix:	mrfip_rx_payld_reg67
HW address:	0x5f
C prefix:	RX_PAYLD_REG67
C offset:	0x17c

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_PAYLD_REG67[31:24]

23	22	21	20	19	18	17	16
RX_PAYLD_REG67[23:16]

15	14	13	12	11	10	9	8
RX_PAYLD_REG67[15:8]

7	6	5	4	3	2	1	0
RX_PAYLD_REG67[7:0]

RX_PAYLD_REG67 [read-only]: reg67
67th 32-bit word

3.97. tx ctrl byte

HW prefix:	mrfip_tx_payld_ctrl
HW address:	0x60
C prefix:	TX_PAYLD_CTRL
C offset:	0x180

contains the 8-bits of the control field of a frame to transmit

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-

7	6	5	4	3	2	1	0
TX_PAYLD_CTRL[7:0]

TX_PAYLD_CTRL [read/write]: tx ctrl byte
contains the 8-bits of the control field of a frame to transmit

3.98. tx payload reg1

HW prefix:	mrfip_tx_payld_reg1
HW address:	0x61
C prefix:	TX_PAYLD_REG1
C offset:	0x184

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG1[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG1[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG1[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG1[7:0]

TX_PAYLD_REG1 [read/write]: reg1
1st 32-bit word

3.99. tx payload reg2

HW prefix:	mrfip_tx_payld_reg2
HW address:	0x62
C prefix:	TX_PAYLD_REG2
C offset:	0x188

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG2[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG2[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG2[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG2[7:0]

TX_PAYLD_REG2 [read/write]: reg2
2nd 32-bit word

3.100. tx payload reg3

HW prefix:	mrfip_tx_payld_reg3
HW address:	0x63
C prefix:	TX_PAYLD_REG3
C offset:	0x18c

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG3[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG3[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG3[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG3[7:0]

TX_PAYLD_REG3 [read/write]: reg3
3rd 32-bit word

3.101. tx payload reg4

HW prefix:	mrfip_tx_payld_reg4
HW address:	0x64
C prefix:	TX_PAYLD_REG4
C offset:	0x190

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG4[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG4[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG4[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG4[7:0]

TX_PAYLD_REG4 [read/write]: reg4
4th 32-bit word

3.102. tx payload reg5

HW prefix:	mrfip_tx_payld_reg5
HW address:	0x65
C prefix:	TX_PAYLD_REG5
C offset:	0x194

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG5[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG5[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG5[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG5[7:0]

TX_PAYLD_REG5 [read/write]: reg5
5th 32-bit word

3.103. tx payload reg6

HW prefix:	mrfip_tx_payld_reg6
HW address:	0x66
C prefix:	TX_PAYLD_REG6
C offset:	0x198

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG6[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG6[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG6[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG6[7:0]

TX_PAYLD_REG6 [read/write]: reg6
6th 32-bit word

3.104. tx payload reg7

HW prefix:	mrfip_tx_payld_reg7
HW address:	0x67
C prefix:	TX_PAYLD_REG7
C offset:	0x19c

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG7[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG7[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG7[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG7[7:0]

TX_PAYLD_REG7 [read/write]: reg7
7th 32-bit word

3.105. tx payload reg8

HW prefix:	mrfip_tx_payld_reg8
HW address:	0x68
C prefix:	TX_PAYLD_REG8
C offset:	0x1a0

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG8[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG8[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG8[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG8[7:0]

TX_PAYLD_REG8 [read/write]: reg8
8th 32-bit word

3.106. tx payload reg9

HW prefix:	mrfip_tx_payld_reg9
HW address:	0x69
C prefix:	TX_PAYLD_REG9
C offset:	0x1a4

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG9[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG9[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG9[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG9[7:0]

TX_PAYLD_REG9 [read/write]: reg9
9th 32-bit word

3.107. tx payload reg10

HW prefix:	mrfip_tx_payld_reg10
HW address:	0x6a
C prefix:	TX_PAYLD_REG10
C offset:	0x1a8

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG10[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG10[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG10[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG10[7:0]

TX_PAYLD_REG10 [read/write]: reg10
10th 32-bit word

3.108. tx payload reg11

HW prefix:	mrfip_tx_payld_reg11
HW address:	0x6b
C prefix:	TX_PAYLD_REG11
C offset:	0x1ac

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG11[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG11[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG11[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG11[7:0]

TX_PAYLD_REG11 [read/write]: reg11
11th 32-bit word

3.109. tx payload reg12

HW prefix:	mrfip_tx_payld_reg12
HW address:	0x6c
C prefix:	TX_PAYLD_REG12
C offset:	0x1b0

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG12[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG12[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG12[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG12[7:0]

TX_PAYLD_REG12 [read/write]: reg12
12th 32-bit word

3.110. tx payload reg13

HW prefix:	mrfip_tx_payld_reg13
HW address:	0x6d
C prefix:	TX_PAYLD_REG13
C offset:	0x1b4

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG13[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG13[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG13[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG13[7:0]

TX_PAYLD_REG13 [read/write]: reg13
13th 32-bit word

3.111. tx payload reg14

HW prefix:	mrfip_tx_payld_reg14
HW address:	0x6e
C prefix:	TX_PAYLD_REG14
C offset:	0x1b8

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG14[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG14[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG14[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG14[7:0]

TX_PAYLD_REG14 [read/write]: reg14
14th 32-bit word

3.112. tx payload reg15

HW prefix:	mrfip_tx_payld_reg15
HW address:	0x6f
C prefix:	TX_PAYLD_REG15
C offset:	0x1bc

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG15[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG15[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG15[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG15[7:0]

TX_PAYLD_REG15 [read/write]: reg15
15th 32-bit word

3.113. tx payload reg16

HW prefix:	mrfip_tx_payld_reg16
HW address:	0x70
C prefix:	TX_PAYLD_REG16
C offset:	0x1c0

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG16[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG16[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG16[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG16[7:0]

TX_PAYLD_REG16 [read/write]: reg16
16th 32-bit word

3.114. tx payload reg17

HW prefix:	mrfip_tx_payld_reg17
HW address:	0x71
C prefix:	TX_PAYLD_REG17
C offset:	0x1c4

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG17[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG17[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG17[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG17[7:0]

TX_PAYLD_REG17 [read/write]: reg17
17th 32-bit word

3.115. tx payload reg18

HW prefix:	mrfip_tx_payld_reg18
HW address:	0x72
C prefix:	TX_PAYLD_REG18
C offset:	0x1c8

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG18[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG18[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG18[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG18[7:0]

TX_PAYLD_REG18 [read/write]: reg18
18th 32-bit word

3.116. tx payload reg19

HW prefix:	mrfip_tx_payld_reg19
HW address:	0x73
C prefix:	TX_PAYLD_REG19
C offset:	0x1cc

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG19[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG19[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG19[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG19[7:0]

TX_PAYLD_REG19 [read/write]: reg19
19th 32-bit word

3.117. tx payload reg20

HW prefix:	mrfip_tx_payld_reg20
HW address:	0x74
C prefix:	TX_PAYLD_REG20
C offset:	0x1d0

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG20[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG20[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG20[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG20[7:0]

TX_PAYLD_REG20 [read/write]: reg20
20th 32-bit word

3.118. tx payload reg21

HW prefix:	mrfip_tx_payld_reg21
HW address:	0x75
C prefix:	TX_PAYLD_REG21
C offset:	0x1d4

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG21[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG21[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG21[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG21[7:0]

TX_PAYLD_REG21 [read/write]: reg21
21th 32-bit word

3.119. tx payload reg22

HW prefix:	mrfip_tx_payld_reg22
HW address:	0x76
C prefix:	TX_PAYLD_REG22
C offset:	0x1d8

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG22[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG22[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG22[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG22[7:0]

TX_PAYLD_REG22 [read/write]: reg22
22th 32-bit word

3.120. tx payload reg23

HW prefix:	mrfip_tx_payld_reg23
HW address:	0x77
C prefix:	TX_PAYLD_REG23
C offset:	0x1dc

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG23[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG23[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG23[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG23[7:0]

TX_PAYLD_REG23 [read/write]: reg23
23th 32-bit word

3.121. tx payload reg24

HW prefix:	mrfip_tx_payld_reg24
HW address:	0x78
C prefix:	TX_PAYLD_REG24
C offset:	0x1e0

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG24[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG24[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG24[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG24[7:0]

TX_PAYLD_REG24 [read/write]: reg24
24th 32-bit word

3.122. tx payload reg25

HW prefix:	mrfip_tx_payld_reg25
HW address:	0x79
C prefix:	TX_PAYLD_REG25
C offset:	0x1e4

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG25[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG25[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG25[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG25[7:0]

TX_PAYLD_REG25 [read/write]: reg25
25th 32-bit word

3.123. tx payload reg26

HW prefix:	mrfip_tx_payld_reg26
HW address:	0x7a
C prefix:	TX_PAYLD_REG26
C offset:	0x1e8

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG26[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG26[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG26[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG26[7:0]

TX_PAYLD_REG26 [read/write]: reg26
26th 32-bit word

3.124. tx payload reg27

HW prefix:	mrfip_tx_payld_reg27
HW address:	0x7b
C prefix:	TX_PAYLD_REG27
C offset:	0x1ec

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG27[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG27[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG27[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG27[7:0]

TX_PAYLD_REG27 [read/write]: reg27
27th 32-bit word

3.125. tx payload reg28

HW prefix:	mrfip_tx_payld_reg28
HW address:	0x7c
C prefix:	TX_PAYLD_REG28
C offset:	0x1f0

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG28[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG28[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG28[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG28[7:0]

TX_PAYLD_REG28 [read/write]: reg28
28th 32-bit word

3.126. tx payload reg29

HW prefix:	mrfip_tx_payld_reg29
HW address:	0x7d
C prefix:	TX_PAYLD_REG29
C offset:	0x1f4

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG29[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG29[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG29[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG29[7:0]

TX_PAYLD_REG29 [read/write]: reg29
29th 32-bit word

3.127. tx payload reg30

HW prefix:	mrfip_tx_payld_reg30
HW address:	0x7e
C prefix:	TX_PAYLD_REG30
C offset:	0x1f8

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG30[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG30[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG30[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG30[7:0]

TX_PAYLD_REG30 [read/write]: reg30
30th 32-bit word

3.128. tx payload reg31

HW prefix:	mrfip_tx_payld_reg31
HW address:	0x7f
C prefix:	TX_PAYLD_REG31
C offset:	0x1fc

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG31[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG31[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG31[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG31[7:0]

TX_PAYLD_REG31 [read/write]: reg31
31th 32-bit word

3.129. tx payload reg32

HW prefix:	mrfip_tx_payld_reg32
HW address:	0x80
C prefix:	TX_PAYLD_REG32
C offset:	0x200

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG32[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG32[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG32[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG32[7:0]

TX_PAYLD_REG32 [read/write]: reg32
32th 32-bit word

3.130. tx payload reg33

HW prefix:	mrfip_tx_payld_reg33
HW address:	0x81
C prefix:	TX_PAYLD_REG33
C offset:	0x204

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG33[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG33[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG33[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG33[7:0]

TX_PAYLD_REG33 [read/write]: reg 33
33rd 32-bit word

3.131. tx payload reg34

HW prefix:	mrfip_tx_payld_reg34
HW address:	0x82
C prefix:	TX_PAYLD_REG34
C offset:	0x208

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG34[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG34[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG34[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG34[7:0]

TX_PAYLD_REG34 [read/write]: reg34
34th 32-bit word

3.132. tx payload reg35

HW prefix:	mrfip_tx_payld_reg35
HW address:	0x83
C prefix:	TX_PAYLD_REG35
C offset:	0x20c

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG35[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG35[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG35[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG35[7:0]

TX_PAYLD_REG35 [read/write]: reg35
35th 32-bit word

3.133. tx payload reg36

HW prefix:	mrfip_tx_payld_reg36
HW address:	0x84
C prefix:	TX_PAYLD_REG36
C offset:	0x210

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG36[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG36[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG36[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG36[7:0]

TX_PAYLD_REG36 [read/write]: reg36
36th 32-bit word

3.134. tx payload reg37

HW prefix:	mrfip_tx_payld_reg37
HW address:	0x85
C prefix:	TX_PAYLD_REG37
C offset:	0x214

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG37[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG37[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG37[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG37[7:0]

TX_PAYLD_REG37 [read/write]: reg37
37th 32-bit word

3.135. tx payload reg38

HW prefix:	mrfip_tx_payld_reg38
HW address:	0x86
C prefix:	TX_PAYLD_REG38
C offset:	0x218

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG38[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG38[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG38[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG38[7:0]

TX_PAYLD_REG38 [read/write]: reg38
38th 32-bit word

3.136. tx payload reg39

HW prefix:	mrfip_tx_payld_reg39
HW address:	0x87
C prefix:	TX_PAYLD_REG39
C offset:	0x21c

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG39[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG39[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG39[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG39[7:0]

TX_PAYLD_REG39 [read/write]: reg39
39th 32-bit word

3.137. tx payload reg40

HW prefix:	mrfip_tx_payld_reg40
HW address:	0x88
C prefix:	TX_PAYLD_REG40
C offset:	0x220

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG40[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG40[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG40[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG40[7:0]

TX_PAYLD_REG40 [read/write]: reg40
40th 32-bit word

3.138. tx payload reg41

HW prefix:	mrfip_tx_payld_reg41
HW address:	0x89
C prefix:	TX_PAYLD_REG41
C offset:	0x224

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG41[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG41[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG41[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG41[7:0]

TX_PAYLD_REG41 [read/write]: reg41
41th 32-bit word

3.139. tx payload reg42

HW prefix:	mrfip_tx_payld_reg42
HW address:	0x8a
C prefix:	TX_PAYLD_REG42
C offset:	0x228

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG42[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG42[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG42[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG42[7:0]

TX_PAYLD_REG42 [read/write]: reg42
42nd 32-bit word

3.140. tx payload reg43

HW prefix:	mrfip_tx_payld_reg43
HW address:	0x8b
C prefix:	TX_PAYLD_REG43
C offset:	0x22c

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG43[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG43[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG43[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG43[7:0]

TX_PAYLD_REG43 [read/write]: reg43
43rd 32-bit word

3.141. tx payload reg44

HW prefix:	mrfip_tx_payld_reg44
HW address:	0x8c
C prefix:	TX_PAYLD_REG44
C offset:	0x230

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG44[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG44[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG44[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG44[7:0]

TX_PAYLD_REG44 [read/write]: reg44
44th 32-bit word

3.142. tx payload reg45

HW prefix:	mrfip_tx_payld_reg45
HW address:	0x8d
C prefix:	TX_PAYLD_REG45
C offset:	0x234

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG45[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG45[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG45[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG45[7:0]

TX_PAYLD_REG45 [read/write]: reg45
45th 32-bit word

3.143. tx payload reg46

HW prefix:	mrfip_tx_payld_reg46
HW address:	0x8e
C prefix:	TX_PAYLD_REG46
C offset:	0x238

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG46[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG46[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG46[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG46[7:0]

TX_PAYLD_REG46 [read/write]: reg46
46th 32-bit word

3.144. tx payload reg47

HW prefix:	mrfip_tx_payld_reg47
HW address:	0x8f
C prefix:	TX_PAYLD_REG47
C offset:	0x23c

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG47[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG47[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG47[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG47[7:0]

TX_PAYLD_REG47 [read/write]: reg47
47th 32-bit word

3.145. tx payload reg48

HW prefix:	mrfip_tx_payld_reg48
HW address:	0x90
C prefix:	TX_PAYLD_REG48
C offset:	0x240

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG48[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG48[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG48[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG48[7:0]

TX_PAYLD_REG48 [read/write]: reg48
48th 32-bit word

3.146. tx payload reg49

HW prefix:	mrfip_tx_payld_reg49
HW address:	0x91
C prefix:	TX_PAYLD_REG49
C offset:	0x244

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG49[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG49[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG49[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG49[7:0]

TX_PAYLD_REG49 [read/write]: reg49
49th 32-bit word

3.147. tx payload reg50

HW prefix:	mrfip_tx_payld_reg50
HW address:	0x92
C prefix:	TX_PAYLD_REG50
C offset:	0x248

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG50[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG50[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG50[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG50[7:0]

TX_PAYLD_REG50 [read/write]: reg50
50th 32-bit word

3.148. tx payload reg51

HW prefix:	mrfip_tx_payld_reg51
HW address:	0x93
C prefix:	TX_PAYLD_REG51
C offset:	0x24c

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG51[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG51[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG51[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG51[7:0]

TX_PAYLD_REG51 [read/write]: reg51
51st 32-bit word

3.149. tx payload reg52

HW prefix:	mrfip_tx_payld_reg52
HW address:	0x94
C prefix:	TX_PAYLD_REG52
C offset:	0x250

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG52[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG52[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG52[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG52[7:0]

TX_PAYLD_REG52 [read/write]: reg52
52nd 32-bit word

3.150. tx payload reg53

HW prefix:	mrfip_tx_payld_reg53
HW address:	0x95
C prefix:	TX_PAYLD_REG53
C offset:	0x254

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG53[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG53[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG53[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG53[7:0]

TX_PAYLD_REG53 [read/write]: reg53
53rd 32-bit word

3.151. tx payload reg54

HW prefix:	mrfip_tx_payld_reg54
HW address:	0x96
C prefix:	TX_PAYLD_REG54
C offset:	0x258

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG54[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG54[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG54[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG54[7:0]

TX_PAYLD_REG54 [read/write]: reg54
54th 32-bit word

3.152. tx payload reg55

HW prefix:	mrfip_tx_payld_reg55
HW address:	0x97
C prefix:	TX_PAYLD_REG55
C offset:	0x25c

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG55[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG55[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG55[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG55[7:0]

TX_PAYLD_REG55 [read/write]: reg55
55th 32-bit word

3.153. tx payload reg56

HW prefix:	mrfip_tx_payld_reg56
HW address:	0x98
C prefix:	TX_PAYLD_REG56
C offset:	0x260

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG56[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG56[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG56[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG56[7:0]

TX_PAYLD_REG56 [read/write]: reg56
56th 32-bit word

3.154. tx payload reg57

HW prefix:	mrfip_tx_payld_reg57
HW address:	0x99
C prefix:	TX_PAYLD_REG57
C offset:	0x264

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG57[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG57[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG57[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG57[7:0]

TX_PAYLD_REG57 [read/write]: reg57
57th 32-bit word

3.155. tx payload reg58

HW prefix:	mrfip_tx_payld_reg58
HW address:	0x9a
C prefix:	TX_PAYLD_REG58
C offset:	0x268

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG58[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG58[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG58[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG58[7:0]

TX_PAYLD_REG58 [read/write]: reg58
58th 32-bit word

3.156. tx payload reg59

HW prefix:	mrfip_tx_payld_reg59
HW address:	0x9b
C prefix:	TX_PAYLD_REG59
C offset:	0x26c

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG59[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG59[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG59[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG59[7:0]

TX_PAYLD_REG59 [read/write]: reg59
59th 32-bit word

3.157. tx payload reg60

HW prefix:	mrfip_tx_payld_reg60
HW address:	0x9c
C prefix:	TX_PAYLD_REG60
C offset:	0x270

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG60[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG60[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG60[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG60[7:0]

TX_PAYLD_REG60 [read/write]: reg60
60th 32-bit word

3.158. tx payload reg61

HW prefix:	mrfip_tx_payld_reg61
HW address:	0x9d
C prefix:	TX_PAYLD_REG61
C offset:	0x274

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG61[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG61[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG61[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG61[7:0]

TX_PAYLD_REG61 [read/write]: reg61
61st 32-bit word

3.159. tx payload reg62

HW prefix:	mrfip_tx_payld_reg62
HW address:	0x9e
C prefix:	TX_PAYLD_REG62
C offset:	0x278

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG62[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG62[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG62[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG62[7:0]

TX_PAYLD_REG62 [read/write]: reg62
62nd 32-bit word

3.160. tx payload reg63

HW prefix:	mrfip_tx_payld_reg63
HW address:	0x9f
C prefix:	TX_PAYLD_REG63
C offset:	0x27c

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG63[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG63[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG63[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG63[7:0]

TX_PAYLD_REG63 [read/write]: reg63
63rd 32-bit word

3.161. tx payload reg64

HW prefix:	mrfip_tx_payld_reg64
HW address:	0xa0
C prefix:	TX_PAYLD_REG64
C offset:	0x280

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG64[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG64[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG64[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG64[7:0]

TX_PAYLD_REG64 [read/write]: reg64
64th 32-bit word

3.162. tx payload reg65

HW prefix:	mrfip_tx_payld_reg65
HW address:	0xa1
C prefix:	TX_PAYLD_REG65
C offset:	0x284

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG65[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG65[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG65[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG65[7:0]

TX_PAYLD_REG65 [read/write]: reg65
65th 32-bit word

3.163. tx payload reg66

HW prefix:	mrfip_tx_payld_reg66
HW address:	0xa2
C prefix:	TX_PAYLD_REG66
C offset:	0x288

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG66[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG66[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG66[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG66[7:0]

TX_PAYLD_REG66 [read/write]: reg66
66th 32-bit word

3.164. tx payload reg67

HW prefix:	mrfip_tx_payld_reg67
HW address:	0xa3
C prefix:	TX_PAYLD_REG67
C offset:	0x28c

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_PAYLD_REG67[31:24]

23	22	21	20	19	18	17	16
TX_PAYLD_REG67[23:16]

15	14	13	12	11	10	9	8
TX_PAYLD_REG67[15:8]

7	6	5	4	3	2	1	0
TX_PAYLD_REG67[7:0]

TX_PAYLD_REG67 [read/write]: reg67
67th 32-bit word

fmc_masterfip_csr

FMC masterFIP core registers

Contents: