Some documentation changes

Changed Slow control shift register to have optional reset before shifting data.
( Still at least one bug - doesn't store data shifted out of MAROC correctly )

Added register stages to risingEdgeDetect




git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@35 e1591323-3689-4d5a-aa31-d1a7cbdc5706

git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@34 e1591323-3689-4d5a-aa31-d1a7cbdc5706

* marocInterface_rtl.vhd - detects the falling edge of status from marocADC
* circuit to detect falling edge of status hdl/fallingEdgeDetect_rtl.vhd



git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@33 e1591323-3689-4d5a-aa31-d1a7cbdc5706

git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@32 e1591323-3689-4d5a-aa31-d1a7cbdc5706

git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@31 e1591323-3689-4d5a-aa31-d1a7cbdc5706

Edited pc049a_top.vhd in order to only build the IPBus ( not the White Rabbit ) cores by default. Reduces power dissipation and keeps chip cooler.



git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@30 e1591323-3689-4d5a-aa31-d1a7cbdc5706

* Took pictures of assembled boards.

* Exported netlist from Circuit schematic.

* Changed clocks to be 31.25MHz IPBus clock.

* General tidying. Unfortunately, latest design doesn't respond to "ping"....



git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@29 e1591323-3689-4d5a-aa31-d1a7cbdc5706

git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@27 e1591323-3689-4d5a-aa31-d1a7cbdc5706

git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@26 e1591323-3689-4d5a-aa31-d1a7cbdc5706

git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@25 e1591323-3689-4d5a-aa31-d1a7cbdc5706

git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@24 e1591323-3689-4d5a-aa31-d1a7cbdc5706

git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@23 e1591323-3689-4d5a-aa31-d1a7cbdc5706

Changing clearanges to get ground pins on DIN connectors connected to ground planes on layers 7 , 10

git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@22 e1591323-3689-4d5a-aa31-d1a7cbdc5706

git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@21 e1591323-3689-4d5a-aa31-d1a7cbdc5706

git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@20 e1591323-3689-4d5a-aa31-d1a7cbdc5706

git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@19 e1591323-3689-4d5a-aa31-d1a7cbdc5706

git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@18 e1591323-3689-4d5a-aa31-d1a7cbdc5706

git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@17 e1591323-3689-4d5a-aa31-d1a7cbdc5706

git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@16 e1591323-3689-4d5a-aa31-d1a7cbdc5706

git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@15 e1591323-3689-4d5a-aa31-d1a7cbdc5706

git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@14 e1591323-3689-4d5a-aa31-d1a7cbdc5706

* Started to construct top level schematic

* Added some block diagrams




git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@13 e1591323-3689-4d5a-aa31-d1a7cbdc5706

git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@12 e1591323-3689-4d5a-aa31-d1a7cbdc5706

git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@11 e1591323-3689-4d5a-aa31-d1a7cbdc5706

git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@10 e1591323-3689-4d5a-aa31-d1a7cbdc5706

git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@9 e1591323-3689-4d5a-aa31-d1a7cbdc5706

git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@8 e1591323-3689-4d5a-aa31-d1a7cbdc5706

git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@7 e1591323-3689-4d5a-aa31-d1a7cbdc5706

git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@2 e1591323-3689-4d5a-aa31-d1a7cbdc5706