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Scalable MAROC Charge Sensitive Readout
Commit b31f50a2 authored by David Cussans's avatar David Cussans
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Comissioning boards.

* Took pictures of assembled boards.

* Exported netlist from Circuit schematic.

* Changed clocks to be 31.25MHz IPBus clock.

* General tidying. Unfortunately, latest design doesn't respond to "ping"....



git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@29 e1591323-3689-4d5a-aa31-d1a7cbdc5706
parent dfeb5646
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Showing with 357 additions and 413 deletions
design_files/pc049a_toplevel.cpm
View file @ b31f50a2
{ Machine generated file created by SPI } { Machine generated file created by SPI }
{ Last modified was 12:29:39 Monday, February 23, 2015 } { Last modified was 15:08:38 Monday, March 23, 2015 }
{ NOTE: Do not modify the contents of this file. If this is regenerated by } { NOTE: Do not modify the contents of this file. If this is regenerated by }
{ SPI, your modifications will be overwritten. } { SPI, your modifications will be overwritten. }
......
design_files/worklib/pc049a_toplevel/packaged/dialbonl.dat
View file @ b31f50a2
...@@ -8,7 +8,7 @@ C2 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL ...@@ -8,7 +8,7 @@ C2 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL
C2_1 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL C2_1 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL
2 VDDD2_1 2 VDDD2_1
C3 CAPCERSMDCL2_0402-1UF,16V 1 GND_SIGNAL C3 CAPCERSMDCL2_0402-1UF,16V 1 GND_SIGNAL
2 AVDD 2 P3V3
C3_1 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL C3_1 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL
2 VDD_DAC_1 2 VDD_DAC_1
C4 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL C4 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL
...@@ -312,25 +312,25 @@ C103 CAPCERSMDCL2_0603-100NF,16V 1 P2V5 ...@@ -312,25 +312,25 @@ C103 CAPCERSMDCL2_0603-100NF,16V 1 P2V5
C104 CAPCERSMDCL2_0805-22UF,6.3V 1 GND_SIGNAL C104 CAPCERSMDCL2_0805-22UF,6.3V 1 GND_SIGNAL
2 MGT_AVCC_A 2 MGT_AVCC_A
C105 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL C105 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL
2 UNNAMED_7_CAPCERSMDCL2_I74_B 2 MGT_AVCC_A
C106 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL C106 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL
2 UNNAMED_7_CAPCERSMDCL2_I70_B 2 MGT_AVCC_A
C107 CAPCERSMDCL2_0402-1UF,16V 1 GND_SIGNAL C107 CAPCERSMDCL2_0402-1UF,16V 1 GND_SIGNAL
2 MGT_AVCC_A 2 MGT_AVCC_A
C108 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL C108 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL
2 UNNAMED_7_CAPCERSMDCL2_I74_B 2 MGT_AVCC_A
C109 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL C109 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL
2 UNNAMED_7_CAPCERSMDCL2_I70_B 2 MGT_AVCC_A
C110 CAPCERSMDCL2_0402-1UF,16V 1 GND_SIGNAL C110 CAPCERSMDCL2_0402-1UF,16V 1 GND_SIGNAL
2 MGT_AVCC_A 2 MGT_AVCC_A
C111 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL C111 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL
2 UNNAMED_7_CAPCERSMDCL2_I74_B 2 MGT_AVCC_A
C112 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL C112 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL
2 UNNAMED_7_CAPCERSMDCL2_I70_B 2 MGT_AVCC_A
C113 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL C113 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL
2 UNNAMED_7_CAPCERSMDCL2_I74_B 2 MGT_AVCC_A
C114 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL C114 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL
2 UNNAMED_7_CAPCERSMDCL2_I70_B 2 MGT_AVCC_A
C115 CAPCERSMDCL2_1206-100UF_X5R,6.A 1 GND_SIGNAL C115 CAPCERSMDCL2_1206-100UF_X5R,6.A 1 GND_SIGNAL
2 P1V2 2 P1V2
C116 CAPCERSMDCL2_1206-100UF_X5R,6.A 1 GND_SIGNAL C116 CAPCERSMDCL2_1206-100UF_X5R,6.A 1 GND_SIGNAL
...@@ -879,7 +879,7 @@ IC15 24AA64T-I/MC 1 GND_SIGNAL ...@@ -879,7 +879,7 @@ IC15 24AA64T-I/MC 1 GND_SIGNAL
6 FPGA_SCL 6 FPGA_SCL
7 GND_SIGNAL 7 GND_SIGNAL
8 P3V3 8 P3V3
IC16 SN74LVC1G06DBVT 2 FPGA_DONE IC16 SN74LVC1G06DBVT-GND=GND_SIGNALA 2 FPGA_DONE
4 UNNAMED_13_LED_I46_K 4 UNNAMED_13_LED_I46_K
IC20 TPS71701DCKRG4_SC70-TEXAS INSTA 1 P2V5 IC20 TPS71701DCKRG4_SC70-TEXAS INSTA 1 P2V5
2 GND_SIGNAL 2 GND_SIGNAL
...@@ -1726,22 +1726,22 @@ RG1_1 LM2937IMP_SOT223-2.5V,TI 1 AVDD ...@@ -1726,22 +1726,22 @@ RG1_1 LM2937IMP_SOT223-2.5V,TI 1 AVDD
2 GND_SIGNAL 2 GND_SIGNAL
3 VH_1 3 VH_1
4 GND_SIGNAL 4 GND_SIGNAL
RN1 R4ISMD_1206-150 1 FPGA_GPIO<3> RN1 R4ISMD_1206-150 1 UNNAMED_8_CON12P_I51_A_1
2 FPGA_GPIO<2> 2 UNNAMED_8_CON12P_I51_A_2
3 FPGA_GPIO<1> 3 UNNAMED_8_CON12P_I51_A_3
4 FPGA_GPIO<0> 4 UNNAMED_8_CON12P_I51_A_4
5 UNNAMED_8_CON12P_I51_A_4 5 FPGA_GPIO<0>
6 UNNAMED_8_CON12P_I51_A_3 6 FPGA_GPIO<1>
7 UNNAMED_8_CON12P_I51_A_2 7 FPGA_GPIO<2>
8 UNNAMED_8_CON12P_I51_A_1 8 FPGA_GPIO<3>
RN2 R4ISMD_1206-150 1 UNNAMED_8_CON12P_I51_A RN2 R4ISMD_1206-150 1 FPGA_GPIO<7>
2 UNNAMED_8_CON12P_I51_A_7 2 FPGA_GPIO<6>
3 UNNAMED_8_CON12P_I51_A_5 3 FPGA_GPIO<5>
4 UNNAMED_8_CON12P_I51_A_6 4 FPGA_GPIO<4>
5 FPGA_GPIO<4> 5 UNNAMED_8_CON12P_I51_A_6
6 FPGA_GPIO<5> 6 UNNAMED_8_CON12P_I51_A_5
7 FPGA_GPIO<6> 7 UNNAMED_8_CON12P_I51_A_7
8 FPGA_GPIO<7> 8 UNNAMED_8_CON12P_I51_A
RZ1 R4ISMD_1206-150 1 GND_SIGNAL RZ1 R4ISMD_1206-150 1 GND_SIGNAL
2 GND_SIGNAL 2 GND_SIGNAL
3 GND_SIGNAL 3 GND_SIGNAL
...@@ -1750,14 +1750,14 @@ RZ1 R4ISMD_1206-150 1 GND_SIGNAL ...@@ -1750,14 +1750,14 @@ RZ1 R4ISMD_1206-150 1 GND_SIGNAL
6 UNNAMED_8_LED_I108_K 6 UNNAMED_8_LED_I108_K
7 UNNAMED_8_LED_I107_K 7 UNNAMED_8_LED_I107_K
8 UNNAMED_8_LED_I105_K 8 UNNAMED_8_LED_I105_K
RZ2 R4ISMD_1206-4.7K 1 GND_SIGNAL RZ2 R4ISMD_1206-4.7K 1 DIP_SWITCH<3>
2 GND_SIGNAL 2 DIP_SWITCH<2>
3 GND_SIGNAL 3 DIP_SWITCH<1>
4 GND_SIGNAL 4 DIP_SWITCH<0>
5 DIP_SWITCH<0> 5 GND_SIGNAL
6 DIP_SWITCH<1> 6 GND_SIGNAL
7 DIP_SWITCH<2> 7 GND_SIGNAL
8 DIP_SWITCH<3> 8 GND_SIGNAL
SW1 SW_PUSHBUTTON_1SPSTA_4P_1-OMROA 1 UNNAMED_8_RSMD0603_I92_B SW1 SW_PUSHBUTTON_1SPSTA_4P_1-OMROA 1 UNNAMED_8_RSMD0603_I92_B
2 P3V3 2 P3V3
3 UNNAMED_8_RSMD0603_I92_B 3 UNNAMED_8_RSMD0603_I92_B
...@@ -2017,7 +2017,7 @@ U2 AD8031_SOT23-5-AD 1 UNNAMED_8_AD8031_I70_IN ...@@ -2017,7 +2017,7 @@ U2 AD8031_SOT23-5-AD 1 UNNAMED_8_AD8031_I70_IN
2 GND_SIGNAL 2 GND_SIGNAL
3 UNBUF_CTEST 3 UNBUF_CTEST
4 UNNAMED_8_AD8031_I70_IN 4 UNNAMED_8_AD8031_I70_IN
5 AVDD 5 P3V3
U3 PC049A_FPGA A1 GND_SIGNAL U3 PC049A_FPGA A1 GND_SIGNAL
A2 LVDS_DLEFT_N<15> A2 LVDS_DLEFT_N<15>
A3 LVDS_DLEFT_N<14> A3 LVDS_DLEFT_N<14>
...@@ -2207,8 +2207,8 @@ U3 PC049A_FPGA A1 GND_SIGNAL ...@@ -2207,8 +2207,8 @@ U3 PC049A_FPGA A1 GND_SIGNAL
H2 FPGA_LEDS<2> H2 FPGA_LEDS<2>
H3 FPGA_LEDS<1> H3 FPGA_LEDS<1>
H4 FPGA_LEDS<0> H4 FPGA_LEDS<0>
H5 P3V3 H5 UNNAMED_8_RSMD0603_I92_B
H6 P3V3 H6 UNNAMED_8_RSMD0603_I97_B
H7 GND_SIGNAL H7 GND_SIGNAL
H9 P2V5 H9 P2V5
H15 P2V5 H15 P2V5
......
design_files/worklib/pc049a_toplevel/packaged/dialcprt.dat
View file @ b31f50a2
...@@ -92,11 +92,11 @@ RSMD0603_1/16W-40.2K,1% R0603_40K2_1%_0.063W_100PPM 1 ...@@ -92,11 +92,11 @@ RSMD0603_1/16W-40.2K,1% R0603_40K2_1%_0.063W_100PPM 1
RSMD0603_1/16W-9K,1% R0603_9K_1%_0.063W_100PPM 1 RSMD0603_1/16W-9K,1% R0603_9K_1%_0.063W_100PPM 1
RSMD0805_-00, R0805_00_JUMPER 2 RSMD0805_-00, R0805_00_JUMPER 2
S25FL128SAGMFIR01-VCC=P3V3,VSSA S25FL128SAGMFIR01 1 S25FL128SAGMFIR01-VCC=P3V3,VSSA S25FL128SAGMFIR01 1
SFP_CAGE-6367034-1 6367034-1 2 SFP_CAGE-6367034-1-GND=GND_SIGA 6367034-1 2
SFP_CAGE-6367035-1 6367035-1 2 SFP_CAGE-6367035-1-GND=GND_SIGA 6367035-1 2
SK_SATA_SMD_STR-MOLEX Molex 67800-5025 2 SK_SATA_SMD_STR-MOLEX Molex 67800-5025 2
SN65LVDS1_SOT23-5-TEXAS INSTRUA snlvds1dbv 1 SN65LVDS1_SOT23-5-TEXAS INSTRUA snlvds1dbv 1
SN74LVC1G06DBVT SN74LVC1G06DBVT 1 SN74LVC1G06DBVT-GND=GND_SIGNALA SN74LVC1G06DBVT 1
SW4INT-1571983-4 1571983-4 1 SW4INT-1571983-4 1571983-4 1
SW_PUSHBUTTON_1SPSTA_4P_1-OMROA b3sn-3012 3 SW_PUSHBUTTON_1SPSTA_4P_1-OMROA b3sn-3012 3
TPS71701DCKRG4_SC70-TEXAS INSTA TI tps71701dckrg4 1 TPS71701DCKRG4_SC70-TEXAS INSTA TI tps71701dckrg4 1
......
design_files/worklib/pc049a_toplevel/packaged/dialpgnd_new.dat
View file @ b31f50a2
...@@ -21,8 +21,8 @@ IC7 DS90LV001TM-GND=GND_SIGNAL,VCCA ...@@ -21,8 +21,8 @@ IC7 DS90LV001TM-GND=GND_SIGNAL,VCCA
IC9 AD5662BRMZ-1-GND=GND_SIGNAL,VDA IC9 AD5662BRMZ-1-GND=GND_SIGNAL,VDA
GND_SIGNAL P3V3A GND_SIGNAL P3V3A
8 1 8 1
IC16 SN74LVC1G06DBVT IC16 SN74LVC1G06DBVT-GND=GND_SIGNALA
GND VCC GND_SIGNAL P3V3
3 5 3 5
IC22 S25FL128SAGMFIR01-VCC=P3V3,VSSA IC22 S25FL128SAGMFIR01-VCC=P3V3,VSSA
GND_SIGNAL P3V3 GND_SIGNAL P3V3
...@@ -59,8 +59,8 @@ RG1 LT3070EUFD#PBF-GND=GND_SIGNAL ...@@ -59,8 +59,8 @@ RG1 LT3070EUFD#PBF-GND=GND_SIGNAL
20 20
26 26
29 29
SFP1 SFP_CAGE-6367034-1 SFP1 SFP_CAGE-6367034-1-GND=GND_SIGA
GND GND_SIGNAL
1 1
2 2
3 3
...@@ -78,13 +78,13 @@ SFP1 SFP_CAGE-6367034-1 ...@@ -78,13 +78,13 @@ SFP1 SFP_CAGE-6367034-1
15 15
16 16
17 17
SFP2 SFP_CAGE-6367035-1 SFP2 SFP_CAGE-6367035-1-GND=GND_SIGA
GND GND_SIGNAL
1 1
2 2
3 3
SFP3 SFP_CAGE-6367034-1 SFP3 SFP_CAGE-6367034-1-GND=GND_SIGA
GND GND_SIGNAL
1 1
2 2
3 3
...@@ -102,8 +102,8 @@ SFP3 SFP_CAGE-6367034-1 ...@@ -102,8 +102,8 @@ SFP3 SFP_CAGE-6367034-1
15 15
16 16
17 17
SFP4 SFP_CAGE-6367035-1 SFP4 SFP_CAGE-6367035-1-GND=GND_SIGA
GND GND_SIGNAL
1 1
2 2
3 3
......
design_files/worklib/pc049a_toplevel/packaged/dialstf.dat
View file @ b31f50a2
...@@ -751,13 +751,13 @@ S25FL128SAGMFIR01-VCC=P3V3,VSSA S25FL128SAGMFIR01 IC22 ...@@ -751,13 +751,13 @@ S25FL128SAGMFIR01-VCC=P3V3,VSSA S25FL128SAGMFIR01 IC22
---------------- ----------------
SFP_CAGE-6367034-1 6367034-1 SFP1 SFP_CAGE-6367034-1-GND=GND_SIGA 6367034-1 SFP1
SFP_CAGE-6367034-1 6367034-1 SFP3 SFP_CAGE-6367034-1-GND=GND_SIGA 6367034-1 SFP3
---------------- ----------------
SFP_CAGE-6367035-1 6367035-1 SFP2 SFP_CAGE-6367035-1-GND=GND_SIGA 6367035-1 SFP2
SFP_CAGE-6367035-1 6367035-1 SFP4 SFP_CAGE-6367035-1-GND=GND_SIGA 6367035-1 SFP4
---------------- ----------------
...@@ -770,7 +770,7 @@ SN65LVDS1_SOT23-5-TEXAS INSTRUA snlvds1dbv U5 ...@@ -770,7 +770,7 @@ SN65LVDS1_SOT23-5-TEXAS INSTRUA snlvds1dbv U5
---------------- ----------------
SN74LVC1G06DBVT SN74LVC1G06DBVT IC16 SN74LVC1G06DBVT-GND=GND_SIGNALA SN74LVC1G06DBVT IC16
---------------- ----------------
......
design_files/worklib/pc049a_toplevel/packaged/scald.list
View file @ b31f50a2
Starting to read /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/pstchip.dat Starting to read /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/pstchip.dat
Finished reading /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/pstchip.dat (00:00:00.11) Finished reading /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/pstchip.dat (00:00:00.10)
Starting to read /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/pstxprt.dat Starting to read /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/pstxprt.dat
Finished reading /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/pstxprt.dat (00:00:00.02) Finished reading /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/pstxprt.dat (00:00:00.02)
Starting to read /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/pstxnet.dat Starting to read /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/pstxnet.dat
...@@ -13,15 +13,15 @@ Starting to generate /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/tr ...@@ -13,15 +13,15 @@ Starting to generate /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/tr
Starting to generate /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/dialstf.dat Starting to generate /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/dialstf.dat
Finished generating /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/dialstf.dat (00:00:00.04) Finished generating /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/dialstf.dat (00:00:00.04)
Starting to generate /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/dialpgnd.dat Starting to generate /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/dialpgnd.dat
Finished generating /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/dialpgnd.dat (00:00:00.03) Finished generating /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/dialpgnd.dat (00:00:00.04)
Starting to generate /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/dialpgnd_new.dat Starting to generate /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/dialpgnd_new.dat
Finished generating /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/dialpgnd_new.dat (00:00:00.04) Finished generating /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/dialpgnd_new.dat (00:00:00.04)
Starting to generate /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/scald.xref Starting to generate /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/scald.xref
Finished generating /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/scald.xref (00:00:00.05) Finished generating /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/scald.xref (00:00:00.05)
SCALD Lists Interface run on Jul 29 17:21:32 2014 SCALD Lists Interface run on Mar 23 15:08:32 2015
DESIGN NAME : 'PC049A_TOPLEVEL' DESIGN NAME : 'PC049A_TOPLEVEL'
PACKAGING ON 29-Jul-2014 AT 17:05:48 PACKAGING ON 06-Oct-2014 AT 12:40:31
DIRECTORIES <none> DIRECTORIES <none>
LIBRARIES 'uob_hep_pc049a_lib' 'bris_cds_analogue' 'bris_cds_connectors' LIBRARIES 'uob_hep_pc049a_lib' 'bris_cds_analogue' 'bris_cds_connectors'
......
firmware/README
View file @ b31f50a2
...@@ -7,3 +7,12 @@ cd uob-hep-pc049a/trunk/firmware/syn/pc049a/demo ...@@ -7,3 +7,12 @@ cd uob-hep-pc049a/trunk/firmware/syn/pc049a/demo
hdlmake-v1.0 --make-ise --ise-proj hdlmake-v1.0 --make-ise --ise-proj
make make
..... for newer versions....
python /projects/HEP_Instrumentation/cad/designs/hdl-make/git-2.1/hdl-make/hdlmake ise-project
......... For HDLMake 2.x
firmware/hdl/IPBusInterfaceGTP_rtl.vhd
View file @ b31f50a2
...@@ -110,8 +110,8 @@ BEGIN ...@@ -110,8 +110,8 @@ BEGIN
-- FIXME - connect SFP control signals -- FIXME - connect SFP control signals
sfp_scl_o <= '0'; sfp_scl_o <= '1';
sfp_sda_o <= sfp_det_i; sfp_sda_o <= '1';
-- DCM clock generation for internal bus, ethernet -- DCM clock generation for internal bus, ethernet
clocks: entity work.clocks_s6_basex port map( clocks: entity work.clocks_s6_basex port map(
...@@ -129,8 +129,9 @@ BEGIN ...@@ -129,8 +129,9 @@ BEGIN
-- Connect IPBus clock and reset to output ports. -- Connect IPBus clock and reset to output ports.
ipb_clk_o <= s_ipb_clk; ipb_clk_o <= s_ipb_clk;
ipb_rst_o <= rst_ipb; ipb_rst_o <= rst_ipb;
-- leds <= ('0', '0', locked, onehz); -- connect up locked signal
clocks_locked_o <= locked;
-- Ethernet MAC core and PHY interface -- Ethernet MAC core and PHY interface
-- In this version, consists of hard MAC core + GTP transceiver -- In this version, consists of hard MAC core + GTP transceiver
......
firmware/hdl/clocks_s6_basex.vhd
View file @ b31f50a2
-- clocks_s6_basex -- clocks_s6_basex
-- --
-- Generates a 25MHz ipbus clock from 200MHz xtal reference -- Generates a 31.25MHz ipbus clock from 125MHz xtal reference
-- Includes reset logic for ipbus -- Includes reset logic for ipbus
-- --
-- Dave Newbold, April 2011 -- Dave Newbold, April 2011
-- --
-- DGC , 26/March/2015 Modified original (which generated a 25MHz ipbus clock from 200MHz xtal reference)
-- $Id$ -- $Id$
library ieee; library ieee;
...@@ -43,11 +44,12 @@ begin ...@@ -43,11 +44,12 @@ begin
o => clk_ipb_b o => clk_ipb_b
); );
-- 125MHz input ( 8ns period ), 31.25MHz output ( 32ns )
dcm0: DCM_CLKGEN dcm0: DCM_CLKGEN
generic map( generic map(
CLKIN_PERIOD => 5.0, CLKIN_PERIOD => 8.0,
CLKFX_MULTIPLY => 2, CLKFX_MULTIPLY => 2,
CLKFX_DIVIDE => 16 CLKFX_DIVIDE => 8
) )
port map( port map(
clkin => sysclk_i, clkin => sysclk_i,
......
firmware/hdl/ipbus_addr_decode.vhd
View file @ b31f50a2
...@@ -27,53 +27,17 @@ package body ipbus_addr_decode is ...@@ -27,53 +27,17 @@ package body ipbus_addr_decode is
function ipbus_addr_sel(signal addr : in std_logic_vector(31 downto 0)) return integer is function ipbus_addr_sel(signal addr : in std_logic_vector(31 downto 0)) return integer is
variable sel : integer; variable sel : integer;
begin begin
if std_match(addr, "-----------------000--000----000") then
sel := 0; -- firmwareid / base 00000000 / mask 00000000
elsif std_match(addr, "-----------------000--000----001") then
sel := 1; -- gpio / base 00000001 / mask 00000000
elsif std_match(addr, "-----------------000--000----010") then
sel := 2; -- select / base 00000002 / mask 00000000
elsif std_match(addr, "-----------------000--000----011") then
sel := 3; -- mask / base 00000003 / mask 00000000
elsif std_match(addr, "-----------------000--000----100") then
sel := 4; -- reset / base 00000004 / mask 00000000
elsif std_match(addr, "-----------------000--001-------") then
sel := 5; -- scshiftreg / base 00000080 / mask 0000007f
elsif std_match(addr, "-----------------000--010-------") then
sel := 6; -- rshiftreg / base 00000100 / mask 0000007f
elsif std_match(addr, "-----------------111--0---------") then if std_match(addr, "-------------------0--001-------") then
sel := 7; -- triggerctrl / base 00007000 / mask 00000fff sel := 0; -- scshiftreg / base 00000080 / mask 0000007f
elsif std_match(addr, "-----------------111--1---------") then elsif std_match(addr, "-------------------0--010-------") then
sel := 8; -- triggerdata / base 00007200 / mask 00000fff sel := 1; -- rshiftreg / base 00000100 / mask 0000007f
elsif std_match(addr, "-------------------0--110-------") then
elsif std_match(addr, "-----------------001--1---------") then sel := 2; -- triggerctrl / base 00000300 / mask 000007f
sel := 10; -- adcctrl0 / base 00001200 / mask 00000fff elsif std_match(addr, "-------------------1--000-------") then
elsif std_match(addr, "-----------------001--0---------") then sel := 3; -- adc / base 00001000 / mask 00000fff
sel := 11; -- adcdata0 / base 00001000 / mask 00000fff elsif std_match(addr, "-------------------0--000-------") then
sel := 5; -- firmwareid / base 00000000 / mask 00000000
elsif std_match(addr, "-----------------010--1---------") then
sel := 12; -- adcctrl1 / base 00002200 / mask 00000fff
elsif std_match(addr, "-----------------010--0---------") then
sel := 13; -- adcdata1 / base 00002000 / mask 00000fff
elsif std_match(addr, "-----------------011--1---------") then
sel := 14; -- adcctrl2 / base 00003200 / mask 00000fff
elsif std_match(addr, "-----------------011--0---------") then
sel := 15; -- adcdata2 / base 00003000 / mask 00000fff
elsif std_match(addr, "-----------------100--1---------") then
sel := 16; -- adcctrl3 / base 00004200 / mask 00000fff
elsif std_match(addr, "-----------------100--0---------") then
sel := 17; -- adcdata3 / base 00004000 / mask 00000fff
elsif std_match(addr, "-----------------101--1---------") then
sel := 18; -- adcctrl4 / base 00005200 / mask 00000fff
elsif std_match(addr, "-----------------101--0---------") then
sel := 19; -- adcdata4 / base 00005000 / mask 00000fff
elsif std_match(addr, "-----------------110------------") then
sel := 9; -- hostemac / base 00006000 / mask 00000fff
else else
sel := 99; sel := 99;
end if; end if;
......
firmware/hdl/ipbus_ver.vhd
View file @ b31f50a2
...@@ -20,7 +20,7 @@ architecture rtl of ipbus_ver is ...@@ -20,7 +20,7 @@ architecture rtl of ipbus_ver is
begin begin
ipbus_out.ipb_rdata <= X"a618" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement). ipbus_out.ipb_rdata <= X"a61f" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement).
ipbus_out.ipb_ack <= ipbus_in.ipb_strobe; ipbus_out.ipb_ack <= ipbus_in.ipb_strobe;
ipbus_out.ipb_err <= '0'; ipbus_out.ipb_err <= '0';
......
firmware/hdl/marocInterface_rtl.vhd
View file @ b31f50a2
...@@ -65,7 +65,9 @@ architecture rtl of marocInterface is ...@@ -65,7 +65,9 @@ architecture rtl of marocInterface is
signal s_timeStamp : std_logic_vector(c_BUSWIDTH-1 downto 0); signal s_timeStamp : std_logic_vector(c_BUSWIDTH-1 downto 0);
signal s_tree_or : std_logic_vector( maroc_trigger_i'left+1 downto 0); signal s_tree_or : std_logic_vector( maroc_trigger_i'left+1 downto 0);
signal ck_40m : std_logic := '0'; -- internal MAROC clock.
begin -- rtl begin -- rtl
...@@ -80,8 +82,8 @@ begin -- rtl ...@@ -80,8 +82,8 @@ begin -- rtl
-- q => register_data -- q => register_data
-- ); -- );
-- Slave 1: slow control shift register controller -- Slave 0: slow control shift register controller
slave1: entity work.ipbusMarocShiftReg slave0: entity work.ipbusMarocShiftReg
generic map( generic map(
g_NBITS => 829, --! Number of bits to shift out to MAROC g_NBITS => 829, --! Number of bits to shift out to MAROC
g_NWORDS => c_NWORDS, --! Number of words in IPBUS space to store data g_NWORDS => c_NWORDS, --! Number of words in IPBUS space to store data
...@@ -103,8 +105,8 @@ begin -- rtl ...@@ -103,8 +105,8 @@ begin -- rtl
rst_sr_n_o => rst_sc_n_o rst_sr_n_o => rst_sc_n_o
); );
-- Slave 2: "R" register shift register controller -- Slave 1: "R" register shift register controller
slave2: entity work.ipbusMarocShiftReg slave1: entity work.ipbusMarocShiftReg
generic map( generic map(
g_NBITS => 128, --! Number of bits to shift out to MAROC g_NBITS => 128, --! Number of bits to shift out to MAROC
g_NWORDS => c_NWORDS, --! Number of words in IPBUS space to store data g_NWORDS => c_NWORDS, --! Number of words in IPBUS space to store data
...@@ -126,8 +128,8 @@ begin -- rtl ...@@ -126,8 +128,8 @@ begin -- rtl
rst_sr_n_o => rst_r_n_o rst_sr_n_o => rst_r_n_o
); );
-- Slave 3: Simple ADC controller -- Slave 2: Simple ADC controller
slave3: entity work.ipbusMarocADC slave2: entity work.ipbusMarocADC
generic map( generic map(
g_ADDRWIDTH => 10 ) g_ADDRWIDTH => 10 )
port map( port map(
...@@ -163,8 +165,8 @@ begin -- rtl ...@@ -163,8 +165,8 @@ begin -- rtl
-- FIXME - clk fast -- FIXME - clk fast
-- Slave 4: Trigger generator -- Slave 3: Trigger generator
slave4: entity work.ipbusMarocTriggerGenerator slave3: entity work.ipbusMarocTriggerGenerator
port map ( port map (
-- signals to IPBus -- signals to IPBus
clk_i => ipb_clk_i, clk_i => ipb_clk_i,
...@@ -206,15 +208,28 @@ begin -- rtl ...@@ -206,15 +208,28 @@ begin -- rtl
s_tree_or(i+1) <= s_tree_or(i) or maroc_trigger_i(i); s_tree_or(i+1) <= s_tree_or(i) or maroc_trigger_i(i);
end generate gen_maroc_or; end generate gen_maroc_or;
-- FIXME - for now, just wire up any old signal to an OBUFDS
-- to get correct signal type for CK_40M -- For now use IPBus clock as MAROC clock
ck_40m_obuf : OBUFDS ck_40m_obuf : OBUFDS
port map ( port map (
I => s_externalTrigger_o or s_tree_or(s_tree_or'left), I => CK_40M,
O => CK_40M_P_O, O => CK_40M_P_O,
OB => CK_40M_N_O OB => CK_40M_N_O
); );
-- Use a DDR output register to get from clock net onto output.
maroc_clock_buf : ODDR2
port map (
Q => CK_40M, -- 1-bit output data
C0 => ipb_clk_i , -- 1-bit clock input
C1 => not ipb_clk_i , -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => '0', -- 1-bit data input (associated with C0)
D1 => '1', -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
EN_OTAQ_O <= '1'; EN_OTAQ_O <= '1';
......
firmware/top/pc049a/demo/Manifest.py
View file @ b31f50a2
files = ["pc049a_top.vhd", "pc049a_top.ucf", "spec_reset_gen.vhd", "ExpansionIO_rtl.vhd"] files = ["pc049a_top.vhd", "pc049a_top.ucf", "spec_reset_gen.vhd", "../../../hdl/ExpansionIO_rtl.vhd"]
modules = { "local" : ["../../../"] } modules = { "local" : ["../../../"] }
firmware/top/pc049a/demo/pc049a_top.ucf
View file @ b31f50a2
...@@ -16,7 +16,7 @@ CONFIG VCCAUX=2.5; ...@@ -16,7 +16,7 @@ CONFIG VCCAUX=2.5;
INST "cmp_gtp_dedicated_clk_buf0" LOC = BUFDS_X2Y5; INST "cmp_gtp_dedicated_clk_buf0" LOC = BUFDS_X2Y5;
INST "IPBusInterface_inst/eth/ibuf0" LOC = BUFDS_X1Y5; INST "IPBusInterface_inst/eth/ibuf0" LOC = BUFDS_X1Y5;
INST "IPBusInterface_inst/eth/phy/transceiver_inst/GTP_1000X/tile0_s6_gtpwizard_i/gtpa1_dual_i" LOC = GTPA1_DUAL_X0Y1; INST "IPBusInterface_inst/eth/phy/transceiver_inst/GTP_1000X/tile0_s6_gtpwizard_i/gtpa1_dual_i" LOC = GTPA1_DUAL_X0Y1;
INST "U_GTP/U_GTP_TILE_INST/gtpa1_dual_i" LOC = GTPA1_DUAL_X1Y1; # INST "U_GTP/U_GTP_TILE_INST/gtpa1_dual_i" LOC = GTPA1_DUAL_X1Y1;
NET "ADC_DAV_I" IOSTANDARD = SSTL2_I; NET "ADC_DAV_I" IOSTANDARD = SSTL2_I;
NET "ADC_DAV_I" LOC = W1; NET "ADC_DAV_I" LOC = W1;
...@@ -506,14 +506,16 @@ NET "RST_SC_N_O" IOSTANDARD = LVCMOS33; ...@@ -506,14 +506,16 @@ NET "RST_SC_N_O" IOSTANDARD = LVCMOS33;
NET "RST_SC_N_O" LOC = U4; NET "RST_SC_N_O" LOC = U4;
NET "RST_SC_N_O_OBUF" IOSTANDARD = LVCMOS33; NET "RST_SC_N_O_OBUF" IOSTANDARD = LVCMOS33;
NET "RST_SC_N_O" SLEW = SLOW; NET "RST_SC_N_O" SLEW = SLOW;
NET "sata_rxn_i[0]" LOC = D13; NET "sata_rxp_i[0]" LOC = D13;
NET "sata_rxn_i[1]" LOC = C9; NET "sata_rxn_i[1]" LOC = C9;
NET "sata_rxp_i[0]" LOC = C13; NET "sata_rxn_i[0]" LOC = C13;
NET "sata_rxp_i[1]" LOC = D9; NET "sata_rxp_i[1]" LOC = D9;
NET "sata_txn_o[0]" LOC = B14; NET "sata_txp_o[0]" LOC = B14;
NET "sata_txn_o[1]" LOC = A8; NET "sata_txn_o[1]" LOC = A8;
NET "sata_txp_o[0]" LOC = A14; NET "sata_txn_o[0]" LOC = A14;
NET "sata_txp_o[1]" LOC = B8; NET "sata_txp_o[1]" LOC = B8;
NET "sfp_mod_def*" PULLUP=true;
NET "sfp_rate_select_b*" PULLUP=true;
NET "sfp_los_i[0]" IOSTANDARD = LVCMOS33; NET "sfp_los_i[0]" IOSTANDARD = LVCMOS33;
NET "sfp_los_i[0]" LOC = P3; NET "sfp_los_i[0]" LOC = P3;
NET "sfp_los_i[1]" IOSTANDARD = LVCMOS33; NET "sfp_los_i[1]" IOSTANDARD = LVCMOS33;
......
firmware/top/pc049a/demo/pc049a_top.vhd
View file @ b31f50a2
--============================================================================= --=============================================================================
--! @file pc049a_top.vhd --! @file pc049a_top.vhd
--============================================================================= --=============================================================================
...@@ -21,6 +20,12 @@ ...@@ -21,6 +20,12 @@
-- --
--! @details --! @details
--! Includes white-rabbit core, and IPBus core. --! Includes white-rabbit core, and IPBus core.
--! LEDs:
--! LED(0) - White Rabbit link active
--! LED(1) - White Rabbit link present
--! LED(2) - IPBus clocks locked. ( should be on )
--! LED(3) - One Hz heart-beat ( should strobe at 1Hz)
--! LED(4) - LOS for IPBus SFP ( should be off )
--! --!
--! <b>Dependencies:</b>\n --! <b>Dependencies:</b>\n
--! --!
...@@ -62,7 +67,7 @@ use work.wishbone_pkg.all; ...@@ -62,7 +67,7 @@ use work.wishbone_pkg.all;
entity pc049a_top is entity pc049a_top is
generic generic
( (
TAR_ADDR_WDTH : integer := 13 -- not used for this project BUILD_WHITERABBIT : integer := 1 -- set to 1 to synthesize White Rabbit cores
); );
port port
( (
...@@ -91,11 +96,10 @@ entity pc049a_top is ...@@ -91,11 +96,10 @@ entity pc049a_top is
dip_switch_i : in std_logic_vector(3 downto 0); dip_switch_i : in std_logic_vector(3 downto 0);
-- SPI interface for DACs that tune VCXO frequencies -- SPI interface for DACs that tune VCXO frequencies
pll25dac_sclk_o : out std_logic; pll25dac_sclk_o : out std_logic := '0';
pll25dac_din_o : out std_logic; pll25dac_din_o : out std_logic := '0';
-- dac_clr_n_o : out std_logic; -- not used. pll25dac1_sync_n_o : out std_logic := '1';
pll25dac1_sync_n_o : out std_logic; pll25dac2_sync_n_o : out std_logic := '1';
pll25dac2_sync_n_o : out std_logic;
-- I2C bus -- I2C bus
fpga_scl_b : inout std_logic; fpga_scl_b : inout std_logic;
...@@ -192,17 +196,7 @@ entity pc049a_top is ...@@ -192,17 +196,7 @@ entity pc049a_top is
lvds_gclk_from_fpga_n_o: out std_logic; lvds_gclk_from_fpga_n_o: out std_logic;
enable_gclk_drive_o: out std_logic; enable_gclk_drive_o: out std_logic;
lvds_gclk_to_fpga_p_i: in std_logic; lvds_gclk_to_fpga_p_i: in std_logic;
lvds_gclk_to_fpga_n_i: in std_logic lvds_gclk_to_fpga_n_i: in std_logic
-- Daughter-board SPI lines
--dboard_miso_p_i : in std_logic;
--dboard_miso_n_i : in std_logic;
--dboard_sclk_p_o : out std_logic;
--dboard_sclk_n_o : out std_logic;
--dboard_mosi_p_o : out std_logic;
--dboard_mosi_n_o : out std_logic;
--dboard_ssn_p_o : out std_logic;
--dboard_ssn_n_o : out std_logic
); );
...@@ -238,9 +232,6 @@ architecture rtl of pc049a_top is ...@@ -238,9 +232,6 @@ architecture rtl of pc049a_top is
signal s_otrig_to_fpga , s_otrig_from_fpga : std_logic; signal s_otrig_to_fpga , s_otrig_from_fpga : std_logic;
signal s_gclk_to_fpga , s_gclk_from_fpga : std_logic; signal s_gclk_to_fpga , s_gclk_from_fpga : std_logic;
-- signals for daugher-board SPI over LVDS connections.
signal s_dboard_mosi, s_dboard_ssn,s_dboard_sclk, s_dboard_miso : std_logic;
-- Dedicated clock for GTP transceiver -- Dedicated clock for GTP transceiver
signal gtp_dedicated_clk : std_logic_vector(1 downto 0); signal gtp_dedicated_clk : std_logic_vector(1 downto 0);
...@@ -286,7 +277,7 @@ architecture rtl of pc049a_top is ...@@ -286,7 +277,7 @@ architecture rtl of pc049a_top is
signal wrc_sda_o : std_logic; signal wrc_sda_o : std_logic;
signal wrc_sda_i : std_logic; signal wrc_sda_i : std_logic;
signal sfp_scl_o : std_logic_vector(1 downto 0); signal sfp_scl_o : std_logic_vector(1 downto 0) := ( others => '0' );
signal sfp_scl_i : std_logic_vector(1 downto 0); signal sfp_scl_i : std_logic_vector(1 downto 0);
signal sfp_sda_o : std_logic_vector(1 downto 0); signal sfp_sda_o : std_logic_vector(1 downto 0);
signal sfp_sda_i : std_logic_vector(1 downto 0); signal sfp_sda_i : std_logic_vector(1 downto 0);
...@@ -356,15 +347,6 @@ architecture rtl of pc049a_top is ...@@ -356,15 +347,6 @@ architecture rtl of pc049a_top is
-- Signals that used to be connected at the top level... -- Signals that used to be connected at the top level...
signal uart_rxd , uart_txd : std_logic; signal uart_rxd , uart_txd : std_logic;
--signal dboard_miso_p_i : std_logic;
--signal dboard_miso_n_i : std_logic;
--signal dboard_sclk_p_o : std_logic;
--signal dboard_sclk_n_o : std_logic;
--signal dboard_mosi_p_o : std_logic;
--signal dboard_mosi_n_o : std_logic;
--signal dboard_ssn_p_o : std_logic;
--signal dboard_ssn_n_o : std_logic;
--
begin begin
...@@ -506,6 +488,10 @@ begin ...@@ -506,6 +488,10 @@ begin
one_wire_b <= '0' when owr_en(0) = '1' else 'Z'; one_wire_b <= '0' when owr_en(0) = '1' else 'Z';
owr_i(0) <= one_wire_b; owr_i(0) <= one_wire_b;
-- The White Rabbit cores use up space in the FPGA and consume power.
-- Don't build them unless we want them.
generate_whiterabbit: if ( BUILD_WHITERABBIT = 1 ) generate
U_WR_CORE : xwr_core U_WR_CORE : xwr_core
generic map ( generic map (
g_simulation => 0, g_simulation => 0,
...@@ -695,15 +681,17 @@ begin ...@@ -695,15 +681,17 @@ begin
dac_sclk_o => pll25dac_sclk_o, dac_sclk_o => pll25dac_sclk_o,
dac_din_o => pll25dac_din_o); dac_din_o => pll25dac_din_o);
end generate generate_whiterabbit;
U_Extend_PPS : gc_extend_pulse
generic map ( -- for now connect leds_o(4) to IPBus LOS
g_width => 10000000) --U_Extend_PPS : gc_extend_pulse
port map ( -- generic map (
clk_i => clk_125m_pllref, -- g_width => 10000000)
rst_n_i => local_reset_n, -- port map (
pulse_i => pps_led, -- clk_i => clk_125m_pllref,
extended_o => leds_o(4) ); -- rst_n_i => local_reset_n,
-- pulse_i => pps_led,
-- extended_o => leds_o(4) );
si57x_oe_o <= '1'; si57x_oe_o <= '1';
...@@ -827,43 +815,6 @@ begin ...@@ -827,43 +815,6 @@ begin
enable_gclk_drive_o <= '1'; enable_gclk_drive_o <= '1';
enable_globaltrig_drive_o <= '1'; enable_globaltrig_drive_o <= '1';
--
-- Differential buffers to Daughter-board SPI connection
--dboard_mosi_obuf : OBUFDS
-- port map (
-- I => s_dboard_mosi,
-- O => dboard_mosi_p_o,
-- OB => dboard_mosi_n_o
-- );
--dboard_ssn_obuf : OBUFDS
-- port map (
-- I => s_dboard_ssn,
-- O => dboard_ssn_p_o,
-- OB => dboard_ssn_n_o
-- );
--dboard_sclk_obuf : OBUFDS
-- port map (
-- I => s_dboard_sclk,
-- O => dboard_sclk_p_o,
-- OB => dboard_sclk_n_o
-- );
--dboard_miso_ibuf : IBUFDS
-- generic map (
-- DIFF_TERM => true)
-- port map (
-- O => s_dboard_miso,
-- I => dboard_miso_p_i,
-- IB => dboard_miso_n_i
-- );
-- FIXME dummy wiring to stop buffers being optimized away.
--s_dboard_mosi <= s_dboard_miso;
--s_dboard_ssn <= s_dboard_miso;
--s_dboard_sclk <= s_dboard_miso;
-- FIXME - loop dip_switches to gpio to stop GPIO being optimized away -- FIXME - loop dip_switches to gpio to stop GPIO being optimized away
gpio(3 downto 0) <= dip_switch_i; gpio(3 downto 0) <= dip_switch_i;
gpio(4) <= si57x_clk; gpio(4) <= si57x_clk;
...@@ -883,15 +834,17 @@ begin ...@@ -883,15 +834,17 @@ begin
IB => si57x_clk_n_i IB => si57x_clk_n_i
); );
-- FIXME - connnect input to output to avoid optimization. sfp_rate_select_b(0) <= '1'; --! Connect high for full rate.
sfp_rate_select_b <= sfp_los_i or sfp_tx_fault_i; sfp_rate_select_b(1) <= '1';
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- IPBus interface -- IPBus interface
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
IPBusInterface_inst : entity work.IPBusInterfaceGTP IPBusInterface_inst : entity work.IPBusInterfaceGTP
GENERIC MAP ( GENERIC MAP (
NUM_EXT_SLAVES => 6 NUM_EXT_SLAVES => c_NMAROC_SLAVES+1 --! Total number of IPBus slave
--busses = number in MAROC +1
) )
PORT MAP ( PORT MAP (
...@@ -932,6 +885,8 @@ begin ...@@ -932,6 +885,8 @@ begin
clk_logic_xtal_o => s_clk_logic_xtal clk_logic_xtal_o => s_clk_logic_xtal
); );
leds_o(4) <= sfp_los_i(1);
-- SFP control signals for IPBus SFP -- SFP control signals for IPBus SFP
sfp_mod_def1_b(1) <= '0' when sfp_scl_o(1) = '0' else 'Z'; sfp_mod_def1_b(1) <= '0' when sfp_scl_o(1) = '0' else 'Z';
sfp_mod_def2_b(1) <= '0' when sfp_sda_o(1) = '0' else 'Z'; sfp_mod_def2_b(1) <= '0' when sfp_sda_o(1) = '0' else 'Z';
...@@ -947,8 +902,8 @@ begin ...@@ -947,8 +902,8 @@ begin
-- IPBus -- IPBus
ipbus_clk_i => s_ipb_clk, ipbus_clk_i => s_ipb_clk,
ipbus_reset_i => s_ipb_rst, ipbus_reset_i => s_ipb_rst,
ipbus_wbus_i => s_ipb_wbus(5), ipbus_wbus_i => s_ipb_wbus(c_NMAROC_SLAVES),
ipbus_rbus_o => s_ipb_rbus(5), ipbus_rbus_o => s_ipb_rbus(c_NMAROC_SLAVES),
-- Data.... -- Data....
lvds_left_data_p_b => lvds_left_data_p_b, lvds_left_data_p_b => lvds_left_data_p_b,
......
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