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Scalable MAROC Charge Sensitive Readout
Commit 2f031cf3 authored by David Cussans's avatar David Cussans
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Connected trigger output to GPIO pin

parent fd606682
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Showing with 859 additions and 648 deletions
design_files/pc049a_toplevel.cpm
View file @ 2f031cf3
{ Machine generated file created by SPI } { Machine generated file created by SPI }
{ Last modified was 12:44:26 Thursday, January 07, 2016 } { Last modified was 18:39:41 Friday, September 16, 2016 }
{ NOTE: Do not modify the contents of this file. If this is regenerated by } { NOTE: Do not modify the contents of this file. If this is regenerated by }
{ SPI, your modifications will be overwritten. } { SPI, your modifications will be overwritten. }
...@@ -34,7 +34,6 @@ HPF_SPEC_PLOT_PAGESIZE 'YES' ...@@ -34,7 +34,6 @@ HPF_SPEC_PLOT_PAGESIZE 'YES'
HPF_BATCH 'YES' HPF_BATCH 'YES'
HPF_PLOT_FILE_LOCATION '/home/phdgc' HPF_PLOT_FILE_LOCATION '/home/phdgc'
HPF_PLOT_FILE_NAME 'pc049a_toplevel1.ps' HPF_PLOT_FILE_NAME 'pc049a_toplevel1.ps'
SEARCH_HISTORY 'c38' 'c32' 'c75' 'c85' 'c94'
PLOTTER_FACILITY 'DEVICE' PLOTTER_FACILITY 'DEVICE'
PLOT_EDGE_TO_EDGE 'ON' PLOT_EDGE_TO_EDGE 'ON'
PAPER_SIZE '9' PAPER_SIZE '9'
...@@ -45,6 +44,7 @@ HPF_PLOT_PAGESIZE 'A4' ...@@ -45,6 +44,7 @@ HPF_PLOT_PAGESIZE 'A4'
HPF_PAGESCALETYPE 'PAGESIZE' HPF_PAGESCALETYPE 'PAGESIZE'
HPF_PAGESIZE 'A4' HPF_PAGESIZE 'A4'
HPF_SCALEFACTOR '0.000000' HPF_SCALEFACTOR '0.000000'
SEARCH_HISTORY 'R8' 'c38' 'c32' 'c75' 'c85'
END_CONCEPTHDL END_CONCEPTHDL
START_PKGRXL START_PKGRXL
...@@ -103,15 +103,8 @@ retain_existing_xnets_and_diffpairs 'NO' ...@@ -103,15 +103,8 @@ retain_existing_xnets_and_diffpairs 'NO'
END_ECSET_MODELS END_ECSET_MODELS
START_VARIANT START_VARIANT
last_variant_file 'variant.dat'
last_edit_type '2'
last_sorted_column 'REFDES'
pref_status_name 'Pref'
sort_style '0'
annotation_property_name 'VARIANT'
annotation_property_value '*'
annotation_DNIproperty_value 'DNI'
columns 'REFDES' 'CDS_VAR_STATUS' 'PART_NAME' 'PART_NUMBER' columns 'REFDES' 'CDS_VAR_STATUS' 'PART_NAME' 'PART_NUMBER'
last_variant_file 'variant.dat'
END_VARIANT END_VARIANT
START_ALLEGRO START_ALLEGRO
......
design_files/worklib/pc049a_db/physical/allegro.jrl
View file @ 2f031cf3
\t (00:00:04) allegro 16.6-2015 S055 (v16-6-112EH) Linux I32
\t (00:00:04) Journal start - Thu Apr 14 13:23:40 2016
\t (00:00:04) Host=voltar.phy.bris.ac.uk User=phdgc Pid=3926 CPUs=8
\t (00:00:04) CmdLine= /software/CAD/Cadence/2015-16/RHELx86/SPB_16.60.055/tools/pcb/bin/allegro.exe -proj /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/pc049a_lemo_db.cpm -product Concept_HDL_studio -mpssession phdgc_ProjectMgr7061 -mpshost voltar.phy.bris.ac.uk
\t (00:00:04)
\t (00:00:05) Opening existing design...
\d (00:00:05) Design opened: /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_db/physical/pc049a_lemo_db_4l_13.brd
\t (00:00:06) Grids are drawn 0.4000, 0.4000 apart for enhanced viewability.
\i (00:00:06) trapsize 4725
\i (00:00:06) trapsize 4605
\i (00:00:07) trapsize 4745
\i (00:00:07) trapsize 3996
\t (00:00:07) Grids are drawn 0.4000, 0.4000 apart for enhanced viewability.
\i (00:00:07) trapsize 3996
\i (00:00:08) ifp
\i (00:00:11) zoom fit
\t (00:00:11) Grids are drawn 1.6000, 1.6000 apart for enhanced viewability.
\i (00:00:11) trapsize 10169
\i (00:01:41) pick grid 3.4574 -44.2338
\t (00:01:41) last pick: 3.5000 -44.2000
\i (00:01:49) plctxt out
\i (00:02:01) setwindow form.plctxt
\i (00:02:01) FORM plctxt filename placement_pin1.txt
\i (00:02:01) FORM plctxt pin_1 YES
\i (00:02:03) FORM plctxt execute
\t (00:02:03) Starting Place symbols by text file...
\i (00:03:00) FORM plctxt cancel
\i (00:03:01) setwindow pcb
\i (00:03:01) ifp
\i (00:08:23) zoom points
\t (00:08:23) Pick 1st corner of the new window.
\i (00:08:24) pick -39.0477 18.4053
\t (00:08:24) last pick: -39.0477 18.4053
\t (00:08:24) Pick to complete the window.
\i (00:08:25) pick 36.6072 -12.3041
\t (00:08:25) last pick: 36.6072 -12.3041
\t (00:08:25) Grids are drawn 0.4000, 0.4000 apart for enhanced viewability.
\i (00:08:25) trapsize 2765
\i (00:08:25) ifp
\i (00:08:47) pick grid -5.1468 -15.7168
\t (00:08:47) last pick: -5.1000 -15.7000
\i (00:08:48) roam y 96
\i (00:08:48) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:50) roam y -96
\i (00:08:50) roam y -96
\i (00:08:50) roam y -96
\i (00:08:50) roam y -96
\i (00:08:50) roam y -96
\i (00:08:50) roam y -96
\i (00:08:50) roam y -96
\i (00:08:50) roam y -96
\i (00:08:50) roam y -96
\i (00:08:50) roam y -96
\i (00:08:50) roam y -96
\i (00:08:50) roam y -96
\i (00:08:50) roam y -96
\i (00:08:50) roam y -96
\i (00:08:50) roam y -96
\i (00:08:50) roam y -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:52) roam x -96
\i (00:08:52) roam x -96
\i (00:08:54) show element
\i (00:11:26) pick grid -57.0313 -82.5654
\t (00:11:26) last pick: -57.0000 -82.6000
\i (00:11:28) zoom out
\i (00:11:28) setwindow pcb
\i (00:11:28) zoom out -70.2487 -91.3033
\t (00:11:28) Grids are drawn 0.8000, 0.8000 apart for enhanced viewability.
\i (00:11:28) trapsize 5530
\i (00:11:29) zoom out
\i (00:11:29) setwindow pcb
\i (00:11:29) zoom out -70.2488 -91.3034
\t (00:11:29) Grids are drawn 1.6000, 1.6000 apart for enhanced viewability.
\i (00:11:29) trapsize 11061
\i (00:11:29) zoom out
\i (00:11:29) setwindow pcb
\i (00:11:29) zoom out -70.2487 -91.3033
\t (00:11:29) Grids are drawn 3.2000, 3.2000 apart for enhanced viewability.
\i (00:11:29) trapsize 22121
\i (00:11:45) show element
\i (00:11:50) setwindow form.find
\i (00:11:50) FORM find shapes YES
\i (00:11:52) setwindow pcb
\i (00:11:52) pick grid -88.6647 4.0949
\t (00:11:52) last pick: -88.7000 4.1000
\i (00:15:10) odb_out
\i (00:15:18) fillin no
(00:15:18) Loading mfg.cxt
\i (00:15:31) exit
\e (00:15:32) Do you want to save the changes you made to pc049a_lemo_db_4l_13.brd?
\i (00:15:35) fillin no
\t (00:15:38) Journal end - Thu Apr 14 13:39:13 2016
design_files/worklib/pc049a_db/physical/allegro.jrl,1
View file @ 2f031cf3
\t (00:00:51) allegro 16.6-2015 S055 (v16-6-112EH) Linux I32 \t (00:00:04) allegro 16.6-2015 S055 (v16-6-112EH) Linux I32
\t (00:00:51) Journal start - Thu Apr 14 12:38:47 2016 \t (00:00:04) Journal start - Thu Apr 14 13:23:40 2016
\t (00:00:51) Host=voltar.phy.bris.ac.uk User=phdgc Pid=1851 CPUs=8 \t (00:00:04) Host=voltar.phy.bris.ac.uk User=phdgc Pid=3926 CPUs=8
\t (00:00:51) CmdLine= /software/CAD/Cadence/2015-16/RHELx86/SPB_16.60.055/tools/pcb/bin/allegro.exe -proj /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/pc049a_lemo_daughter_board.cpm -product Concept_HDL_studio -mpssession phdgc_ProjectMgr7061 -mpshost voltar.phy.bris.ac.uk \t (00:00:04) CmdLine= /software/CAD/Cadence/2015-16/RHELx86/SPB_16.60.055/tools/pcb/bin/allegro.exe -proj /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/pc049a_lemo_db.cpm -product Concept_HDL_studio -mpssession phdgc_ProjectMgr7061 -mpshost voltar.phy.bris.ac.uk
\t (00:00:51) \t (00:00:04)
\d (00:00:51) Design opened: /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_db/physical/pc049a_lemo_db_4l_13.brd \t (00:00:05) Opening existing design...
\i (00:00:51) ifp \d (00:00:05) Design opened: /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_db/physical/pc049a_lemo_db_4l_13.brd
\i (00:00:54) zoom fit \t (00:00:06) Grids are drawn 0.4000, 0.4000 apart for enhanced viewability.
\t (00:00:54) Grids are drawn 1.6000, 1.6000 apart for enhanced viewability. \i (00:00:06) trapsize 4725
\i (00:00:54) trapsize 10169 \i (00:00:06) trapsize 4605
\i (00:43:42) trapsize 13752 \i (00:00:07) trapsize 4745
\i (00:44:11) exit \i (00:00:07) trapsize 3996
\t (00:44:12) Journal end - Thu Apr 14 13:22:07 2016 \t (00:00:07) Grids are drawn 0.4000, 0.4000 apart for enhanced viewability.
\i (00:00:07) trapsize 3996
\i (00:00:08) ifp
\i (00:00:11) zoom fit
\t (00:00:11) Grids are drawn 1.6000, 1.6000 apart for enhanced viewability.
\i (00:00:11) trapsize 10169
\i (00:01:41) pick grid 3.4574 -44.2338
\t (00:01:41) last pick: 3.5000 -44.2000
\i (00:01:49) plctxt out
\i (00:02:01) setwindow form.plctxt
\i (00:02:01) FORM plctxt filename placement_pin1.txt
\i (00:02:01) FORM plctxt pin_1 YES
\i (00:02:03) FORM plctxt execute
\t (00:02:03) Starting Place symbols by text file...
\i (00:03:00) FORM plctxt cancel
\i (00:03:01) setwindow pcb
\i (00:03:01) ifp
\i (00:08:23) zoom points
\t (00:08:23) Pick 1st corner of the new window.
\i (00:08:24) pick -39.0477 18.4053
\t (00:08:24) last pick: -39.0477 18.4053
\t (00:08:24) Pick to complete the window.
\i (00:08:25) pick 36.6072 -12.3041
\t (00:08:25) last pick: 36.6072 -12.3041
\t (00:08:25) Grids are drawn 0.4000, 0.4000 apart for enhanced viewability.
\i (00:08:25) trapsize 2765
\i (00:08:25) ifp
\i (00:08:47) pick grid -5.1468 -15.7168
\t (00:08:47) last pick: -5.1000 -15.7000
\i (00:08:48) roam y 96
\i (00:08:48) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:49) roam y 96
\i (00:08:50) roam y -96
\i (00:08:50) roam y -96
\i (00:08:50) roam y -96
\i (00:08:50) roam y -96
\i (00:08:50) roam y -96
\i (00:08:50) roam y -96
\i (00:08:50) roam y -96
\i (00:08:50) roam y -96
\i (00:08:50) roam y -96
\i (00:08:50) roam y -96
\i (00:08:50) roam y -96
\i (00:08:50) roam y -96
\i (00:08:50) roam y -96
\i (00:08:50) roam y -96
\i (00:08:50) roam y -96
\i (00:08:50) roam y -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:51) roam x -96
\i (00:08:52) roam x -96
\i (00:08:52) roam x -96
\i (00:08:54) show element
\i (00:11:26) pick grid -57.0313 -82.5654
\t (00:11:26) last pick: -57.0000 -82.6000
\i (00:11:28) zoom out
\i (00:11:28) setwindow pcb
\i (00:11:28) zoom out -70.2487 -91.3033
\t (00:11:28) Grids are drawn 0.8000, 0.8000 apart for enhanced viewability.
\i (00:11:28) trapsize 5530
\i (00:11:29) zoom out
\i (00:11:29) setwindow pcb
\i (00:11:29) zoom out -70.2488 -91.3034
\t (00:11:29) Grids are drawn 1.6000, 1.6000 apart for enhanced viewability.
\i (00:11:29) trapsize 11061
\i (00:11:29) zoom out
\i (00:11:29) setwindow pcb
\i (00:11:29) zoom out -70.2487 -91.3033
\t (00:11:29) Grids are drawn 3.2000, 3.2000 apart for enhanced viewability.
\i (00:11:29) trapsize 22121
\i (00:11:45) show element
\i (00:11:50) setwindow form.find
\i (00:11:50) FORM find shapes YES
\i (00:11:52) setwindow pcb
\i (00:11:52) pick grid -88.6647 4.0949
\t (00:11:52) last pick: -88.7000 4.1000
\i (00:15:10) odb_out
\i (00:15:18) fillin no
(00:15:18) Loading mfg.cxt
\i (00:15:31) exit
\e (00:15:32) Do you want to save the changes you made to pc049a_lemo_db_4l_13.brd?
\i (00:15:35) fillin no
\t (00:15:38) Journal end - Thu Apr 14 13:39:13 2016
design_files/worklib/pc049a_toplevel/physical/allegro.jrl
View file @ 2f031cf3
\t (46:40:47) allegro 16.6-2015 S055 (v16-6-112EH) Linux I32 \t (00:00:03) allegro 16.6-2015 S055 (v16-6-112EH) Linux I32
\t (46:40:47) Journal start - Thu Feb 18 12:00:53 2016 \t (00:00:03) Journal start - Fri Sep 16 12:54:12 2016
\t (46:40:47) Host=fortis.phy.bris.ac.uk User=phdgc Pid=27642 CPUs=4 \t (00:00:03) Host=fortis.phy.bris.ac.uk User=phdgc Pid=7639 CPUs=4
\t (46:40:47) CmdLine= /software/CAD/Cadence/2015-16/RHELx86/SPB_16.60.055//tools/pcb/bin/allegro.exe \t (00:00:03) CmdLine= /software/CAD/Cadence/2015-16/RHELx86/SPB_16.60.055/tools/pcb/bin/allegro.exe -proj /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/Git/maroc_csa/design_files/pc049a_toplevel.cpm -product Concept_HDL_studio -mpssession phdgc_ProjectMgr29900 -mpshost fortis.phy.bris.ac.uk
\t (46:40:47) \t (00:00:03)
\d (46:40:47) Design opened: /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/physical/pc049a_toplevel_52.brd \t (00:00:04) Opening existing design...
\i (46:40:47) ifp \d (00:00:04) Design opened: /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/Git/maroc_csa/design_files/worklib/pc049a_toplevel/physical/pc049a_toplevel_52.brd
\i (46:40:56) opencd /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_db/physical/pc049a_lemo_db_12.brd \i (00:00:04) trapsize 17320
\t (46:40:57) Opening existing design... \i (00:00:04) trapsize 17755
\t (46:40:57) Grids are drawn 0.8000, 0.8000 apart for enhanced viewability. \i (00:00:05) trapsize 15373
\i (46:40:57) trapsize 7128 \i (00:00:05) trapsize 15373
\t (46:40:57) Journal end - Thu Feb 18 12:01:03 2016 \i (00:00:05) etchedit
\i (00:00:10) setwindow form.find
\i (00:00:10) FORM find name_type Net
\i (00:00:11) FORM find find_by_name
\i (00:00:17) setwindow form.findname
\i (00:00:17) FORM findname namefilter p1v2*
\i (00:00:18) FORM findname objlist P1v2
\i (00:00:20) FORM findname select
\i (00:00:20) setwindow pcb
\i (00:00:20) trapsize 1971
\i (00:00:24) prepopup 32.3248 89.9984
\i (00:00:26) pick grid 30.4327 87.6726
\t (00:00:26) last pick: 30.4300 87.6700
\i (00:00:28) pick grid 24.0467 94.2162
\t (00:00:28) last pick: 24.0500 94.2200
\i (00:00:36) zoom out
\i (00:00:36) setwindow pcb
\i (00:00:36) zoom out 44.1506 93.7826
\i (00:00:36) trapsize 3942
\i (00:00:59) pick grid 23.8102 93.9403
\t (00:00:59) last pick: 23.8100 93.9400
\i (00:01:13) pick grid 19.8683 104.5047
\t (00:01:13) last pick: 19.8700 104.5000
\i (00:02:28) xNet P3v3
\i (00:02:28) xname_flush
\i (00:02:28) trapsize 13737
\i (00:03:45) setwindow form.findname
\i (00:03:45) FORM findname namefilter p3v3
\i (00:03:47) FORM findname objlist P3v3
\i (00:03:48) FORM findname destlist P1V2
\i (00:03:50) FORM findname select
\i (00:03:50) setwindow pcb
\i (00:03:50) trapsize 13737
\i (00:03:56) zoom in
\i (00:03:56) setwindow pcb
\i (00:03:56) zoom in 43.0696 70.6481
\i (00:03:56) trapsize 6868
\i (00:03:56) zoom in
\i (00:03:56) setwindow pcb
\i (00:03:56) zoom in 43.0696 70.6481
\i (00:03:56) trapsize 3434
\i (00:03:58) roam y -96
\i (00:03:58) roam y -96
\i (00:03:58) roam y -96
\i (00:03:58) roam y -96
\i (00:03:58) roam y -96
\i (00:03:58) roam y -96
\i (00:03:58) roam y -96
\i (00:03:58) roam y -96
\i (00:04:04) pick grid 12.5736 104.4927
\t (00:04:04) last pick: 12.5700 104.4900
\i (00:05:04) setwindow form.findname
\i (00:05:04) FORM findname objtype Symbol (or Pin)
\i (00:05:07) FORM findname namefilter lk1
\i (00:05:09) FORM findname objlist Lk1
\i (00:05:10) FORM findname select
\i (00:05:10) setwindow pcb
\i (00:05:10) trapsize 490
\i (00:05:12) zoom out
\i (00:05:12) setwindow pcb
\i (00:05:12) zoom out 59.2736 20.5242
\i (00:05:12) trapsize 980
\i (00:05:37) setwindow form.findname
\i (00:05:37) FORM findname namefilter p3v3
\i (00:05:40) FORM findname objtype Net
\i (00:05:41) FORM findname objlist P3v3
\i (00:05:42) FORM findname select
\i (00:05:42) setwindow pcb
\i (00:05:42) trapsize 13737
\i (00:05:44) zoom points
\t (00:05:44) Pick 1st corner of the new window.
\i (00:05:45) pick -2.2625 117.3538
\t (00:05:45) last pick: -2.2625 117.3538
\t (00:05:45) Pick to complete the window.
\i (00:05:46) pick 39.4979 82.1871
\t (00:05:46) last pick: 39.4979 82.1871
\i (00:05:46) trapsize 2290
\i (00:05:46) etchedit
\i (00:06:23) roam y 96
\i (00:06:23) roam y 96
\i (00:06:23) roam y 96
\i (00:06:23) roam y 96
\i (00:06:23) roam y 96
\i (00:06:23) roam y 96
\i (00:06:24) roam y 96
\i (00:06:24) roam y 96
\i (00:06:24) roam y 96
\i (00:06:24) roam y 96
\i (00:06:24) roam x 96
\i (00:06:24) roam x 96
\i (00:06:25) roam x 96
\i (00:06:25) roam x 96
\i (00:06:25) roam y 96
\i (00:06:25) roam y 96
\i (00:06:25) roam y 96
\i (00:06:25) roam y 96
\i (00:06:25) roam y 96
\i (00:06:25) roam y 96
\i (00:06:26) roam y 96
\i (00:06:26) roam y 96
\i (00:06:26) roam y 96
\i (00:06:26) roam y 96
\i (00:06:26) roam y 96
\i (00:06:26) roam y 96
\i (00:06:26) roam y 96
\i (00:06:26) roam y 96
\i (00:06:26) roam y 96
\i (00:06:26) roam y 96
\i (00:06:27) roam y 96
\i (00:06:27) roam y 96
\i (00:06:27) roam y 96
\i (00:06:27) roam y 96
\i (00:15:02) setwindow form.find
\i (00:15:02) FORM find find_name P4V6
\i (00:15:02) setwindow pcb
\i (00:15:02) trapsize 1660
\i (00:15:08) zoom out
\i (00:15:08) setwindow pcb
\i (00:15:08) zoom out 65.8556 6.8565
\i (00:15:08) trapsize 3319
\i (00:22:54) setwindow form.vf_vis
\i (00:22:54) FORM vf_vis 10 all_colorvisible YES
\i (00:23:04) setwindow form.find
\i (00:23:04) FORM find symbols YES
\i (00:23:10) setwindow pcb
\i (00:23:10) prepopup 103.0290 14.2912
\i (00:23:11) pick grid 104.6221 17.8094
\t (00:23:11) last pick: 104.6200 17.8100
\i (00:23:12) show element
\i (00:23:15) setwindow form.find
\i (00:23:15) FORM find symbols YES
\i (00:23:40) setwindow pcb
\i (00:23:40) xrefdes R8.2
\i (00:23:40) xname_flush
\i (00:23:40) trapsize 182
\i (00:23:49) zoom out
\i (00:23:49) setwindow pcb
\i (00:23:49) zoom out 75.2600 -1.3036
\i (00:23:49) trapsize 364
\i (05:39:55) exit
\e (05:39:55) Do you want to save the changes you made to pc049a_toplevel_52.brd?
\i (05:39:58) fillin no
\t (05:39:59) Journal end - Fri Sep 16 18:34:08 2016
design_files/worklib/pc049a_toplevel/physical/allegro.jrl,1
View file @ 2f031cf3
\t (00:00:05) allegro 16.6-2015 S055 (v16-6-112EH) Linux I32 \t (00:00:05) allegro 16.6-2015 S055 (v16-6-112EH) Linux I32
\t (00:00:05) Journal start - Tue Feb 2 17:46:55 2016 \t (00:00:05) Journal start - Fri Sep 16 12:48:07 2016
\t (00:00:05) Host=fortis.phy.bris.ac.uk User=phdgc Pid=3330 CPUs=4 \t (00:00:05) Host=fortis.phy.bris.ac.uk User=phdgc Pid=7399 CPUs=4
\t (00:00:05) CmdLine= /software/CAD/Cadence/2015-16/RHELx86/SPB_16.60.055//tools/pcb/bin/allegro.exe \t (00:00:05) CmdLine= /software/CAD/Cadence/2015-16/RHELx86/SPB_16.60.055//tools/pcb/bin/allegro.exe pc049a_toplevel_52.brd
\t (00:00:05) \t (00:00:05)
\t (00:00:07) Opening existing design... \t (00:00:07) Opening existing design...
\d (00:00:07) Design opened: /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/physical/pc049a_toplevel_52.brd \d (00:00:07) Design opened: /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/Git/maroc_csa/design_files/worklib/pc049a_toplevel/physical/pc049a_toplevel_52.brd
\i (00:00:08) trapsize 20270 \i (00:00:07) trapsize 17320
\i (00:00:08) trapsize 19784 \i (00:00:07) trapsize 17755
\i (00:00:08) trapsize 20354 \i (00:00:08) trapsize 15373
\i (00:00:08) trapsize 17283 \i (00:00:08) trapsize 15373
\i (00:00:08) trapsize 17283 \i (00:00:09) etchedit
\i (00:00:09) ifp \i (00:00:12) zoom points
\i (00:00:11) open \t (00:00:12) Pick 1st corner of the new window.
\i (00:00:23) fillin "/projects/HEP_Instrumentation/cad/designs/uob-hep-pc050a/trunk/design_files/worklib/pc050a_clock_board_40mhz/physical/pc050a_clock_board_40mhz_08.brd" \i (00:00:13) pick 7.7680 119.6919
\i (00:00:23) cd "/projects/HEP_Instrumentation/cad/designs/uob-hep-pc050a/trunk/design_files/worklib/pc050a_clock_board_40mhz/physical" \t (00:00:13) last pick: 7.7680 119.6919
\t (00:00:23) Opening existing design... \t (00:00:13) Pick to complete the window.
\t (00:00:23) Grids are drawn 0.6400, 0.6400 apart for enhanced viewability. \i (00:00:13) pick 36.3611 85.2573
\i (00:00:23) trapsize 4754 \t (00:00:13) last pick: 36.3611 85.2573
\t (00:00:23) Journal end - Tue Feb 2 17:47:13 2016 \i (00:00:13) trapsize 2185
\i (00:00:13) etchedit
\i (00:00:16) show element
\i (00:00:19) setwindow form.find
\i (00:00:19) FORM find all_off
\i (00:00:20) FORM find pins YES
\i (00:01:10) setwindow pcb
\i (00:01:10) trapsize 2457
\i (00:01:51) exit
\e (00:01:51) Do you want to save the changes you made to pc049a_toplevel_52.brd?
\i (00:01:53) fillin no
\t (00:01:53) Journal end - Fri Sep 16 12:49:55 2016
design_files/worklib/pc049a_toplevel/sch_1/module_order.dat
View file @ 2f031cf3
Version 15.0 Version 15.0
START_MODULEORDER START_MODULEORDER
@uob_hep_pc049a_lib.pc049a_toplevel(sch_1) 0 1 1 11 0 @uob_hep_pc049a_lib.pc049a_toplevel(sch_1) 0 1 1 11 0
@uob_hep_pc049a_lib.pc049a_toplevel(sch_1):page1_i3@uob_hep_pc049a_lib.pc043c_single_maroc(sch_1) 0 1 12 3 0 @uob_hep_pc049a_lib.pc049a_toplevel(sch_1):page1_i3@uob_hep_pc049a_lib.pc043c_single_maroc(sch_1) 0 0 12 3 0
END_MODULEORDER END_MODULEORDER
firmware/IPBus/firmware/Manifest.py
View file @ 2f031cf3
modules = { "local" : ["./ethernet/cfg" , "ipbus_core/cfg", "slaves/cfg" ] } modules = { "local" : ["./ethernet/cfg" , "./ipbus_core/cfg", "./slaves/cfg" , "./sim/cfg" ] }
firmware/IPBus/firmware/ethernet/cfg/Manifest.py
View file @ 2f031cf3
...@@ -6,10 +6,11 @@ files = [ ...@@ -6,10 +6,11 @@ files = [
"../../ethernet/coregen/gig_eth_pcs_pma_v11_4.xco", "../../ethernet/coregen/gig_eth_pcs_pma_v11_4.xco",
"../hdl/eth_s6_1000basex.vhd", "../hdl/eth_s6_1000basex.vhd",
"../hdl/emac_hostbus_decl.vhd", "../hdl/emac_hostbus_decl.vhd",
"../../../../work/ipcore_dir/gig_eth_pcs_pma_v11_4/example_design/gig_eth_pcs_pma_v11_4_block.vhd" , "../../../../ipcore_dir/gig_eth_pcs_pma_v11_4/example_design/gig_eth_pcs_pma_v11_4_block.vhd" ,
"../../../../work/ipcore_dir/gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_transceiver_A.vhd", "../../../../ipcore_dir/gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_transceiver_A.vhd",
"../../../../work/ipcore_dir/gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard.vhd", "../../../../ipcore_dir/gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard.vhd",
"../../../../work/ipcore_dir/gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard_tile.vhd" "../../../../ipcore_dir/gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard_tile.vhd",
"../sim/eth_mac_sim.vhd"
] ]
......
firmware/IPBus/firmware/ethernet/coregen/_xmsgs/cg.xmsgs
View file @ 2f031cf3
...@@ -11,7 +11,7 @@ ...@@ -11,7 +11,7 @@
<msg type="warning" file="sim" num="100" delta="old" >The Simulation File Type &lt;<arg fmt="%s" index="1">Behavioral</arg>&gt; is not valid for this core. Overriding with File Type &lt;<arg fmt="%s" index="2">Structural</arg>&gt;. <msg type="warning" file="sim" num="100" delta="old" >The Simulation File Type &lt;<arg fmt="%s" index="1">Behavioral</arg>&gt; is not valid for this core. Overriding with File Type &lt;<arg fmt="%s" index="2">Structural</arg>&gt;.
</msg> </msg>
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">VHDL simulation file type &apos;Behavioral&apos; is not valid for this core. Overriding with simulation file type &apos;Structural&apos;.</arg> <msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Verilog simulation file type &apos;Behavioral&apos; is not valid for this core. Overriding with simulation file type &apos;Structural&apos;.</arg>
</msg> </msg>
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named &apos;gig_eth_pcs_pma_v11_4&apos; already exists in the project. Output products for this core may be overwritten.</arg> <msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named &apos;gig_eth_pcs_pma_v11_4&apos; already exists in the project. Output products for this core may be overwritten.</arg>
...@@ -26,10 +26,10 @@ ...@@ -26,10 +26,10 @@
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">BlackBox generator run option &apos;-p&apos; found multiple times. Only the first occurence is considered.</arg> <msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">BlackBox generator run option &apos;-p&apos; found multiple times. Only the first occurence is considered.</arg>
</msg> </msg>
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">VHDL simulation file type &apos;Behavioral&apos; is not valid for this core. Overriding with simulation file type &apos;Structural&apos;.</arg> <msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Verilog simulation file type &apos;Behavioral&apos; is not valid for this core. Overriding with simulation file type &apos;Structural&apos;.</arg>
</msg> </msg>
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Overwriting existing file /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBus/firmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4/doc/pg047-gig-eth-pcs-pma.pdf with file from view xilinx_documentation</arg> <msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Overwriting existing file /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/Git/maroc_csa/firmware/IPBus/firmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4/doc/pg047-gig-eth-pcs-pma.pdf with file from view xilinx_documentation</arg>
</msg> </msg>
<msg type="info" file="sim" num="949" delta="old" >Finished generation of ASY schematic symbol. <msg type="info" file="sim" num="949" delta="old" >Finished generation of ASY schematic symbol.
......
firmware/IPBus/firmware/ethernet/coregen/_xmsgs/pn_parser.xmsgs
View file @ 2f031cf3
...@@ -8,7 +8,7 @@ ...@@ -8,7 +8,7 @@
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --> <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<messages> <messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBus/firmware/ethernet/coregen/gig_eth_pcs_pma_v11_4.vhd&quot; into library work</arg> <msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/Git/maroc_csa/firmware/IPBus/firmware/ethernet/coregen/gig_eth_pcs_pma_v11_4.v&quot; into library work</arg>
</msg> </msg>
</messages> </messages>
......
firmware/IPBus/firmware/ethernet/coregen/coregen.log
View file @ 2f031cf3
...@@ -4,8 +4,8 @@ WARNING:sim:100 - The Simulation File Type <Behavioral> is not valid for this ...@@ -4,8 +4,8 @@ WARNING:sim:100 - The Simulation File Type <Behavioral> is not valid for this
Applying current project options... Applying current project options...
Finished applying current project options. Finished applying current project options.
Resolving generics for 'gig_eth_pcs_pma_v11_4'... Resolving generics for 'gig_eth_pcs_pma_v11_4'...
WARNING:sim - VHDL simulation file type 'Behavioral' is not valid for this core. WARNING:sim - Verilog simulation file type 'Behavioral' is not valid for this
Overriding with simulation file type 'Structural'. core. Overriding with simulation file type 'Structural'.
WARNING:sim - A core named 'gig_eth_pcs_pma_v11_4' already exists in the WARNING:sim - A core named 'gig_eth_pcs_pma_v11_4' already exists in the
project. Output products for this core may be overwritten. project. Output products for this core may be overwritten.
Applying external generics to 'gig_eth_pcs_pma_v11_4'... Applying external generics to 'gig_eth_pcs_pma_v11_4'...
...@@ -19,17 +19,17 @@ WARNING:sim - BlackBox generator run option '-p' found multiple times. Only the ...@@ -19,17 +19,17 @@ WARNING:sim - BlackBox generator run option '-p' found multiple times. Only the
first occurence is considered. first occurence is considered.
Running synthesis for 'gig_eth_pcs_pma_v11_4' Running synthesis for 'gig_eth_pcs_pma_v11_4'
Running ngcbuild... Running ngcbuild...
Writing VHO instantiation template for 'gig_eth_pcs_pma_v11_4'... Writing VEO instantiation template for 'gig_eth_pcs_pma_v11_4'...
WARNING:sim - VHDL simulation file type 'Behavioral' is not valid for this core. WARNING:sim - Verilog simulation file type 'Behavioral' is not valid for this
Overriding with simulation file type 'Structural'. core. Overriding with simulation file type 'Structural'.
Writing VHDL structural simulation model for 'gig_eth_pcs_pma_v11_4'... Writing Verilog structural simulation model for 'gig_eth_pcs_pma_v11_4'...
WARNING:sim - Overwriting existing file WARNING:sim - Overwriting existing file
/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBus /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/Git/maroc_csa/firmwa
/firmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4/doc/pg047-gig-eth-pc re/IPBus/firmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4/doc/pg047-gi
s-pma.pdf with file from view xilinx_documentation g-eth-pcs-pma.pdf with file from view xilinx_documentation
Delivered 2 files into directory Delivered 2 files into directory
/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBus/fi /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/Git/maroc_csa/firmware/
rmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4 IPBus/firmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4
Generating ASY schematic symbol... Generating ASY schematic symbol...
INFO:sim:949 - Finished generation of ASY schematic symbol. INFO:sim:949 - Finished generation of ASY schematic symbol.
Generating SYM schematic symbol for 'gig_eth_pcs_pma_v11_4'... Generating SYM schematic symbol for 'gig_eth_pcs_pma_v11_4'...
...@@ -38,38 +38,38 @@ Generating ISE project... ...@@ -38,38 +38,38 @@ Generating ISE project...
XCO file found: gig_eth_pcs_pma_v11_4.xco XCO file found: gig_eth_pcs_pma_v11_4.xco
XMDF file found: gig_eth_pcs_pma_v11_4_xmdf.tcl XMDF file found: gig_eth_pcs_pma_v11_4_xmdf.tcl
Adding Adding
/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBus/fi /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/Git/maroc_csa/firmware/
rmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4.asy -view all -origin_type IPBus/firmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4.asy -view all
imported -origin_type imported
Adding Adding
/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBus/fi /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/Git/maroc_csa/firmware/
rmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4.ngc -view all -origin_type IPBus/firmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4.ngc -view all
created -origin_type created
Checking file Checking file
"/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBus/f "/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/Git/maroc_csa/firmware
irmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4.ngc" for project device /IPBus/firmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4.ngc" for project
match ... device match ...
File File
"/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBus/f "/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/Git/maroc_csa/firmware
irmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4.ngc" device information /IPBus/firmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4.ngc" device
matches project device. information matches project device.
Adding Adding
/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBus/fi /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/Git/maroc_csa/firmware/
rmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4.sym -view all -origin_type IPBus/firmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4.sym -view all
imported -origin_type imported
Adding Adding
/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBus/fi /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/Git/maroc_csa/firmware/
rmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4.vhd -view all -origin_type IPBus/firmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4.v -view all
created -origin_type created
INFO:HDLCompiler:1061 - Parsing VHDL file INFO:HDLCompiler:1845 - Analyzing Verilog file
"/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBu "/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/Git/maroc_csa/firmw
s/firmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4.vhd" into library are/IPBus/firmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4.v" into
work library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully. INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding Adding
/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBus/fi /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/Git/maroc_csa/firmware/
rmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4.vho -view all -origin_type IPBus/firmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4.veo -view all
imported -origin_type imported
INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off. INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
Please set the new top explicitly by running the "project set top" command. Please set the new top explicitly by running the "project set top" command.
To re-calculate the new top automatically, set the "Auto Implementation Top" To re-calculate the new top automatically, set the "Auto Implementation Top"
......
firmware/IPBus/firmware/ethernet/coregen/gen_gig_eth_pcs_pma_v11_4.tcl
View file @ 2f031cf3
...@@ -22,7 +22,7 @@ proc findRtfPath { relativePath } { ...@@ -22,7 +22,7 @@ proc findRtfPath { relativePath } {
source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
set result [ run_cg_regen "gig_eth_pcs_pma_v11_4" xc6slx100t-3fgg484 VHDL CURRENT ] set result [ run_cg_regen "gig_eth_pcs_pma_v11_4" xc6slx100t-3fgg484 Verilog CURRENT ]
if { $result == 0 } { if { $result == 0 } {
puts "Core Generator regen command completed successfully." puts "Core Generator regen command completed successfully."
......
firmware/IPBus/firmware/ethernet/coregen/gen_tri_mode_eth_mac_v5_4.tcl
View file @ 2f031cf3
...@@ -22,7 +22,7 @@ proc findRtfPath { relativePath } { ...@@ -22,7 +22,7 @@ proc findRtfPath { relativePath } {
source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
set result [ run_cg_regen "tri_mode_eth_mac_v5_4" xc6slx100t-3fgg484 VHDL CURRENT ] set result [ run_cg_regen "tri_mode_eth_mac_v5_4" xc6slx45t-3fgg484 Verilog CURRENT ]
if { $result == 0 } { if { $result == 0 } {
puts "Core Generator regen command completed successfully." puts "Core Generator regen command completed successfully."
......
firmware/IPBus/firmware/ethernet/coregen/gig_eth_pcs_pma_v11_4.ngc
View file @ 2f031cf3
This source diff could not be displayed because it is too large. You can view the blob instead.
firmware/IPBus/firmware/ethernet/coregen/gig_eth_pcs_pma_v11_4.sym
View file @ 2f031cf3
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="gig_eth_pcs_pma_v11_4"> <symbol version="7" name="gig_eth_pcs_pma_v11_4">
<symboltype>BLOCK</symboltype> <symboltype>BLOCK</symboltype>
<timestamp>2015-3-23T15:7:50</timestamp> <timestamp>2016-10-6T13:44:10</timestamp>
<pin polarity="Input" x="0" y="80" name="reset" /> <pin polarity="Input" x="0" y="80" name="reset" />
<pin polarity="Input" x="0" y="176" name="userclk" /> <pin polarity="Input" x="0" y="176" name="userclk" />
<pin polarity="Input" x="0" y="208" name="userclk2" /> <pin polarity="Input" x="0" y="208" name="userclk2" />
......
firmware/IPBus/firmware/ethernet/coregen/gig_eth_pcs_pma_v11_4.xco
View file @ 2f031cf3
############################################################## ##############################################################
# #
# Xilinx Core Generator version 14.7 # Xilinx Core Generator version 14.7
# Date: Mon Mar 23 15:07:18 2015 # Date: Thu Oct 6 13:43:20 2016
# #
############################################################## ##############################################################
# #
...@@ -21,7 +21,7 @@ SET addpads = false ...@@ -21,7 +21,7 @@ SET addpads = false
SET asysymbol = true SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false SET createndf = false
SET designentry = VHDL SET designentry = Verilog
SET device = xc6slx100t SET device = xc6slx100t
SET devicefamily = spartan6 SET devicefamily = spartan6
SET flowvendor = Foundation_ISE SET flowvendor = Foundation_ISE
...@@ -32,8 +32,8 @@ SET package = fgg484 ...@@ -32,8 +32,8 @@ SET package = fgg484
SET removerpms = false SET removerpms = false
SET simulationfiles = Behavioral SET simulationfiles = Behavioral
SET speedgrade = -3 SET speedgrade = -3
SET verilogsim = false SET verilogsim = true
SET vhdlsim = true SET vhdlsim = false
# END Project Options # END Project Options
# BEGIN Select # BEGIN Select
SELECT Ethernet_1000BASE-X_PCS/PMA_or_SGMII xilinx.com:ip:gig_eth_pcs_pma:11.4 SELECT Ethernet_1000BASE-X_PCS/PMA_or_SGMII xilinx.com:ip:gig_eth_pcs_pma:11.4
...@@ -53,4 +53,4 @@ CSET transceiver_tile=A ...@@ -53,4 +53,4 @@ CSET transceiver_tile=A
MISC pkg_timestamp=2012-06-05T17:19:16Z MISC pkg_timestamp=2012-06-05T17:19:16Z
# END Extra information # END Extra information
GENERATE GENERATE
# CRC: f804edf0 # CRC: 3531b627
firmware/IPBus/firmware/ethernet/coregen/gig_eth_pcs_pma_v11_4.xise
View file @ 2f031cf3
...@@ -19,8 +19,8 @@ ...@@ -19,8 +19,8 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/> <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file> </file>
<file xil_pn:name="gig_eth_pcs_pma_v11_4.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="gig_eth_pcs_pma_v11_4.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/> <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/> <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
...@@ -51,8 +51,8 @@ ...@@ -51,8 +51,8 @@
<!-- --> <!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="gig_eth_pcs_pma_v11_4" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_DesignName" xil_pn:value="gig_eth_pcs_pma_v11_4" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-03-23T15:07:54" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-10-06T14:44:25" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="764184409318772D6D4DE6B130630AAA" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="D7462CCD31FB6BC6D069E82F5F6B1F91" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties> </properties>
......
firmware/IPBus/firmware/ethernet/coregen/gig_eth_pcs_pma_v11_4/implement/implement.bat
View file @ 2f031cf3
...@@ -33,5 +33,5 @@ trce -u -e 10 routed -o routed mapped.pcf ...@@ -33,5 +33,5 @@ trce -u -e 10 routed -o routed mapped.pcf
echo 'Running design through bitgen' echo 'Running design through bitgen'
bitgen -w routed.ncd routed mapped.pcf bitgen -w routed.ncd routed mapped.pcf
echo 'Running netgen to create gate level VHDL model' echo 'Running netgen to create gate level Verilog model'
netgen -ofmt vhdl -pcf mapped.pcf -sim -dir . -tm gig_eth_pcs_pma_v11_4_example_design -w routed.ncd routed.vhd netgen -ofmt verilog -pcf mapped.pcf -sim -dir . -tm gig_eth_pcs_pma_v11_4_example_design -w -sdf_anno false routed.ncd routed.v
firmware/IPBus/firmware/ethernet/coregen/gig_eth_pcs_pma_v11_4/implement/implement.sh
View file @ 2f031cf3
...@@ -33,6 +33,6 @@ trce -u -e 10 routed -o routed mapped.pcf ...@@ -33,6 +33,6 @@ trce -u -e 10 routed -o routed mapped.pcf
echo 'Running design through bitgen' echo 'Running design through bitgen'
bitgen -w routed.ncd routed mapped.pcf bitgen -w routed.ncd routed mapped.pcf
echo 'Running netgen to create gate level VHDL model' echo 'Running netgen to create gate level Verilog model'
netgen -ofmt vhdl -pcf mapped.pcf -sim -dir . -tm gig_eth_pcs_pma_v11_4_example_design -w routed.ncd routed.vhd netgen -ofmt verilog -pcf mapped.pcf -sim -dir . -tm gig_eth_pcs_pma_v11_4_example_design -w -sdf_anno false routed.ncd routed.v
firmware/IPBus/firmware/ethernet/coregen/gig_eth_pcs_pma_v11_4/implement/xst.prj
View file @ 2f031cf3
vhdl work ../example_design/gig_eth_pcs_pma_v11_4_sync_block.vhd verilog work ../example_design/gig_eth_pcs_pma_v11_4_sync_block.v
vhdl work ../example_design/gig_eth_pcs_pma_v11_4_reset_sync.vhd verilog work ../example_design/gig_eth_pcs_pma_v11_4_reset_sync.v
vhdl work ../example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard_tile.vhd verilog work ../example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard_tile.v
vhdl work ../example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard.vhd verilog work ../example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard.v
vhdl work ../example_design/transceiver/gig_eth_pcs_pma_v11_4_transceiver_A.vhd verilog work ../example_design/transceiver/gig_eth_pcs_pma_v11_4_transceiver_A.v
vhdl work ../example_design/gig_eth_pcs_pma_v11_4_tx_elastic_buffer.vhd verilog work ../example_design/gig_eth_pcs_pma_v11_4_tx_elastic_buffer.v
vhdl work ../example_design/gig_eth_pcs_pma_v11_4_block.vhd verilog work ../example_design/gig_eth_pcs_pma_v11_4_mod.v
vhdl work ../example_design/gig_eth_pcs_pma_v11_4_example_design.vhd verilog work ../example_design/gig_eth_pcs_pma_v11_4_block.v
verilog work ../example_design/gig_eth_pcs_pma_v11_4_example_design.v
firmware/IPBus/firmware/ethernet/coregen/gig_eth_pcs_pma_v11_4/simulation/functional/simulate_mti.do
View file @ 2f031cf3
...@@ -2,24 +2,24 @@ vlib work ...@@ -2,24 +2,24 @@ vlib work
vmap work work vmap work work
echo "Compiling Core Simulation Models" echo "Compiling Core Simulation Models"
vcom -work work ../../../gig_eth_pcs_pma_v11_4.vhd vlog -work work ../../../gig_eth_pcs_pma_v11_4.v
echo "Compiling Example Design" echo "Compiling Example Design"
vcom -2008 -work work \ vlog -work work \
../../example_design/gig_eth_pcs_pma_v11_4_sync_block.vhd \ ../../example_design/gig_eth_pcs_pma_v11_4_sync_block.v \
../../example_design/gig_eth_pcs_pma_v11_4_reset_sync.vhd \ ../../example_design/gig_eth_pcs_pma_v11_4_reset_sync.v \
../../example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard_tile.vhd \ ../../example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard_tile.v \
../../example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard.vhd \ ../../example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard.v \
../../example_design/transceiver/gig_eth_pcs_pma_v11_4_transceiver_A.vhd \ ../../example_design/transceiver/gig_eth_pcs_pma_v11_4_transceiver_A.v \
../../example_design/gig_eth_pcs_pma_v11_4_tx_elastic_buffer.vhd \ ../../example_design/gig_eth_pcs_pma_v11_4_tx_elastic_buffer.v \
../../example_design/gig_eth_pcs_pma_v11_4_block.vhd \ ../../example_design/gig_eth_pcs_pma_v11_4_block.v \
../../example_design/gig_eth_pcs_pma_v11_4_example_design.vhd ../../example_design/gig_eth_pcs_pma_v11_4_example_design.v
echo "Compiling Test Bench" echo "Compiling Test Bench"
vcom -work work -novopt ../stimulus_tb.vhd ../demo_tb.vhd vlog -work work -novopt ../stimulus_tb.v ../demo_tb.v
echo "Starting simulation" echo "Starting simulation"
vsim -voptargs="+acc" -t ps work.demo_tb vsim -voptargs="+acc" -L unisims_ver -L secureip -t ps work.demo_tb work.glbl
do wave_mti.do do wave_mti.do
run -all run -all
firmware/IPBus/firmware/ethernet/coregen/gig_eth_pcs_pma_v11_4/simulation/functional/simulate_ncsim.sh
View file @ 2f031cf3
...@@ -2,24 +2,24 @@ ...@@ -2,24 +2,24 @@
mkdir work mkdir work
echo "Compiling Core Simulation Models" echo "Compiling Core Simulation Models"
ncvhdl -v93 -work work ../../../gig_eth_pcs_pma_v11_4.vhd ncvlog -work work ../../../gig_eth_pcs_pma_v11_4.v
echo "Compiling Example Design" echo "Compiling Example Design"
ncvhdl -v93 -work work \ ncvlog -work work \
../../example_design/gig_eth_pcs_pma_v11_4_sync_block.vhd \ ../../example_design/gig_eth_pcs_pma_v11_4_sync_block.v \
../../example_design/gig_eth_pcs_pma_v11_4_reset_sync.vhd \ ../../example_design/gig_eth_pcs_pma_v11_4_reset_sync.v \
../../example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard_tile.vhd \ ../../example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard_tile.v \
../../example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard.vhd \ ../../example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard.v \
../../example_design/transceiver/gig_eth_pcs_pma_v11_4_transceiver_A.vhd \ ../../example_design/transceiver/gig_eth_pcs_pma_v11_4_transceiver_A.v \
../../example_design/gig_eth_pcs_pma_v11_4_tx_elastic_buffer.vhd \ ../../example_design/gig_eth_pcs_pma_v11_4_tx_elastic_buffer.v \
../../example_design/gig_eth_pcs_pma_v11_4_block.vhd \ ../../example_design/gig_eth_pcs_pma_v11_4_block.v \
../../example_design/gig_eth_pcs_pma_v11_4_example_design.vhd ../../example_design/gig_eth_pcs_pma_v11_4_example_design.v
echo "Compiling Test Bench" echo "Compiling Test Bench"
ncvhdl -v93 -work work ../stimulus_tb.vhd ../demo_tb.vhd ncvlog -work work ../stimulus_tb.v ../demo_tb.v
echo "Elaborating design" echo "Elaborating design"
ncelab -access +rw work.demo_tb:behav ncelab -access +rw work.demo_tb glbl
echo "Starting simulation" echo "Starting simulation"
ncsim -gui work.demo_tb:behav -input @"simvision -input wave_ncsim.sv" ncsim -gui work.demo_tb -input @"simvision -input wave_ncsim.sv"
firmware/IPBus/firmware/ethernet/coregen/gig_eth_pcs_pma_v11_4/simulation/functional/wave_ncsim.sv
View file @ 2f031cf3
...@@ -11,10 +11,10 @@ if {[catch {group new -name {System Signals} -overlay 0}] != ""} { ...@@ -11,10 +11,10 @@ if {[catch {group new -name {System Signals} -overlay 0}] != ""} {
group clear 0 end group clear 0 end
} }
group insert \ group insert \
:reset \ demo_tb.reset \
:brefclk_p \ demo_tb.brefclk_p \
:brefclk_n demo_tb.brefclk_n
:signal_detect0 \ demo_tb.signal_detect0 \
if {[catch {group new -name {Management I/F 0} -overlay 0}] != ""} { if {[catch {group new -name {Management I/F 0} -overlay 0}] != ""} {
group using {Management I/F} group using {Management I/F}
...@@ -23,8 +23,8 @@ if {[catch {group new -name {Management I/F 0} -overlay 0}] != ""} { ...@@ -23,8 +23,8 @@ if {[catch {group new -name {Management I/F 0} -overlay 0}] != ""} {
group clear 0 end group clear 0 end
} }
group insert \ group insert \
:dut.configuration_vector0 \ {demo_tb.dut.configuration_vector0[3:0]} \
:status_vector0 demo_tb.status_vector0
if {[catch {group new -name {Tx GMII 0} -overlay 0}] != ""} { if {[catch {group new -name {Tx GMII 0} -overlay 0}] != ""} {
group using {Tx GMII} group using {Tx GMII}
...@@ -33,9 +33,9 @@ if {[catch {group new -name {Tx GMII 0} -overlay 0}] != ""} { ...@@ -33,9 +33,9 @@ if {[catch {group new -name {Tx GMII 0} -overlay 0}] != ""} {
group clear 0 end group clear 0 end
} }
group insert \ group insert \
:gmii_txd0 \ {demo_tb.gmii_txd0[7:0]} \
:gmii_tx_en0 \ demo_tb.gmii_tx_en0 \
:gmii_tx_er0 demo_tb.gmii_tx_er0
if {[catch {group new -name {Rx GMII 0} -overlay 0}] != ""} { if {[catch {group new -name {Rx GMII 0} -overlay 0}] != ""} {
group using {Rx GMII} group using {Rx GMII}
...@@ -44,9 +44,9 @@ if {[catch {group new -name {Rx GMII 0} -overlay 0}] != ""} { ...@@ -44,9 +44,9 @@ if {[catch {group new -name {Rx GMII 0} -overlay 0}] != ""} {
group clear 0 end group clear 0 end
} }
group insert \ group insert \
:gmii_rxd0 \ {demo_tb.gmii_rxd0[7:0]} \
:gmii_rx_dv0 \ demo_tb.gmii_rx_dv0 \
:gmii_rx_er0 demo_tb.gmii_rx_er0
if {[catch {group new -name {Transceiver Tx 0} -overlay 0}] != ""} { if {[catch {group new -name {Transceiver Tx 0} -overlay 0}] != ""} {
group using {Transceiver Tx} group using {Transceiver Tx}
...@@ -55,8 +55,8 @@ if {[catch {group new -name {Transceiver Tx 0} -overlay 0}] != ""} { ...@@ -55,8 +55,8 @@ if {[catch {group new -name {Transceiver Tx 0} -overlay 0}] != ""} {
group clear 0 end group clear 0 end
} }
group insert \ group insert \
:txp0 \ demo_tb.txp0 \
:txn0 demo_tb.txn0
if {[catch {group new -name {Transceiver Rx 0} -overlay 0}] != ""} { if {[catch {group new -name {Transceiver Rx 0} -overlay 0}] != ""} {
group using {Transceiver Rx} group using {Transceiver Rx}
...@@ -65,8 +65,8 @@ if {[catch {group new -name {Transceiver Rx 0} -overlay 0}] != ""} { ...@@ -65,8 +65,8 @@ if {[catch {group new -name {Transceiver Rx 0} -overlay 0}] != ""} {
group clear 0 end group clear 0 end
} }
group insert \ group insert \
:rxp0 \ demo_tb.rxp0 \
:rxn0 demo_tb.rxn0
if {[catch {group new -name {Tx Monitor 0} -overlay 0}] != ""} { if {[catch {group new -name {Tx Monitor 0} -overlay 0}] != ""} {
group using {Tx Monitor} group using {Tx Monitor}
...@@ -75,10 +75,10 @@ if {[catch {group new -name {Tx Monitor 0} -overlay 0}] != ""} { ...@@ -75,10 +75,10 @@ if {[catch {group new -name {Tx Monitor 0} -overlay 0}] != ""} {
group clear 0 end group clear 0 end
} }
group insert \ group insert \
:stimulus_0.mon_tx_clk \ demo_tb.stimulus_0.mon_tx_clk \
:stimulus_0.tx_pdata \ {demo_tb.stimulus_0.tx_pdata[7:0]} \
:stimulus_0.tx_is_k \ demo_tb.stimulus_0.tx_is_k \
:stimulus_0.bitclock demo_tb.stimulus_0.bitclock
if {[catch {group new -name {Rx Stimulus 0} -overlay 0}] != ""} { if {[catch {group new -name {Rx Stimulus 0} -overlay 0}] != ""} {
group using {Rx Stimulus} group using {Rx Stimulus}
group set -overlay 0 group set -overlay 0
...@@ -86,11 +86,11 @@ if {[catch {group new -name {Rx Stimulus 0} -overlay 0}] != ""} { ...@@ -86,11 +86,11 @@ if {[catch {group new -name {Rx Stimulus 0} -overlay 0}] != ""} {
group clear 0 end group clear 0 end
} }
group insert \ group insert \
:stimulus_0.stim_rx_clk \ demo_tb.stimulus_0.stim_rx_clk \
:stimulus_0.rx_even \ demo_tb.stimulus_0.rx_even \
:stimulus_0.rx_pdata \ {demo_tb.stimulus_0.rx_pdata[7:0]} \
:stimulus_0.rx_is_k \ demo_tb.stimulus_0.rx_is_k \
:stimulus_0.rx_rundisp_pos demo_tb.stimulus_0.rx_rundisp_pos
if {[catch {group new -name {Test semaphores} -overlay 0}] != ""} { if {[catch {group new -name {Test semaphores} -overlay 0}] != ""} {
group using {Test semaphores} group using {Test semaphores}
...@@ -98,10 +98,10 @@ if {[catch {group new -name {Test semaphores} -overlay 0}] != ""} { ...@@ -98,10 +98,10 @@ if {[catch {group new -name {Test semaphores} -overlay 0}] != ""} {
group set -comment {} group set -comment {}
group clear 0 end group clear 0 end
} }
:configuration_finished \ demo_tb.configuration_finished \
:tx_monitor_finished0 \ demo_tb.tx_monitor_finished0 \
:rx_monitor_finished0 \ demo_tb.rx_monitor_finished0 \
:simulation_finished demo_tb.simulation_finished
# #
# Waveform windows # Waveform windows
# #
......
firmware/IPBus/firmware/ethernet/coregen/gig_eth_pcs_pma_v11_4_flist.txt
View file @ 2f031cf3
...@@ -2,34 +2,38 @@ ...@@ -2,34 +2,38 @@
_xmsgs/pn_parser.xmsgs _xmsgs/pn_parser.xmsgs
gig_eth_pcs_pma_v11_4/doc/gig_eth_pcs_pma_v11_4_vinfo.html gig_eth_pcs_pma_v11_4/doc/gig_eth_pcs_pma_v11_4_vinfo.html
gig_eth_pcs_pma_v11_4/doc/pg047-gig-eth-pcs-pma.pdf gig_eth_pcs_pma_v11_4/doc/pg047-gig-eth-pcs-pma.pdf
gig_eth_pcs_pma_v11_4/example_design/gig_eth_pcs_pma_v11_4_block.vhd gig_eth_pcs_pma_v11_4/example_design/gig_eth_pcs_pma_v11_4_block.v
gig_eth_pcs_pma_v11_4/example_design/gig_eth_pcs_pma_v11_4_example_design.ucf gig_eth_pcs_pma_v11_4/example_design/gig_eth_pcs_pma_v11_4_example_design.ucf
gig_eth_pcs_pma_v11_4/example_design/gig_eth_pcs_pma_v11_4_example_design.vhd gig_eth_pcs_pma_v11_4/example_design/gig_eth_pcs_pma_v11_4_example_design.v
gig_eth_pcs_pma_v11_4/example_design/gig_eth_pcs_pma_v11_4_reset_sync.vhd gig_eth_pcs_pma_v11_4/example_design/gig_eth_pcs_pma_v11_4_mod.v
gig_eth_pcs_pma_v11_4/example_design/gig_eth_pcs_pma_v11_4_sync_block.vhd gig_eth_pcs_pma_v11_4/example_design/gig_eth_pcs_pma_v11_4_reset_sync.v
gig_eth_pcs_pma_v11_4/example_design/gig_eth_pcs_pma_v11_4_tx_elastic_buffer.vhd gig_eth_pcs_pma_v11_4/example_design/gig_eth_pcs_pma_v11_4_sync_block.v
gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard.vhd gig_eth_pcs_pma_v11_4/example_design/gig_eth_pcs_pma_v11_4_tx_elastic_buffer.v
gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard.v
gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard.xco gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard.xco
gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard_tile.vhd gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard_tile.v
gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_transceiver_A.vhd gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_transceiver_A.v
gig_eth_pcs_pma_v11_4/gig_eth_pcs_pma_readme.txt gig_eth_pcs_pma_v11_4/gig_eth_pcs_pma_readme.txt
gig_eth_pcs_pma_v11_4/implement/example_design_xst.xcf gig_eth_pcs_pma_v11_4/implement/example_design_xst.xcf
gig_eth_pcs_pma_v11_4/implement/implement.bat gig_eth_pcs_pma_v11_4/implement/implement.bat
gig_eth_pcs_pma_v11_4/implement/implement.sh gig_eth_pcs_pma_v11_4/implement/implement.sh
gig_eth_pcs_pma_v11_4/implement/xst.prj gig_eth_pcs_pma_v11_4/implement/xst.prj
gig_eth_pcs_pma_v11_4/implement/xst.scr gig_eth_pcs_pma_v11_4/implement/xst.scr
gig_eth_pcs_pma_v11_4/simulation/demo_tb.vhd gig_eth_pcs_pma_v11_4/simulation/demo_tb.v
gig_eth_pcs_pma_v11_4/simulation/functional/simulate_mti.do gig_eth_pcs_pma_v11_4/simulation/functional/simulate_mti.do
gig_eth_pcs_pma_v11_4/simulation/functional/simulate_ncsim.sh gig_eth_pcs_pma_v11_4/simulation/functional/simulate_ncsim.sh
gig_eth_pcs_pma_v11_4/simulation/functional/simulate_vcs.sh
gig_eth_pcs_pma_v11_4/simulation/functional/ucli_commands.key
gig_eth_pcs_pma_v11_4/simulation/functional/vcs_session.tcl
gig_eth_pcs_pma_v11_4/simulation/functional/wave_mti.do gig_eth_pcs_pma_v11_4/simulation/functional/wave_mti.do
gig_eth_pcs_pma_v11_4/simulation/functional/wave_ncsim.sv gig_eth_pcs_pma_v11_4/simulation/functional/wave_ncsim.sv
gig_eth_pcs_pma_v11_4/simulation/stimulus_tb.vhd gig_eth_pcs_pma_v11_4/simulation/stimulus_tb.v
gig_eth_pcs_pma_v11_4.asy gig_eth_pcs_pma_v11_4.asy
gig_eth_pcs_pma_v11_4.gise gig_eth_pcs_pma_v11_4.gise
gig_eth_pcs_pma_v11_4.ngc gig_eth_pcs_pma_v11_4.ngc
gig_eth_pcs_pma_v11_4.sym gig_eth_pcs_pma_v11_4.sym
gig_eth_pcs_pma_v11_4.vhd gig_eth_pcs_pma_v11_4.v
gig_eth_pcs_pma_v11_4.vho gig_eth_pcs_pma_v11_4.veo
gig_eth_pcs_pma_v11_4.xco gig_eth_pcs_pma_v11_4.xco
gig_eth_pcs_pma_v11_4.xise gig_eth_pcs_pma_v11_4.xise
gig_eth_pcs_pma_v11_4_flist.txt gig_eth_pcs_pma_v11_4_flist.txt
......
firmware/IPBus/firmware/ethernet/coregen/gig_eth_pcs_pma_v11_4_xmdf.tcl
View file @ 2f031cf3
...@@ -43,7 +43,7 @@ utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_ ...@@ -43,7 +43,7 @@ utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_pma_v11_4/example_design/gig_eth_pcs_pma_v11_4_block.vhd utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_pma_v11_4/example_design/gig_eth_pcs_pma_v11_4_block.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount incr fcount
...@@ -51,23 +51,27 @@ utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_ ...@@ -51,23 +51,27 @@ utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_pma_v11_4/example_design/gig_eth_pcs_pma_v11_4_example_design.vhd utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_pma_v11_4/example_design/gig_eth_pcs_pma_v11_4_example_design.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_pma_v11_4/example_design/gig_eth_pcs_pma_v11_4_reset_sync.vhd utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_pma_v11_4/example_design/gig_eth_pcs_pma_v11_4_mod.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_pma_v11_4/example_design/gig_eth_pcs_pma_v11_4_sync_block.vhd utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_pma_v11_4/example_design/gig_eth_pcs_pma_v11_4_reset_sync.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_pma_v11_4/example_design/gig_eth_pcs_pma_v11_4_tx_elastic_buffer.vhd utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_pma_v11_4/example_design/gig_eth_pcs_pma_v11_4_sync_block.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard.vhd utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_pma_v11_4/example_design/gig_eth_pcs_pma_v11_4_tx_elastic_buffer.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount incr fcount
...@@ -75,11 +79,11 @@ utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_ ...@@ -75,11 +79,11 @@ utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard_tile.vhd utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard_tile.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_transceiver_A.vhd utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_transceiver_A.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount incr fcount
...@@ -107,7 +111,7 @@ utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_ ...@@ -107,7 +111,7 @@ utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_pma_v11_4/simulation/demo_tb.vhd utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_pma_v11_4/simulation/demo_tb.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount incr fcount
...@@ -119,6 +123,18 @@ utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_ ...@@ -119,6 +123,18 @@ utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_pma_v11_4/simulation/functional/simulate_vcs.sh
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_pma_v11_4/simulation/functional/ucli_commands.key
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_pma_v11_4/simulation/functional/vcs_session.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_pma_v11_4/simulation/functional/wave_mti.do utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_pma_v11_4/simulation/functional/wave_mti.do
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount incr fcount
...@@ -127,7 +143,7 @@ utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_ ...@@ -127,7 +143,7 @@ utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_pma_v11_4/simulation/stimulus_tb.vhd utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_pma_v11_4/simulation/stimulus_tb.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount incr fcount
...@@ -143,12 +159,12 @@ utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_ ...@@ -143,12 +159,12 @@ utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_
utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol
incr fcount incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_pma_v11_4.vhd utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_pma_v11_4.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
incr fcount incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_pma_v11_4.vho utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_pma_v11_4.veo
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
incr fcount incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_pma_v11_4.xco utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path gig_eth_pcs_pma_v11_4.xco
......
firmware/IPBus/firmware/ethernet/coregen/tmp/_xmsgs/netgen.xmsgs
View file @ 2f031cf3
...@@ -5,7 +5,7 @@ ...@@ -5,7 +5,7 @@
behavior or data corruption. It is strongly advised that behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. --> users do not edit the contents of this file. -->
<messages> <messages>
<msg type="info" file="NetListWriters" num="635" delta="old" >The generated VHDL netlist contains Xilinx <arg fmt="%s" index="1">UNISIM</arg> simulation primitives and has to be used with <arg fmt="%s" index="2">UNISIM</arg> library for correct compilation and simulation. <msg type="info" file="NetListWriters" num="633" delta="old" >The generated Verilog netlist contains Xilinx <arg fmt="%s" index="1">UNISIM</arg> simulation primitives and has to be used with <arg fmt="%s" index="2">UNISIM</arg> simulation library for correct compilation and simulation.
</msg> </msg>
</messages> </messages>
......
firmware/IPBus/firmware/ethernet/coregen/tmp/_xmsgs/pn_parser.xmsgs
View file @ 2f031cf3
...@@ -8,7 +8,7 @@ ...@@ -8,7 +8,7 @@
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --> <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<messages> <messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBus/firmware/ethernet/coregen/tri_mode_eth_mac_v5_4.vhd&quot; into library work</arg> <msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/Git/maroc_csa/firmware/IPBus/firmware/ethernet/coregen/gig_eth_pcs_pma_v11_4.vhd&quot; into library work</arg>
</msg> </msg>
</messages> </messages>
......
firmware/IPBus/firmware/ethernet/coregen/tri_mode_eth_mac_v5_4.sym
View file @ 2f031cf3
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="tri_mode_eth_mac_v5_4"> <symbol version="7" name="tri_mode_eth_mac_v5_4">
<symboltype>BLOCK</symboltype> <symboltype>BLOCK</symboltype>
<timestamp>2015-3-23T15:6:55</timestamp> <timestamp>2016-10-6T13:9:13</timestamp>
<pin polarity="Input" x="0" y="80" name="glbl_rstn" /> <pin polarity="Input" x="0" y="80" name="glbl_rstn" />
<pin polarity="Input" x="0" y="112" name="rx_axi_rstn" /> <pin polarity="Input" x="0" y="112" name="rx_axi_rstn" />
<pin polarity="Input" x="0" y="144" name="tx_axi_rstn" /> <pin polarity="Input" x="0" y="144" name="tx_axi_rstn" />
......
firmware/IPBus/firmware/ethernet/coregen/tri_mode_eth_mac_v5_4.xco
View file @ 2f031cf3
############################################################## ##############################################################
# #
# Xilinx Core Generator version 14.7 # Xilinx Core Generator version 14.7
# Date: Mon Mar 23 15:05:09 2015 # Date: Thu Oct 6 13:06:35 2016
# #
############################################################## ##############################################################
# #
...@@ -21,8 +21,8 @@ SET addpads = false ...@@ -21,8 +21,8 @@ SET addpads = false
SET asysymbol = true SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false SET createndf = false
SET designentry = VHDL SET designentry = Verilog
SET device = xc6slx100t SET device = xc6slx45t
SET devicefamily = spartan6 SET devicefamily = spartan6
SET flowvendor = Foundation_ISE SET flowvendor = Foundation_ISE
SET formalverification = false SET formalverification = false
...@@ -32,8 +32,8 @@ SET package = fgg484 ...@@ -32,8 +32,8 @@ SET package = fgg484
SET removerpms = false SET removerpms = false
SET simulationfiles = Behavioral SET simulationfiles = Behavioral
SET speedgrade = -3 SET speedgrade = -3
SET verilogsim = false SET verilogsim = true
SET vhdlsim = true SET vhdlsim = false
# END Project Options # END Project Options
# BEGIN Select # BEGIN Select
SELECT Tri_Mode_Ethernet_MAC xilinx.com:ip:tri_mode_eth_mac:5.4 SELECT Tri_Mode_Ethernet_MAC xilinx.com:ip:tri_mode_eth_mac:5.4
...@@ -55,4 +55,4 @@ CSET statistics_width=64bit ...@@ -55,4 +55,4 @@ CSET statistics_width=64bit
MISC pkg_timestamp=2012-06-05T21:10:47Z MISC pkg_timestamp=2012-06-05T21:10:47Z
# END Extra information # END Extra information
GENERATE GENERATE
# CRC: c525364d # CRC: bb83dd46
firmware/IPBus/firmware/ethernet/coregen/tri_mode_eth_mac_v5_4.xise
View file @ 2f031cf3
...@@ -19,8 +19,8 @@ ...@@ -19,8 +19,8 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/> <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file> </file>
<file xil_pn:name="tri_mode_eth_mac_v5_4.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="tri_mode_eth_mac_v5_4.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/> <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/> <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
...@@ -30,7 +30,7 @@ ...@@ -30,7 +30,7 @@
<properties> <properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/> <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx100t" xil_pn:valueState="non-default"/> <property xil_pn:name="Device" xil_pn:value="xc6slx45t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/> <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/> <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/> <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
...@@ -51,8 +51,8 @@ ...@@ -51,8 +51,8 @@
<!-- --> <!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="tri_mode_eth_mac_v5_4" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_DesignName" xil_pn:value="tri_mode_eth_mac_v5_4" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-03-23T15:06:59" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-10-06T14:09:25" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="CD43368B14E6CB253FE17B9286BF4EA1" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="DB4B85F8FB6FD06DF586EAFCFD4FD09B" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties> </properties>
......
firmware/IPBus/firmware/ethernet/coregen/tri_mode_eth_mac_v5_4/example_design/tri_mode_eth_mac_v5_4_example_design.ucf
View file @ 2f031cf3
# the part selection and associated pin choices (if any) are intended as # the part selection and associated pin choices (if any) are intended as
# an example for the family selected. Please refer to the User Guide # an example for the family selected. Please refer to the User Guide
# for more information about IO selection. # for more information about IO selection.
# part selected is spartan6 xc6slx100tfgg484 # part selected is spartan6 xc6slx45tfgg484
CONFIG PART = xc6slx16csg324-2; CONFIG PART = xc6slx45tfgg484-2;
# #
#### ####
...@@ -13,60 +13,65 @@ CONFIG PART = xc6slx16csg324-2; ...@@ -13,60 +13,65 @@ CONFIG PART = xc6slx16csg324-2;
## System level constraints ## System level constraints
########## GMII LOC CONSTRAINTS ########## ########## GMII LOC CONSTRAINTS ##########
########## SP601 Board ########## ########## SP605 Board ##########
NET clk_in_p LOC = K15 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE; NET clk_in_p LOC = K21 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
NET clk_in_n LOC = K16 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE; NET clk_in_n LOC = K22 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
Net glbl_rst LOC = N4 | IOSTANDARD = LVCMOS25 | TIG; Net glbl_rst LOC = H8 | IOSTANDARD = LVCMOS15 | TIG;
#### Module LEDs_8Bit constraints #### Module LEDs_8Bit constraints
Net frame_error LOC = A4 | IOSTANDARD = LVCMOS25; Net frame_error LOC = D17 | IOSTANDARD = LVCMOS25;
Net frame_errorn LOC = C4 | IOSTANDARD = LVCMOS25; Net frame_errorn LOC = AB4 | IOSTANDARD = LVCMOS25;
Net activity_flash LOC = C14 | IOSTANDARD = LVCMOS25; Net activity_flash LOC = D21 | IOSTANDARD = LVCMOS25;
Net activity_flashn LOC = E13 | IOSTANDARD = LVCMOS25; Net activity_flashn LOC = W15 | IOSTANDARD = LVCMOS25;
#### Module Push_Buttons_4Bit constraints #### Module Push_Buttons_4Bit constraints
Net update_speed LOC = P4 | IOSTANDARD = LVCMOS15; Net update_speed LOC = F3 | IOSTANDARD = LVCMOS15;
Net config_board LOC = F6 | IOSTANDARD = LVCMOS15; Net config_board LOC = G6 | IOSTANDARD = LVCMOS15;
Net pause_req_s LOC = E4 | IOSTANDARD = LVCMOS15; Net pause_req_s LOC = F5 | IOSTANDARD = LVCMOS15;
Net reset_error LOC = F5 | IOSTANDARD = LVCMOS15; Net reset_error LOC = C1 | IOSTANDARD = LVCMOS15;
#### Module DIP_Switches_4Bit constraints #### Module DIP_Switches_4Bit constraints
Net mac_speed<0> LOC = D14 | IOSTANDARD = LVCMOS25; Net mac_speed<0> LOC = C18 | IOSTANDARD = LVCMOS25;
Net mac_speed<1> LOC = E12 | IOSTANDARD = LVCMOS25; Net mac_speed<1> LOC = Y6 | IOSTANDARD = LVCMOS25;
Net gen_tx_data LOC = F12 | IOSTANDARD = LVCMOS25; Net gen_tx_data LOC = W6 | IOSTANDARD = LVCMOS25;
Net chk_tx_data LOC = V13 | IOSTANDARD = LVCMOS25 | TIG; Net chk_tx_data LOC = E4 | IOSTANDARD = LVCMOS25 | TIG;
Net phy_resetn LOC = L13 | IOSTANDARD = LVCMOS25 | TIG; Net phy_resetn LOC = J22 | IOSTANDARD = LVCMOS25 | TIG;
Net gmii_txd<0> LOC = F8 | IOSTANDARD = LVCMOS25; Net gmii_rxd<7> LOC = U22 | IOSTANDARD = LVCMOS25;
Net gmii_txd<1> LOC = G8 | IOSTANDARD = LVCMOS25; Net gmii_rxd<6> LOC = V21 | IOSTANDARD = LVCMOS25;
Net gmii_txd<2> LOC = A6 | IOSTANDARD = LVCMOS25; Net gmii_rxd<5> LOC = V22 | IOSTANDARD = LVCMOS25;
Net gmii_txd<3> LOC = B6 | IOSTANDARD = LVCMOS25; Net gmii_rxd<4> LOC = W20 | IOSTANDARD = LVCMOS25;
Net gmii_txd<4> LOC = E6 | IOSTANDARD = LVCMOS25; Net gmii_rxd<3> LOC = W22 | IOSTANDARD = LVCMOS25;
Net gmii_txd<5> LOC = F7 | IOSTANDARD = LVCMOS25; Net gmii_rxd<2> LOC = Y21 | IOSTANDARD = LVCMOS25;
Net gmii_txd<6> LOC = A5 | IOSTANDARD = LVCMOS25; Net gmii_rxd<1> LOC = Y22 | IOSTANDARD = LVCMOS25;
Net gmii_txd<7> LOC = C5 | IOSTANDARD = LVCMOS25; Net gmii_rxd<0> LOC = P19 | IOSTANDARD = LVCMOS25;
Net gmii_tx_en LOC = B8 | IOSTANDARD = LVCMOS25;
Net gmii_tx_er LOC = A8 | IOSTANDARD = LVCMOS25; Net gmii_txd<7> LOC = W12 | IOSTANDARD = LVCMOS25;
Net gmii_tx_clk LOC = A9 | IOSTANDARD = LVCMOS25; Net gmii_txd<6> LOC = Y12 | IOSTANDARD = LVCMOS25;
Net gmii_rxd<0> LOC = M14 | IOSTANDARD = LVCMOS25; Net gmii_txd<5> LOC = Y9 | IOSTANDARD = LVCMOS25;
Net gmii_rxd<1> LOC = U18 | IOSTANDARD = LVCMOS25; Net gmii_txd<4> LOC = AB9 | IOSTANDARD = LVCMOS25;
Net gmii_rxd<2> LOC = U17 | IOSTANDARD = LVCMOS25; Net gmii_txd<3> LOC = AA8 | IOSTANDARD = LVCMOS25;
Net gmii_rxd<3> LOC = T18 | IOSTANDARD = LVCMOS25; Net gmii_txd<2> LOC = AB8 | IOSTANDARD = LVCMOS25;
Net gmii_rxd<4> LOC = T17 | IOSTANDARD = LVCMOS25; Net gmii_txd<1> LOC = T10 | IOSTANDARD = LVCMOS25;
Net gmii_rxd<5> LOC = N16 | IOSTANDARD = LVCMOS25; Net gmii_txd<0> LOC = U10 | IOSTANDARD = LVCMOS25;
Net gmii_rxd<6> LOC = N15 | IOSTANDARD = LVCMOS25;
Net gmii_rxd<7> LOC = P18 | IOSTANDARD = LVCMOS25;
Net gmii_rx_dv LOC = N18 | IOSTANDARD = LVCMOS25; Net gmii_tx_en LOC = T8 | IOSTANDARD = LVCMOS25;
Net gmii_rx_er LOC = P17 | IOSTANDARD = LVCMOS25; Net gmii_tx_er LOC = U8 | IOSTANDARD = LVCMOS25;
Net gmii_rx_clk LOC = L16 | IOSTANDARD = LVCMOS25 | PERIOD = 8000 ps; Net gmii_tx_clk LOC = AB7 | IOSTANDARD = LVCMOS25;
Net gmii_rx_dv LOC = T22 | IOSTANDARD = LVCMOS25;
Net gmii_rx_er LOC = U20 | IOSTANDARD = LVCMOS25;
# P20 - GCLK7
Net gmii_rx_clk LOC = P20 | IOSTANDARD = LVCMOS25;
# lock to unused header # lock to unused header
Net serial_response LOC = A13 | IOSTANDARD = LVCMOS25; Net serial_response LOC = A20 | IOSTANDARD = LVCMOS25;
Net tx_statistics_s LOC = C13 | IOSTANDARD = LVCMOS25; Net tx_statistics_s LOC = B20 | IOSTANDARD = LVCMOS25;
Net rx_statistics_s LOC = C12 | IOSTANDARD = LVCMOS25; Net rx_statistics_s LOC = A19 | IOSTANDARD = LVCMOS25;
# #
...@@ -190,11 +195,11 @@ INST "gmii_tx_clk" SLEW = FAST; ...@@ -190,11 +195,11 @@ INST "gmii_tx_clk" SLEW = FAST;
# For more information on IDELAYCTRL and IODELAY, please # For more information on IDELAYCTRL and IODELAY, please
# refer to the Spartan-6 User Guide. # refer to the Spartan-6 User Guide.
# #
INST "*trimac_block*gmii_interface*delay_gmii_rx_dv" IDELAY_VALUE = 15; INST "*trimac_block*gmii_interface*delay_gmii_rx_dv" IDELAY_VALUE = 25;
INST "*trimac_block*gmii_interface*delay_gmii_rx_er" IDELAY_VALUE = 15; INST "*trimac_block*gmii_interface*delay_gmii_rx_er" IDELAY_VALUE = 25;
INST "*trimac_block*gmii_interface*delay_gmii_rxd" IDELAY_VALUE = 15; INST "*trimac_block*gmii_interface*delay_gmii_rxd" IDELAY_VALUE = 25;
INST *trimac_block*gmii_interface*bufio_gmii_rx_clk LOC = BUFIO2_X3Y13; INST *trimac_block*gmii_interface*bufio_gmii_rx_clk LOC = BUFIO2_X3Y12;
#INST *trimac_block*gmii_interface*bufg_gmii_rx_clk LOC = BUFGMUX_X3Y5; #INST *trimac_block*gmii_interface*bufg_gmii_rx_clk LOC = BUFGMUX_X3Y5;
############################################################ ############################################################
......
firmware/IPBus/firmware/ethernet/coregen/tri_mode_eth_mac_v5_4/implement/implement.bat
View file @ 2f031cf3
...@@ -3,8 +3,8 @@ rem Clean up the results directory ...@@ -3,8 +3,8 @@ rem Clean up the results directory
rmdir /S /Q results rmdir /S /Q results
mkdir results mkdir results
rem Synthesize the VHDL Wrapper Files rem Synthesize the Verilog Wrapper Files
echo 'Synthesizing VHDL example design with XST'; echo 'Synthesizing verilog example design with XST';
xst -ifn xst.scr xst -ifn xst.scr
copy tri_mode_eth_mac_v5_4_example_design.ngc .\results\ copy tri_mode_eth_mac_v5_4_example_design.ngc .\results\
...@@ -32,5 +32,5 @@ trce -u -e 10 routed -o routed mapped.pcf ...@@ -32,5 +32,5 @@ trce -u -e 10 routed -o routed mapped.pcf
echo 'Running design through bitgen' echo 'Running design through bitgen'
bitgen -w routed routed mapped.pcf bitgen -w routed routed mapped.pcf
echo 'Running netgen to create gate level VHDL model' echo 'Running netgen to create gate level Verilog model'
netgen -ofmt vhdl -pcf mapped.pcf -sim -dir . -tm tri_mode_eth_mac_v5_4_example_design -w routed.ncd routed.vhd netgen -ofmt verilog -pcf mapped.pcf -sim -dir . -tm tri_mode_eth_mac_v5_4_example_design -w -sdf_anno false routed.ncd routed.v
firmware/IPBus/firmware/ethernet/coregen/tri_mode_eth_mac_v5_4/implement/implement.sh
View file @ 2f031cf3
...@@ -4,8 +4,8 @@ ...@@ -4,8 +4,8 @@
rm -rf results rm -rf results
mkdir results mkdir results
#Synthesize the VHDL Wrapper Files #Synthesize the Verilog Wrapper Files
echo 'Synthesizing VHDL example design with XST'; echo 'Synthesizing verilog example design with XST';
xst -ifn xst.scr xst -ifn xst.scr
cp tri_mode_eth_mac_v5_4_example_design.ngc ./results/ cp tri_mode_eth_mac_v5_4_example_design.ngc ./results/
...@@ -34,5 +34,5 @@ trce -u -e 10 routed -o routed mapped.pcf ...@@ -34,5 +34,5 @@ trce -u -e 10 routed -o routed mapped.pcf
echo 'Running design through bitgen' echo 'Running design through bitgen'
bitgen -w routed routed mapped.pcf bitgen -w routed routed mapped.pcf
echo 'Running netgen to create gate level VHDL model' echo 'Running netgen to create gate level Verilog model'
netgen -ofmt vhdl -pcf mapped.pcf -sim -dir . -tm tri_mode_eth_mac_v5_4_example_design -w routed.ncd routed.vhd netgen -ofmt verilog -pcf mapped.pcf -sim -dir . -tm tri_mode_eth_mac_v5_4_example_design -w -sdf_anno false routed.ncd routed.v
firmware/IPBus/firmware/ethernet/coregen/tri_mode_eth_mac_v5_4/implement/xst.prj
View file @ 2f031cf3
vhdl work ..\example_design\fifo\tri_mode_eth_mac_v5_4_tx_client_fifo.vhd verilog work ../example_design/tri_mode_eth_mac_v5_4_mod.v
vhdl work ..\example_design\fifo\tri_mode_eth_mac_v5_4_rx_client_fifo.vhd verilog work ../example_design/fifo/tri_mode_eth_mac_v5_4_tx_client_fifo.v
vhdl work ..\example_design\fifo\tri_mode_eth_mac_v5_4_ten_100_1g_eth_fifo.vhd verilog work ../example_design/fifo/tri_mode_eth_mac_v5_4_rx_client_fifo.v
vhdl work ..\example_design\common\tri_mode_eth_mac_v5_4_reset_sync.vhd verilog work ../example_design/fifo/tri_mode_eth_mac_v5_4_ten_100_1g_eth_fifo.v
vhdl work ..\example_design\common\tri_mode_eth_mac_v5_4_sync_block.vhd verilog work ../example_design/common/tri_mode_eth_mac_v5_4_reset_sync.v
vhdl work ..\example_design\pat_gen\tri_mode_eth_mac_v5_4_address_swap.vhd verilog work ../example_design/common/tri_mode_eth_mac_v5_4_sync_block.v
vhdl work ..\example_design\pat_gen\tri_mode_eth_mac_v5_4_axi_mux.vhd verilog work ../example_design/pat_gen/tri_mode_eth_mac_v5_4_address_swap.v
vhdl work ..\example_design\pat_gen\tri_mode_eth_mac_v5_4_axi_pat_gen.vhd verilog work ../example_design/pat_gen/tri_mode_eth_mac_v5_4_axi_mux.v
vhdl work ..\example_design\pat_gen\tri_mode_eth_mac_v5_4_axi_pat_check.vhd verilog work ../example_design/pat_gen/tri_mode_eth_mac_v5_4_axi_pat_gen.v
vhdl work ..\example_design\pat_gen\tri_mode_eth_mac_v5_4_axi_pipe.vhd verilog work ../example_design/pat_gen/tri_mode_eth_mac_v5_4_axi_pat_check.v
vhdl work ..\example_design\pat_gen\tri_mode_eth_mac_v5_4_basic_pat_gen.vhd verilog work ../example_design/pat_gen/tri_mode_eth_mac_v5_4_axi_pipe.v
vhdl work ..\example_design\physical\tri_mode_eth_mac_v5_4_gmii_if.vhd verilog work ../example_design/pat_gen/tri_mode_eth_mac_v5_4_basic_pat_gen.v
vhdl work ..\example_design\control\tri_mode_eth_mac_v5_4_config_vector_sm.vhd verilog work ../example_design/physical/tri_mode_eth_mac_v5_4_gmii_if.v
verilog work ../example_design/control/tri_mode_eth_mac_v5_4_config_vector_sm.v
vhdl work ..\example_design\tri_mode_eth_mac_v5_4_clk_wiz.vhd verilog work ../example_design/tri_mode_eth_mac_v5_4_clk_wiz.v
vhdl work ..\example_design\tri_mode_eth_mac_v5_4_block.vhd verilog work ../example_design/tri_mode_eth_mac_v5_4_block.v
vhdl work ..\example_design\tri_mode_eth_mac_v5_4_fifo_block.vhd verilog work ../example_design/tri_mode_eth_mac_v5_4_fifo_block.v
vhdl work ..\example_design\tri_mode_eth_mac_v5_4_example_design.vhd verilog work ../example_design/tri_mode_eth_mac_v5_4_example_design.v
firmware/IPBus/firmware/ethernet/coregen/tri_mode_eth_mac_v5_4/simulation/functional/simulate_mti.do
View file @ 2f031cf3
...@@ -2,32 +2,33 @@ vlib work ...@@ -2,32 +2,33 @@ vlib work
vmap work work vmap work work
echo "Compiling Core Simulation Model" echo "Compiling Core Simulation Model"
vcom -work work ../../../tri_mode_eth_mac_v5_4.vhd vlog -work work ../../../tri_mode_eth_mac_v5_4.v
echo "Compiling Example Design" echo "Compiling Example Design"
vcom -work work \ vlog -work work \
../../example_design/fifo/tri_mode_eth_mac_v5_4_tx_client_fifo.vhd \ ../../example_design/fifo/tri_mode_eth_mac_v5_4_tx_client_fifo.v \
../../example_design/fifo/tri_mode_eth_mac_v5_4_rx_client_fifo.vhd \ ../../example_design/fifo/tri_mode_eth_mac_v5_4_rx_client_fifo.v \
../../example_design/fifo/tri_mode_eth_mac_v5_4_ten_100_1g_eth_fifo.vhd \ ../../example_design/fifo/tri_mode_eth_mac_v5_4_ten_100_1g_eth_fifo.v \
../../example_design/common/tri_mode_eth_mac_v5_4_reset_sync.vhd \ ../../example_design/common/tri_mode_eth_mac_v5_4_reset_sync.v \
../../example_design/common/tri_mode_eth_mac_v5_4_sync_block.vhd \ ../../example_design/common/tri_mode_eth_mac_v5_4_sync_block.v \
../../example_design/pat_gen/tri_mode_eth_mac_v5_4_address_swap.vhd \ ../../example_design/pat_gen/tri_mode_eth_mac_v5_4_address_swap.v \
../../example_design/pat_gen/tri_mode_eth_mac_v5_4_axi_mux.vhd \ ../../example_design/pat_gen/tri_mode_eth_mac_v5_4_axi_mux.v \
../../example_design/pat_gen/tri_mode_eth_mac_v5_4_axi_pat_gen.vhd \ ../../example_design/pat_gen/tri_mode_eth_mac_v5_4_axi_pat_gen.v \
../../example_design/pat_gen/tri_mode_eth_mac_v5_4_axi_pat_check.vhd \ ../../example_design/pat_gen/tri_mode_eth_mac_v5_4_axi_pat_check.v \
../../example_design/pat_gen/tri_mode_eth_mac_v5_4_axi_pipe.vhd \ ../../example_design/pat_gen/tri_mode_eth_mac_v5_4_axi_pipe.v \
../../example_design/pat_gen/tri_mode_eth_mac_v5_4_basic_pat_gen.vhd \ ../../example_design/pat_gen/tri_mode_eth_mac_v5_4_basic_pat_gen.v \
../../example_design/physical/tri_mode_eth_mac_v5_4_gmii_if.vhd \ ../../example_design/physical/tri_mode_eth_mac_v5_4_gmii_if.v \
../../example_design/control/tri_mode_eth_mac_v5_4_config_vector_sm.vhd \ ../../example_design/control/tri_mode_eth_mac_v5_4_config_vector_sm.v \
../../example_design/tri_mode_eth_mac_v5_4_clk_wiz.vhd \ ../../example_design/tri_mode_eth_mac_v5_4_clk_wiz.v \
../../example_design/tri_mode_eth_mac_v5_4_block.vhd \ ../../example_design/tri_mode_eth_mac_v5_4_block.v \
../../example_design/tri_mode_eth_mac_v5_4_fifo_block.vhd \ ../../example_design/tri_mode_eth_mac_v5_4_fifo_block.v \
../../example_design/tri_mode_eth_mac_v5_4_example_design.vhd ../../example_design/tri_mode_eth_mac_v5_4_example_design.v
echo "Compiling Test Bench" echo "Compiling Test Bench"
vcom -work work ../demo_tb.vhd vlog -work work ../tri_mode_eth_mac_v5_4_frame_typ.v
vlog -work work ../demo_tb.v
echo "Starting simulation" echo "Starting simulation"
vsim -t ps work.demo_tb -voptargs="+acc+demo_tb+/demo_tb/dut+/demo_tb/dut/trimac_fifo_block" vsim -L unisims_ver -L unimacro_ver -t ps work.demo_tb work.glbl -voptargs="+acc+demo_tb+/demo_tb/dut+/demo_tb/dut/trimac_fifo_block"
do wave_mti.do do wave_mti.do
run -all run -all
firmware/IPBus/firmware/ethernet/coregen/tri_mode_eth_mac_v5_4/simulation/functional/simulate_ncsim.sh
View file @ 2f031cf3
...@@ -2,34 +2,34 @@ ...@@ -2,34 +2,34 @@
mkdir work mkdir work
echo "Compiling Tri-Mode Ethernet MAC Core Simulation Models" echo "Compiling Tri-Mode Ethernet MAC Core Simulation Models"
ncvhdl -v93 -work work ../../../tri_mode_eth_mac_v5_4.vhd ncvlog -work work ../../../tri_mode_eth_mac_v5_4.v
echo "Compiling Example Design" echo "Compiling Example Design"
ncvhdl -v93 -work work \ ncvlog -work work \
../../example_design/fifo/tri_mode_eth_mac_v5_4_tx_client_fifo.vhd \ ../../example_design/fifo/tri_mode_eth_mac_v5_4_tx_client_fifo.v \
../../example_design/fifo/tri_mode_eth_mac_v5_4_rx_client_fifo.vhd \ ../../example_design/fifo/tri_mode_eth_mac_v5_4_rx_client_fifo.v \
../../example_design/fifo/tri_mode_eth_mac_v5_4_ten_100_1g_eth_fifo.vhd \ ../../example_design/fifo/tri_mode_eth_mac_v5_4_ten_100_1g_eth_fifo.v \
../../example_design/common/tri_mode_eth_mac_v5_4_reset_sync.vhd \ ../../example_design/common/tri_mode_eth_mac_v5_4_reset_sync.v \
../../example_design/common/tri_mode_eth_mac_v5_4_sync_block.vhd \ ../../example_design/common/tri_mode_eth_mac_v5_4_sync_block.v \
../../example_design/pat_gen/tri_mode_eth_mac_v5_4_address_swap.vhd \ ../../example_design/pat_gen/tri_mode_eth_mac_v5_4_address_swap.v \
../../example_design/pat_gen/tri_mode_eth_mac_v5_4_axi_mux.vhd \ ../../example_design/pat_gen/tri_mode_eth_mac_v5_4_axi_mux.v \
../../example_design/pat_gen/tri_mode_eth_mac_v5_4_axi_pat_gen.vhd \ ../../example_design/pat_gen/tri_mode_eth_mac_v5_4_axi_pat_gen.v \
../../example_design/pat_gen/tri_mode_eth_mac_v5_4_axi_pat_check.vhd \ ../../example_design/pat_gen/tri_mode_eth_mac_v5_4_axi_pat_check.v \
../../example_design/pat_gen/tri_mode_eth_mac_v5_4_axi_pipe.vhd \ ../../example_design/pat_gen/tri_mode_eth_mac_v5_4_axi_pipe.v \
../../example_design/pat_gen/tri_mode_eth_mac_v5_4_basic_pat_gen.vhd \ ../../example_design/pat_gen/tri_mode_eth_mac_v5_4_basic_pat_gen.v \
../../example_design/physical/tri_mode_eth_mac_v5_4_gmii_if.vhd \ ../../example_design/physical/tri_mode_eth_mac_v5_4_gmii_if.v \
../../example_design/control/tri_mode_eth_mac_v5_4_config_vector_sm.vhd \ ../../example_design/control/tri_mode_eth_mac_v5_4_config_vector_sm.v \
../../example_design/tri_mode_eth_mac_v5_4_clk_wiz.vhd \ ../../example_design/tri_mode_eth_mac_v5_4_clk_wiz.v \
../../example_design/tri_mode_eth_mac_v5_4_block.vhd \ ../../example_design/tri_mode_eth_mac_v5_4_block.v \
../../example_design/tri_mode_eth_mac_v5_4_fifo_block.vhd \ ../../example_design/tri_mode_eth_mac_v5_4_fifo_block.v \
../../example_design/tri_mode_eth_mac_v5_4_example_design.vhd ../../example_design/tri_mode_eth_mac_v5_4_example_design.v
echo "Compiling Test Bench" echo "Compiling Test Bench"
ncvhdl -v93 -work work ../demo_tb.vhd ncvlog -work work ../tri_mode_eth_mac_v5_4_frame_typ.v
ncvlog -work work ../demo_tb.v
echo "Elaborating design" echo "Elaborating design"
ncelab -access +r work.demo_tb:behav ncelab -access +rw work.demo_tb glbl
echo "Starting simulation" echo "Starting simulation"
ncsim -gui work.demo_tb:behav -input @"simvision -input wave_ncsim.sv" ncsim -gui -input @"simvision -input wave_ncsim.sv" work.demo_tb
firmware/IPBus/firmware/ethernet/coregen/tri_mode_eth_mac_v5_4/simulation/functional/wave_ncsim.sv
View file @ 2f031cf3
...@@ -11,8 +11,8 @@ if {[catch {group new -name {System Signals} -overlay 0}] != ""} { ...@@ -11,8 +11,8 @@ if {[catch {group new -name {System Signals} -overlay 0}] != ""} {
group clear 0 end group clear 0 end
} }
group insert \ group insert \
:reset \ :demo_tb.reset \
:gtx_clk :demo_tb.gtx_clk
if {[catch {group new -name {TX MAC Interface} -overlay 0}] != ""} { if {[catch {group new -name {TX MAC Interface} -overlay 0}] != ""} {
group using {TX MAC Interface} group using {TX MAC Interface}
...@@ -21,13 +21,13 @@ if {[catch {group new -name {TX MAC Interface} -overlay 0}] != ""} { ...@@ -21,13 +21,13 @@ if {[catch {group new -name {TX MAC Interface} -overlay 0}] != ""} {
group clear 0 end group clear 0 end
} }
group insert \ group insert \
:dut.trimac_fifo_block.tx_mac_resetn \ :demo_tb.dut.trimac_fifo_block.tx_mac_resetn \
:dut.trimac_fifo_block.tx_axis_mac_tvalid \ :demo_tb.dut.trimac_fifo_block.tx_axis_mac_tvalid \
:dut.trimac_fifo_block.tx_axis_mac_tdata \ :demo_tb.dut.trimac_fifo_block.tx_axis_mac_tdata \
:dut.trimac_fifo_block.tx_axis_mac_tready \ :demo_tb.dut.trimac_fifo_block.tx_axis_mac_tready \
:dut.trimac_fifo_block.tx_axis_mac_tlast \ :demo_tb.dut.trimac_fifo_block.tx_axis_mac_tlast \
:dut.trimac_fifo_block.tx_axis_mac_tuser :demo_tb.dut.trimac_fifo_block.tx_axis_mac_tuser
if {[catch {group new -name {TX Statistics Vector} -overlay 0}] != ""} { if {[catch {group new -name {TX Statistics Vector} -overlay 0}] != ""} {
group using {TX Statistics Vector} group using {TX Statistics Vector}
...@@ -36,8 +36,8 @@ if {[catch {group new -name {TX Statistics Vector} -overlay 0}] != ""} { ...@@ -36,8 +36,8 @@ if {[catch {group new -name {TX Statistics Vector} -overlay 0}] != ""} {
group clear 0 end group clear 0 end
} }
group insert \ group insert \
:dut.tx_statistics_vector \ :demo_tb.dut.tx_statistics_vector \
:dut.tx_statistics_valid :demo_tb.dut.tx_statistics_valid
if {[catch {group new -name {RX MAC Interface} -overlay 0}] != ""} { if {[catch {group new -name {RX MAC Interface} -overlay 0}] != ""} {
group using {RX MAC Interface} group using {RX MAC Interface}
...@@ -46,12 +46,12 @@ if {[catch {group new -name {RX MAC Interface} -overlay 0}] != ""} { ...@@ -46,12 +46,12 @@ if {[catch {group new -name {RX MAC Interface} -overlay 0}] != ""} {
group clear 0 end group clear 0 end
} }
group insert \ group insert \
:dut.trimac_fifo_block.rx_mac_aclk \ :demo_tb.dut.trimac_fifo_block.rx_mac_aclk \
:dut.trimac_fifo_block.rx_mac_resetn \ :demo_tb.dut.trimac_fifo_block.rx_mac_resetn \
:dut.trimac_fifo_block.rx_axis_mac_tvalid \ :demo_tb.dut.trimac_fifo_block.rx_axis_mac_tvalid \
:dut.trimac_fifo_block.rx_axis_mac_tdata \ :demo_tb.dut.trimac_fifo_block.rx_axis_mac_tdata \
:dut.trimac_fifo_block.rx_axis_mac_tlast \ :demo_tb.dut.trimac_fifo_block.rx_axis_mac_tlast \
:dut.trimac_fifo_block.rx_axis_mac_tuser :demo_tb.dut.trimac_fifo_block.rx_axis_mac_tuser
if {[catch {group new -name {RX Statistics Vector} -overlay 0}] != ""} { if {[catch {group new -name {RX Statistics Vector} -overlay 0}] != ""} {
...@@ -61,8 +61,8 @@ if {[catch {group new -name {RX Statistics Vector} -overlay 0}] != ""} { ...@@ -61,8 +61,8 @@ if {[catch {group new -name {RX Statistics Vector} -overlay 0}] != ""} {
group clear 0 end group clear 0 end
} }
group insert \ group insert \
:dut.rx_statistics_vector \ :demo_tb.dut.rx_statistics_vector \
:dut.rx_statistics_valid :demo_tb.dut.rx_statistics_valid
if {[catch {group new -name {Flow Control} -overlay 0}] != ""} { if {[catch {group new -name {Flow Control} -overlay 0}] != ""} {
...@@ -72,8 +72,8 @@ if {[catch {group new -name {Flow Control} -overlay 0}] != ""} { ...@@ -72,8 +72,8 @@ if {[catch {group new -name {Flow Control} -overlay 0}] != ""} {
group clear 0 end group clear 0 end
} }
group insert \ group insert \
:dut.pause_val \ :demo_tb.dut.pause_val \
:dut.pause_req :demo_tb.dut.pause_req
if {[catch {group new -name {Rx FIFO Interface} -overlay 0}] != ""} { if {[catch {group new -name {Rx FIFO Interface} -overlay 0}] != ""} {
group using {Rx FIFO Interface} group using {Rx FIFO Interface}
...@@ -83,12 +83,12 @@ if {[catch {group new -name {Rx FIFO Interface} -overlay 0}] != ""} { ...@@ -83,12 +83,12 @@ if {[catch {group new -name {Rx FIFO Interface} -overlay 0}] != ""} {
group clear 0 end group clear 0 end
} }
group insert \ group insert \
:dut.trimac_fifo_block.rx_fifo_clock \ :demo_tb.dut.trimac_fifo_block.rx_fifo_clock \
:dut.trimac_fifo_block.rx_fifo_resetn \ :demo_tb.dut.trimac_fifo_block.rx_fifo_resetn \
:dut.trimac_fifo_block.rx_axis_fifo_tdata \ :demo_tb.dut.trimac_fifo_block.rx_axis_fifo_tdata \
:dut.trimac_fifo_block.rx_axis_fifo_tlast \ :demo_tb.dut.trimac_fifo_block.rx_axis_fifo_tlast \
:dut.trimac_fifo_block.rx_axis_fifo_tready \ :demo_tb.dut.trimac_fifo_block.rx_axis_fifo_tready \
:dut.trimac_fifo_block.rx_axis_fifo_tvalid :demo_tb.dut.trimac_fifo_block.rx_axis_fifo_tvalid
if {[catch {group new -name {Tx FIFO Interface} -overlay 0}] != ""} { if {[catch {group new -name {Tx FIFO Interface} -overlay 0}] != ""} {
group using {Tx FIFO Interface} group using {Tx FIFO Interface}
...@@ -97,12 +97,12 @@ if {[catch {group new -name {Tx FIFO Interface} -overlay 0}] != ""} { ...@@ -97,12 +97,12 @@ if {[catch {group new -name {Tx FIFO Interface} -overlay 0}] != ""} {
group clear 0 end group clear 0 end
} }
group insert \ group insert \
:dut.trimac_fifo_block.tx_fifo_clock \ :demo_tb.dut.trimac_fifo_block.tx_fifo_clock \
:dut.trimac_fifo_block.tx_fifo_resetn \ :demo_tb.dut.trimac_fifo_block.tx_fifo_resetn \
:dut.trimac_fifo_block.tx_axis_fifo_tdata \ :demo_tb.dut.trimac_fifo_block.tx_axis_fifo_tdata \
:dut.trimac_fifo_block.tx_axis_fifo_tlast \ :demo_tb.dut.trimac_fifo_block.tx_axis_fifo_tlast \
:dut.trimac_fifo_block.tx_axis_fifo_tready \ :demo_tb.dut.trimac_fifo_block.tx_axis_fifo_tready \
:dut.trimac_fifo_block.tx_axis_fifo_tvalid :demo_tb.dut.trimac_fifo_block.tx_axis_fifo_tvalid
if {[catch {group new -name {TX GMII/MII Interface} -overlay 0}] != ""} { if {[catch {group new -name {TX GMII/MII Interface} -overlay 0}] != ""} {
group using {TX GMII/MII Interface} group using {TX GMII/MII Interface}
...@@ -111,10 +111,10 @@ if {[catch {group new -name {TX GMII/MII Interface} -overlay 0}] != ""} { ...@@ -111,10 +111,10 @@ if {[catch {group new -name {TX GMII/MII Interface} -overlay 0}] != ""} {
group clear 0 end group clear 0 end
} }
group insert \ group insert \
:gmii_tx_clk \ :demo_tb.gmii_tx_clk \
:gmii_tx_en \ :demo_tb.gmii_tx_en \
:gmii_tx_er \ :demo_tb.gmii_tx_er \
:gmii_txd :demo_tb.gmii_txd
if {[catch {group new -name {RX GMII/MII Interface} -overlay 0}] != ""} { if {[catch {group new -name {RX GMII/MII Interface} -overlay 0}] != ""} {
group using {RX GMII/MII Interface} group using {RX GMII/MII Interface}
...@@ -123,10 +123,10 @@ if {[catch {group new -name {RX GMII/MII Interface} -overlay 0}] != ""} { ...@@ -123,10 +123,10 @@ if {[catch {group new -name {RX GMII/MII Interface} -overlay 0}] != ""} {
group clear 0 end group clear 0 end
} }
group insert \ group insert \
:gmii_rx_clk \ :demo_tb.gmii_rx_clk \
:gmii_rx_dv \ :demo_tb.gmii_rx_dv \
:gmii_rx_er \ :demo_tb.gmii_rx_er \
:gmii_rxd :demo_tb.gmii_rxd
...@@ -138,8 +138,8 @@ if {[catch {group new -name {Configuration Interface} -overlay 0}] != ""} { ...@@ -138,8 +138,8 @@ if {[catch {group new -name {Configuration Interface} -overlay 0}] != ""} {
group clear 0 end group clear 0 end
} }
group insert \ group insert \
:dut.rx_configuration_vector \ :demo_tb.dut.rx_configuration_vector \
:dut.tx_configuration_vector :demo_tb.dut.tx_configuration_vector
# #
......
firmware/IPBus/firmware/ethernet/coregen/tri_mode_eth_mac_v5_4_flist.txt
View file @ 2f031cf3
# Output products list for <tri_mode_eth_mac_v5_4> # Output products list for <tri_mode_eth_mac_v5_4>
_xmsgs/pn_parser.xmsgs
tri_mode_eth_mac_v5_4/doc/pg051-tri-mode-eth-mac.pdf tri_mode_eth_mac_v5_4/doc/pg051-tri-mode-eth-mac.pdf
tri_mode_eth_mac_v5_4/doc/tri_mode_eth_mac_v5_4_vinfo.html tri_mode_eth_mac_v5_4/doc/tri_mode_eth_mac_v5_4_vinfo.html
tri_mode_eth_mac_v5_4/example_design/axi_ipif/tri_mode_eth_mac_v5_4_address_decoder.vhd tri_mode_eth_mac_v5_4/example_design/axi_ipif/tri_mode_eth_mac_v5_4_address_decoder.v
tri_mode_eth_mac_v5_4/example_design/axi_ipif/tri_mode_eth_mac_v5_4_axi4_lite_ipif_wrapper.vhd tri_mode_eth_mac_v5_4/example_design/axi_ipif/tri_mode_eth_mac_v5_4_axi4_lite_ipif_wrapper.v
tri_mode_eth_mac_v5_4/example_design/axi_ipif/tri_mode_eth_mac_v5_4_axi_lite_ipif.vhd tri_mode_eth_mac_v5_4/example_design/axi_ipif/tri_mode_eth_mac_v5_4_axi_lite_ipif.v
tri_mode_eth_mac_v5_4/example_design/axi_ipif/tri_mode_eth_mac_v5_4_counter_f.vhd tri_mode_eth_mac_v5_4/example_design/axi_ipif/tri_mode_eth_mac_v5_4_counter_f.v
tri_mode_eth_mac_v5_4/example_design/axi_ipif/tri_mode_eth_mac_v5_4_ipif_pkg.vhd tri_mode_eth_mac_v5_4/example_design/axi_ipif/tri_mode_eth_mac_v5_4_pselect_f.v
tri_mode_eth_mac_v5_4/example_design/axi_ipif/tri_mode_eth_mac_v5_4_pselect_f.vhd tri_mode_eth_mac_v5_4/example_design/axi_ipif/tri_mode_eth_mac_v5_4_slave_attachment.v
tri_mode_eth_mac_v5_4/example_design/axi_ipif/tri_mode_eth_mac_v5_4_slave_attachment.vhd tri_mode_eth_mac_v5_4/example_design/common/tri_mode_eth_mac_v5_4_reset_sync.v
tri_mode_eth_mac_v5_4/example_design/common/tri_mode_eth_mac_v5_4_reset_sync.vhd tri_mode_eth_mac_v5_4/example_design/common/tri_mode_eth_mac_v5_4_sync_block.v
tri_mode_eth_mac_v5_4/example_design/common/tri_mode_eth_mac_v5_4_sync_block.vhd tri_mode_eth_mac_v5_4/example_design/control/tri_mode_eth_mac_v5_4_config_vector_sm.v
tri_mode_eth_mac_v5_4/example_design/control/tri_mode_eth_mac_v5_4_config_vector_sm.vhd tri_mode_eth_mac_v5_4/example_design/fifo/tri_mode_eth_mac_v5_4_rx_client_fifo.v
tri_mode_eth_mac_v5_4/example_design/fifo/tri_mode_eth_mac_v5_4_rx_client_fifo.vhd tri_mode_eth_mac_v5_4/example_design/fifo/tri_mode_eth_mac_v5_4_ten_100_1g_eth_fifo.v
tri_mode_eth_mac_v5_4/example_design/fifo/tri_mode_eth_mac_v5_4_ten_100_1g_eth_fifo.vhd tri_mode_eth_mac_v5_4/example_design/fifo/tri_mode_eth_mac_v5_4_tx_client_fifo.v
tri_mode_eth_mac_v5_4/example_design/fifo/tri_mode_eth_mac_v5_4_tx_client_fifo.vhd tri_mode_eth_mac_v5_4/example_design/pat_gen/tri_mode_eth_mac_v5_4_address_swap.v
tri_mode_eth_mac_v5_4/example_design/pat_gen/tri_mode_eth_mac_v5_4_address_swap.vhd tri_mode_eth_mac_v5_4/example_design/pat_gen/tri_mode_eth_mac_v5_4_axi_mux.v
tri_mode_eth_mac_v5_4/example_design/pat_gen/tri_mode_eth_mac_v5_4_axi_mux.vhd tri_mode_eth_mac_v5_4/example_design/pat_gen/tri_mode_eth_mac_v5_4_axi_pat_check.v
tri_mode_eth_mac_v5_4/example_design/pat_gen/tri_mode_eth_mac_v5_4_axi_pat_check.vhd tri_mode_eth_mac_v5_4/example_design/pat_gen/tri_mode_eth_mac_v5_4_axi_pat_gen.v
tri_mode_eth_mac_v5_4/example_design/pat_gen/tri_mode_eth_mac_v5_4_axi_pat_gen.vhd tri_mode_eth_mac_v5_4/example_design/pat_gen/tri_mode_eth_mac_v5_4_axi_pipe.v
tri_mode_eth_mac_v5_4/example_design/pat_gen/tri_mode_eth_mac_v5_4_axi_pipe.vhd tri_mode_eth_mac_v5_4/example_design/pat_gen/tri_mode_eth_mac_v5_4_basic_pat_gen.v
tri_mode_eth_mac_v5_4/example_design/pat_gen/tri_mode_eth_mac_v5_4_basic_pat_gen.vhd tri_mode_eth_mac_v5_4/example_design/physical/tri_mode_eth_mac_v5_4_gmii_if.v
tri_mode_eth_mac_v5_4/example_design/physical/tri_mode_eth_mac_v5_4_gmii_if.vhd tri_mode_eth_mac_v5_4/example_design/tri_mode_eth_mac_v5_4_block.v
tri_mode_eth_mac_v5_4/example_design/tri_mode_eth_mac_v5_4_block.vhd tri_mode_eth_mac_v5_4/example_design/tri_mode_eth_mac_v5_4_clk_wiz.v
tri_mode_eth_mac_v5_4/example_design/tri_mode_eth_mac_v5_4_clk_wiz.vhd
tri_mode_eth_mac_v5_4/example_design/tri_mode_eth_mac_v5_4_example_design.ucf tri_mode_eth_mac_v5_4/example_design/tri_mode_eth_mac_v5_4_example_design.ucf
tri_mode_eth_mac_v5_4/example_design/tri_mode_eth_mac_v5_4_example_design.vhd tri_mode_eth_mac_v5_4/example_design/tri_mode_eth_mac_v5_4_example_design.v
tri_mode_eth_mac_v5_4/example_design/tri_mode_eth_mac_v5_4_fifo_block.vhd tri_mode_eth_mac_v5_4/example_design/tri_mode_eth_mac_v5_4_fifo_block.v
tri_mode_eth_mac_v5_4/example_design/tri_mode_eth_mac_v5_4_mod.v
tri_mode_eth_mac_v5_4/implement/implement.bat tri_mode_eth_mac_v5_4/implement/implement.bat
tri_mode_eth_mac_v5_4/implement/implement.sh tri_mode_eth_mac_v5_4/implement/implement.sh
tri_mode_eth_mac_v5_4/implement/xst.prj tri_mode_eth_mac_v5_4/implement/xst.prj
tri_mode_eth_mac_v5_4/implement/xst.scr tri_mode_eth_mac_v5_4/implement/xst.scr
tri_mode_eth_mac_v5_4/simulation/demo_tb.vhd tri_mode_eth_mac_v5_4/simulation/demo_tb.v
tri_mode_eth_mac_v5_4/simulation/functional/simulate_mti.do tri_mode_eth_mac_v5_4/simulation/functional/simulate_mti.do
tri_mode_eth_mac_v5_4/simulation/functional/simulate_ncsim.sh tri_mode_eth_mac_v5_4/simulation/functional/simulate_ncsim.sh
tri_mode_eth_mac_v5_4/simulation/functional/simulate_vcs.sh
tri_mode_eth_mac_v5_4/simulation/functional/ucli_commands.key
tri_mode_eth_mac_v5_4/simulation/functional/vcs_session.tcl
tri_mode_eth_mac_v5_4/simulation/functional/wave_mti.do tri_mode_eth_mac_v5_4/simulation/functional/wave_mti.do
tri_mode_eth_mac_v5_4/simulation/functional/wave_ncsim.sv tri_mode_eth_mac_v5_4/simulation/functional/wave_ncsim.sv
tri_mode_eth_mac_v5_4/simulation/tri_mode_eth_mac_v5_4_frame_typ.v
tri_mode_eth_mac_v5_4/tri_mode_eth_mac_readme.txt tri_mode_eth_mac_v5_4/tri_mode_eth_mac_readme.txt
tri_mode_eth_mac_v5_4.asy tri_mode_eth_mac_v5_4.asy
tri_mode_eth_mac_v5_4.gise tri_mode_eth_mac_v5_4.gise
tri_mode_eth_mac_v5_4.ngc tri_mode_eth_mac_v5_4.ngc
tri_mode_eth_mac_v5_4.sym tri_mode_eth_mac_v5_4.sym
tri_mode_eth_mac_v5_4.vhd tri_mode_eth_mac_v5_4.v
tri_mode_eth_mac_v5_4.vho tri_mode_eth_mac_v5_4.veo
tri_mode_eth_mac_v5_4.xco tri_mode_eth_mac_v5_4.xco
tri_mode_eth_mac_v5_4.xise tri_mode_eth_mac_v5_4.xise
tri_mode_eth_mac_v5_4_flist.txt tri_mode_eth_mac_v5_4_flist.txt
......
firmware/Manifest.py
View file @ 2f031cf3
...@@ -2,8 +2,8 @@ ...@@ -2,8 +2,8 @@
fetchto = "ip_cores" fetchto = "ip_cores"
modules = {"local" : modules = {"local" :
[ "whiteRabbit/wr-cores", [ "IPBus/firmware",
"IPBus/firmware",
"hdl" "hdl"
] ],
"git" : "git://ohwr.org/hdl-core-lib/wr-cores.git"
} }
firmware/README
View file @ 2f031cf3
...@@ -8,11 +8,15 @@ hdlmake-v1.0 --make-ise --ise-proj ...@@ -8,11 +8,15 @@ hdlmake-v1.0 --make-ise --ise-proj
make make
----------------------
..... for newer versions.... *NB* Tested with ISE version 14.7 . Other versions may not work.
python /projects/HEP_Instrumentation/cad/designs/hdl-make/git-2.1/hdl-make/hdlmake ise-project Hacked version of hdlmake that can (just about) work with ISE Coregen *.xco
files copied into firmware directory.
......... For HDLMake 2.x cd maroc_csa/firmware/syn/pc049a/demo
python ../../../hdl-make/hdlmake ise-project
firmware/hdl/IPBusInterfaceGTP_rtl.vhd
View file @ 2f031cf3
...@@ -71,7 +71,7 @@ ENTITY IPBusInterfaceGTP IS ...@@ -71,7 +71,7 @@ ENTITY IPBusInterfaceGTP IS
ipbr_i : IN ipb_rbus_array (NUM_EXT_SLAVES-1 DOWNTO 0); -- ! IPBus read signals ipbr_i : IN ipb_rbus_array (NUM_EXT_SLAVES-1 DOWNTO 0); -- ! IPBus read signals
sysclk_i : IN std_logic; -- ! 125 MHz xtal clock sysclk_i : IN std_logic; -- ! 125 MHz xtal clock
clocks_locked_o : OUT std_logic; clocks_locked_o,pkt_rx_led_o, pkt_tx_led_o : OUT std_logic;
ipb_clk_o : OUT std_logic; -- ! IPBus clock to slaves ipb_clk_o : OUT std_logic; -- ! IPBus clock to slaves
ipb_rst_o : OUT std_logic; -- ! IPBus reset to slaves ipb_rst_o : OUT std_logic; -- ! IPBus reset to slaves
ipbw_o : OUT ipb_wbus_array (NUM_EXT_SLAVES-1 DOWNTO 0); -- ! IBus write signals ipbw_o : OUT ipb_wbus_array (NUM_EXT_SLAVES-1 DOWNTO 0); -- ! IBus write signals
...@@ -105,7 +105,7 @@ ARCHITECTURE rtl OF IPBusInterfaceGTP IS ...@@ -105,7 +105,7 @@ ARCHITECTURE rtl OF IPBusInterfaceGTP IS
signal s_ipbw_internal: ipb_wbus_array (NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-1 DOWNTO 0); signal s_ipbw_internal: ipb_wbus_array (NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-1 DOWNTO 0);
signal s_ipbr_internal: ipb_rbus_array (NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-1 DOWNTO 0); signal s_ipbr_internal: ipb_rbus_array (NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-1 DOWNTO 0);
signal s_sysclk : std_logic; signal s_sysclk : std_logic;
signal pkt_rx, pkt_tx, pkt_rx_led, pkt_tx_led, sys_rst: std_logic := '0'; signal pkt_rx, pkt_tx, sys_rst: std_logic := '0';
BEGIN BEGIN
...@@ -223,8 +223,8 @@ BEGIN ...@@ -223,8 +223,8 @@ BEGIN
ip_addr => ip_addr, ip_addr => ip_addr,
pkt_rx => pkt_rx, pkt_rx => pkt_rx,
pkt_tx => pkt_tx, pkt_tx => pkt_tx,
pkt_rx_led => pkt_rx_led, pkt_rx_led => pkt_rx_led_o,
pkt_tx_led => pkt_tx_led pkt_tx_led => pkt_tx_led_o
); );
......
firmware/hdl/i2c_master_rtl.vhd
View file @ 2f031cf3
...@@ -81,12 +81,19 @@ BEGIN ...@@ -81,12 +81,19 @@ BEGIN
wb_cyc_i => '1', wb_cyc_i => '1',
wb_ack_o => ipbus_o.ipb_ack, wb_ack_o => ipbus_o.ipb_ack,
wb_inta_o => open, wb_inta_o => open,
scl_pad_i => i2c_scl_i, scl_pad_i(0) => i2c_scl_i,
scl_pad_o => open, scl_pad_o => open,
scl_padoen_o => i2c_scl_enb_o, scl_padoen_o(0) => i2c_scl_enb_o,
sda_pad_i => i2c_sda_i, sda_pad_i(0) => i2c_sda_i,
sda_pad_o => open, sda_pad_o => open,
sda_padoen_o => i2c_sda_enb_o sda_padoen_o(0) => i2c_sda_enb_o
--scl_pad_i => i2c_scl_i,
--scl_pad_o => open,
--scl_padoen_o => i2c_scl_enb_o,
--sda_pad_i => i2c_sda_i,
--sda_pad_o => open,
--sda_padoen_o => i2c_sda_enb_o
); );
......
firmware/hdl/ipbus_ver.vhd
View file @ 2f031cf3
...@@ -20,7 +20,7 @@ architecture rtl of ipbus_ver is ...@@ -20,7 +20,7 @@ architecture rtl of ipbus_ver is
begin begin
ipbus_out.ipb_rdata <= X"a627" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement). ipbus_out.ipb_rdata <= X"a62A" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement).
ipbus_out.ipb_ack <= ipbus_in.ipb_strobe; ipbus_out.ipb_ack <= ipbus_in.ipb_strobe;
ipbus_out.ipb_err <= '0'; ipbus_out.ipb_err <= '0';
......
firmware/scripts/MarocDAQ.py
View file @ 2f031cf3
...@@ -10,9 +10,10 @@ numMaroc = 1 ...@@ -10,9 +10,10 @@ numMaroc = 1
class MarocDAQ(object): class MarocDAQ(object):
def __init__(self,board,debugLevel): def __init__(self,board,debugLevel,internalTriggers=0):
"""Class to interface to MAROC-3 via IPBus""" """Class to interface to MAROC-3 via IPBus"""
self.board = board # pointer to PyChips object self.board = board # pointer to PyChips object
self.internalTriggers = internalTriggers # Set to > 0 to fire internal triggers.
self.timeStampEventSize = 12 self.timeStampEventSize = 12
self.timeStampBufferSize = 512 self.timeStampBufferSize = 512
self.adcEventSize = 26 # size of each event self.adcEventSize = 26 # size of each event
...@@ -86,8 +87,15 @@ class MarocDAQ(object): ...@@ -86,8 +87,15 @@ class MarocDAQ(object):
def readADCData(self): def readADCData(self):
"""Reads the whole ADC buffer for a MAROC, takes the portion after the read pointer and spits it into events. """Reads the whole ADC buffer for a MAROC, takes the portion after the read pointer and spits it into events.
It can cope with wrap-round of circular buffer. Returns an array of arrays of 32-bit integers""" It can cope with wrap-round of circular buffer. Returns an array of arrays of 32-bit integers. If self.internalTriggers = N ( N>0) then fires internal trigger N times"""
for internalTrigger in range(self.internalTriggers):
self.logger.info("Firing internal trigger , number %i" % internalTrigger )
self.board.write("trigManualTrigger", 1 )
# We only have one maroc per board in this type of hardware....
marocNumber = 0 marocNumber = 0
eventData = [] eventData = []
writePointerName= 'adc'+format(marocNumber,'1d')+'WritePointer' writePointerName= 'adc'+format(marocNumber,'1d')+'WritePointer'
dataName= 'adc'+format(marocNumber,'1d')+'Data' dataName= 'adc'+format(marocNumber,'1d')+'Data'
......
firmware/scripts/MarocHistogrammingThread.py
View file @ 2f031cf3
...@@ -8,6 +8,7 @@ from PyChipsUser import * ...@@ -8,6 +8,7 @@ from PyChipsUser import *
# N.B. Root Histogramming doesn't play nicely with multi-processing # N.B. Root Histogramming doesn't play nicely with multi-processing
#import threading #import threading
from threading import Thread from threading import Thread
#from multiprocessing import Process as Thread
import time import time
......
firmware/scripts/MarocReadoutThread.py
View file @ 2f031cf3
...@@ -21,13 +21,14 @@ from marocLogging import marocLogging ...@@ -21,13 +21,14 @@ from marocLogging import marocLogging
class MarocReadoutThread(Thread): class MarocReadoutThread(Thread):
"""Class with functions that can read out MAROC3 using IPBus. Inherits from threading class, so has a 'start' method""" """Class with functions that can read out MAROC3 using IPBus. Inherits from threading class, so has a 'start' method"""
def __init__(self, threadID, name, board , rawDataQueue , numTriggers, debugLevel=logging.DEBUG ): def __init__(self, threadID, name, board , rawDataQueue , numTriggers, numInternalTriggers , debugLevel=logging.DEBUG ):
Thread.__init__(self) Thread.__init__(self)
self.threadID = threadID self.threadID = threadID
self.board = board self.board = board
self.name = name self.name = name
self.rawDataQueue = rawDataQueue self.rawDataQueue = rawDataQueue
self.numTriggers = numTriggers self.numTriggers = numTriggers
self.numInternalTriggers = numInternalTriggers
self.debugLevel = debugLevel self.debugLevel = debugLevel
self.logger = logging.getLogger(__name__) self.logger = logging.getLogger(__name__)
self.lastEventRead = -1 self.lastEventRead = -1
...@@ -38,17 +39,17 @@ class MarocReadoutThread(Thread): ...@@ -38,17 +39,17 @@ class MarocReadoutThread(Thread):
self.logger.info( "Starting thread. Event limit = %i" %(self.numTriggers) ) self.logger.info( "Starting thread. Event limit = %i" %(self.numTriggers) )
self.readout_maroc(self.name, self.board , self.rawDataQueue , self.numTriggers , self.logger , self.debugLevel) self.readout_maroc(self.name, self.board , self.rawDataQueue , self.numTriggers , self.numInternalTriggers , self.logger , self.debugLevel)
self.logger.info( "Exiting thread" ) self.logger.info( "Exiting thread" )
def readout_maroc(self, name, board , rawDataQueue , numTriggers , logger , debugLevel): def readout_maroc(self, name, board , rawDataQueue , numTriggers , numInternalTriggers, logger , debugLevel):
exitFlag = False exitFlag = False
# Create pointer to MAROC board and set up structures. # Create pointer to MAROC board and set up structures.
marocData = MarocDAQ.MarocDAQ(board,debugLevel) marocData = MarocDAQ.MarocDAQ(board,debugLevel,numInternalTriggers)
# BODGE - wait for histogram thread to book histograms. # BODGE - wait for histogram thread to book histograms.
time.sleep(5) time.sleep(5)
...@@ -68,9 +69,10 @@ class MarocReadoutThread(Thread): ...@@ -68,9 +69,10 @@ class MarocReadoutThread(Thread):
# Try to detect and recover from buffer over-run # Try to detect and recover from buffer over-run
if (eventNumber != self.lastEventRead +1) and (self.lastEventRead != -1) : if (eventNumber != self.lastEventRead +1) and (self.lastEventRead != -1) :
logger.warn("Buffer over-run detected! Event read = %i , previous event = %i . Resetting read and write pointers " %(eventNumber,self.lastEventRead)) logger.warn("Buffer over-run detected!! Event read = %i , previous event = %i . Resetting read and write pointers " %(eventNumber,self.lastEventRead))
marocData.resetADCPointers() marocData.resetADCPointers()
self.lastEventRead = -1 self.lastEventRead = -1
eventNumber = -1
break # break out of loop and read another block of data. break # break out of loop and read another block of data.
self.lastEventRead = eventNumber self.lastEventRead = eventNumber
......
firmware/scripts/takeMarocData.py
View file @ 2f031cf3
...@@ -38,6 +38,8 @@ parser.add_option("-o", dest = 'outputFile' , default = 'marocTimeStamps.root' ) ...@@ -38,6 +38,8 @@ parser.add_option("-o", dest = 'outputFile' , default = 'marocTimeStamps.root' )
parser.add_option("-n" , dest = 'numTriggers' , default = 1000 ) parser.add_option("-n" , dest = 'numTriggers' , default = 1000 )
parser.add_option("-t" , dest = 'numInternalTriggers' , default = 0 )
parser.add_option("-c" , dest = 'configFile' , default = 'testADC_marocSC.csv' ) parser.add_option("-c" , dest = 'configFile' , default = 'testADC_marocSC.csv' )
(options, args) = parser.parse_args() (options, args) = parser.parse_args()
...@@ -47,6 +49,8 @@ logger.info("Board address table %s"%( options.boardAddressTable)) ...@@ -47,6 +49,8 @@ logger.info("Board address table %s"%( options.boardAddressTable))
numTriggers = int(options.numTriggers) numTriggers = int(options.numTriggers)
numInternalTriggers = int(options.numInternalTriggers)
logger.info("Event limit = %i "%( numTriggers)) logger.info("Event limit = %i "%( numTriggers))
bAddrTab = AddressTable(options.boardAddressTable) bAddrTab = AddressTable(options.boardAddressTable)
...@@ -71,7 +75,7 @@ histogramDataQueue = Queue(histogramQueueSize) ...@@ -71,7 +75,7 @@ histogramDataQueue = Queue(histogramQueueSize)
# Create a readout thread. Pass down an event limit. When the event limit is reached the readout thread will pass a message along chain and threads will terminate. # Create a readout thread. Pass down an event limit. When the event limit is reached the readout thread will pass a message along chain and threads will terminate.
readoutThread = MarocReadoutThread.MarocReadoutThread(1,"readoutThread",board,rawDataQueue,numTriggers,debugLevel=debugLevel) readoutThread = MarocReadoutThread.MarocReadoutThread(1,"readoutThread",board,rawDataQueue,numTriggers,numInternalTriggers,debugLevel=debugLevel)
unpackerThread = MarocUnpackingThread.MarocUnpackingThread(2,"unpackingThread",rawDataQueue,recordingDataQueue,histogramDataQueue,debugLevel=debugLevel) unpackerThread = MarocUnpackingThread.MarocUnpackingThread(2,"unpackingThread",rawDataQueue,recordingDataQueue,histogramDataQueue,debugLevel=debugLevel)
......
firmware/scripts/testADC_marocSC.csv
View file @ 2f031cf3
...@@ -46,6 +46,7 @@ mask_OR = 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, ...@@ -46,6 +46,7 @@ mask_OR = 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
Ctest_ch = 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 Ctest_ch = 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1
GAIN = 64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64 GAIN = 64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64
DAC = 650,450 DAC = 650,450
#DAC = 650,550
[registers] [registers]
trigSourceSelect = 13 trigSourceSelect = 13
......
firmware/syn/pc049a/demo/Manifest.py
View file @ 2f031cf3
target = "xilinx" target = "xilinx"
action = "synthesis" action = "synthesis"
fetchto = "../../../ip_cores" fetchto = "../../../ip_cores"
syn_device = "xc6slx45t" syn_device = "xc6slx100t"
syn_grade = "-3" syn_grade = "-3"
syn_package = "fgg484" syn_package = "fgg484"
syn_top = "pc049a_top" syn_top = "pc049a_top"
syn_project = "pc049a_top_demo.xise" syn_project = "pc049a_top_demo.xise"
syn_tool = "ise"
modules = { "local" : modules = { "local" : "../../../top/pc049a/demo",
[ "../../../top/pc049a/demo", "git" : "git://ohwr.org/hdl-core-lib/wr-cores.git"
"../../../whiteRabbit/wr-cores/platform",
"../../../whiteRabbit/wr-cores/ip_cores/general-cores",
"../../../whiteRabbit/wr-cores/ip_cores/etherbone-core",
"../../../whiteRabbit/wr-cores/ip_cores/gn4124-core"]
} }
firmware/top/pc049a/demo/pc049a_top.vhd
View file @ 2f031cf3
...@@ -289,7 +289,8 @@ architecture rtl of pc049a_top is ...@@ -289,7 +289,8 @@ architecture rtl of pc049a_top is
signal sfp_scl_i : std_logic_vector(1 downto 0); signal sfp_scl_i : std_logic_vector(1 downto 0);
signal sfp_sda_o : std_logic_vector(1 downto 0); signal sfp_sda_o : std_logic_vector(1 downto 0);
signal sfp_sda_i : std_logic_vector(1 downto 0); signal sfp_sda_i : std_logic_vector(1 downto 0);
--! White Rabbit Signals
signal dio : std_logic_vector(3 downto 0); signal dio : std_logic_vector(3 downto 0);
signal dac_hpll_load_p1 : std_logic; signal dac_hpll_load_p1 : std_logic;
...@@ -302,11 +303,13 @@ architecture rtl of pc049a_top is ...@@ -302,11 +303,13 @@ architecture rtl of pc049a_top is
signal phy_tx_data : std_logic_vector(7 downto 0); signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_k : std_logic; signal phy_tx_k : std_logic;
-- signal phy_tx_k : std_logic_vector(1 downto 0);
signal phy_tx_disparity : std_logic; signal phy_tx_disparity : std_logic;
signal phy_tx_enc_err : std_logic; signal phy_tx_enc_err : std_logic;
signal phy_rx_data : std_logic_vector(7 downto 0); signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_rx_rbclk : std_logic; signal phy_rx_rbclk : std_logic;
signal phy_rx_k : std_logic; signal phy_rx_k : std_logic;
-- signal phy_rx_k : std_logic_vector(1 downto 0);
signal phy_rx_enc_err : std_logic; signal phy_rx_enc_err : std_logic;
signal phy_rx_bitslide : std_logic_vector(3 downto 0); signal phy_rx_bitslide : std_logic_vector(3 downto 0);
signal phy_rst : std_logic; signal phy_rst : std_logic;
...@@ -547,12 +550,14 @@ begin ...@@ -547,12 +550,14 @@ begin
phy_ref_clk_i => clk_125m_pllref, phy_ref_clk_i => clk_125m_pllref,
phy_tx_data_o => phy_tx_data, phy_tx_data_o => phy_tx_data,
phy_tx_k_o => phy_tx_k, -- phy_tx_k_o => phy_tx_k,
phy_tx_k_o(0) => phy_tx_k,
phy_tx_disparity_i => phy_tx_disparity, phy_tx_disparity_i => phy_tx_disparity,
phy_tx_enc_err_i => phy_tx_enc_err, phy_tx_enc_err_i => phy_tx_enc_err,
phy_rx_data_i => phy_rx_data, phy_rx_data_i => phy_rx_data,
phy_rx_rbclk_i => phy_rx_rbclk, phy_rx_rbclk_i => phy_rx_rbclk,
phy_rx_k_i => phy_rx_k, phy_rx_k_i(0) => phy_rx_k,
-- phy_rx_k_i => phy_rx_k,
phy_rx_enc_err_i => phy_rx_enc_err, phy_rx_enc_err_i => phy_rx_enc_err,
phy_rx_bitslide_i => phy_rx_bitslide, phy_rx_bitslide_i => phy_rx_bitslide,
phy_rst_o => phy_rst, phy_rst_o => phy_rst,
......
firmware/top/pc049a/simple/pc049a_top.vhd
View file @ 2f031cf3
...@@ -568,7 +568,8 @@ begin ...@@ -568,7 +568,8 @@ begin
gpio(5) <= '0'; gpio(5) <= '0';
-- gpio(6) <= uart_txd; -- gpio(6) <= uart_txd;
-- uart_rxd <= gpio(7); -- uart_rxd <= gpio(7);
gpio(6) <= '0'; gpio(6) <= s_globaltrig_from_fpga;
-- gpio(6) <= '0';
s_gpio_trigger <= gpio(7); s_gpio_trigger <= gpio(7);
......
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