GHDL as simulator. It's based on VHDL generators.

Using Icarus Verilog for VHDL synthesis is still in an early stage, and
the tool is not able to handle arrays. Thus, the generated VHDL code is
always completely unrolled

Output signal is calculated by parsing VCD file

Include toolbar icons

Developed at CERN BE-CO H&T in the week 37 of year 2013.