- 01 Nov, 2013 2 commits
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Javier D. Garcia-Lasheras authored
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Javier D. Garcia-Lasheras authored
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- 31 Oct, 2013 3 commits
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Javier D. Garcia-Lasheras authored
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Javier D. Garcia-Lasheras authored
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Javier D. Garcia-Lasheras authored
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- 11 Oct, 2013 1 commit
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Javier D. Garcia-Lasheras authored
GHDL as simulator. It's based on VHDL generators. Using Icarus Verilog for VHDL synthesis is still in an early stage, and the tool is not able to handle arrays. Thus, the generated VHDL code is always completely unrolled
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- 05 Oct, 2013 2 commits
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Javier D. Garcia-Lasheras authored
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Javier D. Garcia-Lasheras authored
Output signal is calculated by parsing VCD file
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- 14 Sep, 2013 2 commits
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Javier D. Garcia-Lasheras authored
Include toolbar icons
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Javier D. Garcia-Lasheras authored
Developed at CERN BE-CO H&T in the week 37 of year 2013.
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