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Libre Filter Design and Analysis Tool
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5fd91c12
Commit
5fd91c12
authored
Oct 05, 2013
by
Javier D. Garcia-Lasheras
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Fix bug on VCD parsing mechanism
parent
19f17f15
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simcore.py
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simcore.py
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5fd91c12
...
@@ -493,6 +493,10 @@ class Simcore:
...
@@ -493,6 +493,10 @@ class Simcore:
vcdParsedOutput
.
pop
(
0
)
vcdParsedOutput
.
pop
(
0
)
#vcdBinaryOutput.pop(0)
#vcdBinaryOutput.pop(0)
# Expand signal to match stimulus length
for
ii
in
range
(
totalSamples
-
len
(
vcdParsedOutput
)):
vcdParsedOutput
.
append
(
vcdParsedOutput
[
len
(
vcdParsedOutput
)
-
1
])
connect_sample_out
=
np
.
zeros
(
len
(
vcdParsedOutput
))
connect_sample_out
=
np
.
zeros
(
len
(
vcdParsedOutput
))
for
ii
in
range
(
len
(
vcdParsedOutput
)):
for
ii
in
range
(
len
(
vcdParsedOutput
)):
connect_sample_out
[
ii
]
=
vcdParsedOutput
[
ii
]
connect_sample_out
[
ii
]
=
vcdParsedOutput
[
ii
]
...
...
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