Commit 008a9d93 authored by Mattia Rizzi's avatar Mattia Rizzi

Test bench with bootloader support

parent 07a15a52
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
package envm_sim_pkg is
type stdvector_array is array (natural range <>) of std_logic_vector (31 downto 0);
end package;
use work.envm_sim_pkg.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity envm_sim is
generic (
g_bootldr_text_offset : std_logic_vector (31 downto 0);
g_app_text_offset : std_logic_vector (31 downto 0);
g_app_data_offset : std_logic_vector (31 downto 0)
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
bootldr_text_image_i : stdvector_array;
app_text_image_i : stdvector_array;
app_data_image_i : stdvector_array;
apb_psel_i : in std_logic;
apb_pwr_i : in std_logic;
apb_pen_i : in std_logic;
apb_paddr_i : in std_logic_vector(31 downto 0);
apb_pwdat_i : in std_logic_vector(31 downto 0);
apb_prdat_o : out std_logic_vector(31 downto 0);
apb_pready_o : out std_logic; --
apb_pslverr_o : out std_logic
);
end entity envm_sim;
architecture rtl of envm_sim is
begin
process (clk_i)
begin
if rising_edge (clk_i) then
apb_prdat_o <= (others => '0');
apb_pready_o <= '0';
if (apb_psel_i = '1' and apb_pen_i = '1') then
apb_pready_o <= '1';
if (apb_paddr_i (31 downto 16) = g_app_text_offset (31 downto 16)) then
apb_prdat_o <= app_text_image_i (to_integer(unsigned(apb_paddr_i(31 downto 2))) - to_integer(unsigned(g_app_text_offset(31 downto 2))));
elsif (apb_paddr_i (31 downto 16) = g_app_data_offset (31 downto 16)) then
apb_prdat_o <= app_data_image_i(to_integer(unsigned(apb_paddr_i(31 downto 2))) - to_integer(unsigned(g_app_data_offset(31 downto 2))));
elsif (apb_paddr_i (31 downto 16) = g_bootldr_text_offset (31 downto 16)) then
apb_prdat_o <= bootldr_text_image_i(to_integer(unsigned(apb_paddr_i (31 downto 2))) - to_integer(unsigned(g_bootldr_text_offset(31 downto 2))));
elsif (apb_paddr_i = x"60080120") then -- busy bit check
apb_prdat_o <= x"00000001";
-- else
-- report "invalid address" severity failure;
end if;
end if;
end if;
end process;
end architecture;
\ No newline at end of file
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.math_real.all;
use work.envm_sim_pkg.all;
entity urv_tb is
end urv_tb;
architecture behav of urv_tb is
signal clk, clk_mac : std_logic;
signal rst : std_logic;
signal rst_cpu : std_logic;
signal tx_data : std_logic_vector (3 downto 0);
signal apb_psel : std_logic;
signal apb_pwr : std_logic;
signal apb_pen : std_logic;
signal apb_paddr : std_logic_vector(31 downto 0);
signal apb_pwdat : std_logic_vector(31 downto 0);
signal apb_prdat : std_logic_vector(31 downto 0);
signal apb_pready : std_logic; --
signal bootldr_text: stdvector_array (0 to 1024*64 - 1);
signal app_text: stdvector_array (0 to 1024*64 - 1);
signal app_data: stdvector_array (0 to 1024*64 - 1);
signal eth_tx_en : std_logic;
signal uart_tx : std_logic;
signal uart_tx_ecc : std_logic;
signal rx_d : std_logic_vector (3 downto 0);
signal rx_dv: std_logic;
subtype word_t is std_logic_vector(31 downto 0);
type word_array is array (natural range <>) of word_t;
type nibble_array is array (natural range <>) of std_logic_vector (3 downto 0);
signal clk_mac_rx, clk_mac_tx : std_logic;
signal lock_a,lock_b, grant_a, grant_b : std_logic;
signal aa,ab : std_logic_vector (15 downto 0);
constant frame : nibble_array := (x"f", x"f", x"f", x"f", x"f", x"f",x"f", x"f", x"f", x"f", x"f", x"f",x"0",x"a",x"0",x"0",x"3",x"0",x"b",x"5",x"2",x"8",x"0",x"1",x"0",x"8",x"0",x"6",x"0",x"0",x"0",x"1",x"0",x"8",x"0",x"0",x"0",x"6",x"0",x"4",x"0",x"0",x"0",x"1",x"0",x"a",x"0",x"0",x"3",x"0",x"b",x"5",x"2",x"8",x"0",x"1",x"8",x"0",x"8",x"d",x"a",x"2",x"0",x"1",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"8",x"0",x"8",x"d",x"a",x"2",x"f",x"c",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"0",x"8",x"1",x"5",x"2",x"1",x"e",x"d",x"c");
signal error_size, eth_tx_en_d : std_logic;
signal count_nibble : integer range 0 to 1023;
procedure read_binary(filename : string; data : out stdvector_array)
is
type char_file is file of character;
file f : char_file;
variable c : character;
variable b : std_logic_vector(7 downto 0);
variable w : std_logic_vector (31 downto 0);
variable addr : natural;
begin
data := (data'range => (others => '0'));
file_open(f, filename, READ_MODE);
addr := data'left;
while not endfile(f) loop
for i in 0 to 3 loop
read(f, c);
b := std_logic_vector(to_unsigned(character'pos(c), 8));
w (8*i + 7 downto 8*i) := b;
end loop;
data(addr) := w;
addr := addr + 1;
--report to_hstring(w) severity note;
end loop;
file_close(f);
end read_binary;
begin
envm_simulated : entity work.envm_sim
generic map (
g_bootldr_text_offset => x"60012000",
g_app_text_offset => x"60000000",
g_app_data_offset => x"60020000"
)
port map (
clk_i => clk,
rst_i => rst,
bootldr_text_image_i => bootldr_text,
app_text_image_i => app_text,
app_data_image_i => app_data,
apb_psel_i => apb_psel,
apb_pwr_i => apb_pwr,
apb_pen_i => apb_pen,
apb_paddr_i => apb_paddr,
apb_pwdat_i => apb_pwdat,
apb_prdat_o => apb_prdat,
apb_pready_o => apb_pready
);
soc: entity work.urv_soc
port map (
clk_i => clk,
clk_ram_i => (others => clk),
rst_i => rst,
apb_psel_o => apb_psel,
apb_pwr_o => apb_pwr,
apb_pen_o => apb_pen,
apb_paddr_o => apb_paddr,
apb_pwdat_o => apb_pwdat,
apb_prdat_i => apb_prdat,
apb_pready_i => apb_pready,
apb_pslverr_i => '0',
uart_tx_o => uart_tx,
eth_tx_clk_i => clk_mac_TX,
eth_rx_clk_i => clk_mac_RX,
eth_rxd_i => rx_d,
eth_txd_o => tx_data,
eth_rxdv_i => rx_dv,
eth_rxerr_i => '0',
eth_md_i => '0',
eth_txen_o => eth_tx_en,
devrst_i => rst
-- irq_i => irq
);
process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end process;
process
begin
wait for 10ns;
loop
clk_mac_RX <= '0';
wait for 19.347654 ns;
clk_mac_RX <= '1';
wait for 19.24667 ns;
end loop;
end process;
process
begin
loop
clk_mac_TX <= '0';
wait for 19.1 ns;
clk_mac_TX <= '1';
wait for 19.1 ns;
end loop;
end process;
process
variable data : stdvector_array(0 to 1024*64 - 1);
-- variable i : integer;
begin
rst <= '1';
read_binary ("bootldr.bin", data);
bootldr_text <= data;
read_binary ("app_text.bin", data);
app_text <= data;
read_binary ("app_data.bin", data);
app_data <= data;
wait for 1ms;
rst <= '0';
--write_memory(arm_iram_psel, arm_iram_pwr, arm_iram_pen, arm_iram_paddr, arm_iram_pwdat, arm_iram_pready, mem_code);
--write_memory(arm_iram_bank1_psel, arm_iram_bank1_pwr, arm_iram_bank1_pen, arm_iram_bank1_paddr, arm_iram_bank1_pwdat, arm_iram_bank1_pready, mem_code);
--write_memory(arm_dram_psel, arm_dram_pwr, arm_dram_pen, arm_dram_paddr, arm_dram_pwdat, arm_dram_pready, mem_data);
wait until rising_edge(clk);
report "Starting CPU" severity note;
rst_cpu <= '0';
wait for 1 ms;
loop
wait for 10000 ns;
--read_memory(144, arm_dram_psel, arm_dram_pwr, arm_dram_pen, arm_dram_paddr, arm_dram_prdat, arm_dram_pready);
end loop;
wait;
end process;
process
begin
wait until rising_edge(clk);
--secded ecc
wait until rising_edge(clk);
wait for 1ms;
--secded ecc
rx_dv <= '0';
rx_d <= x"0";
wait for 9 ms;
for k in 1 to 10000 loop
wait for 205 ms;
for i in 1 to 15 loop
wait until rising_edge(clk_mac_rx);
rx_d <= x"5";
rx_dv <= '1';
end loop;
wait until rising_edge(clk_mac_rx);
rx_d <= x"D";
for i in 1 to (frame'length/2) loop
wait until rising_edge(clk_mac_rx);
rx_d <= frame(2*i-1);
wait until rising_edge(clk_mac_rx);
rx_d <= frame(2*i-2);
end loop;
for i in 1 to (frame'length/2) loop
wait until rising_edge(clk_mac_rx);
rx_d <= frame(2*i-1);
wait until rising_edge(clk_mac_rx);
rx_d <= frame(2*i-2);
end loop;
for i in 1 to (frame'length/2) loop
wait until rising_edge(clk_mac_rx);
rx_d <= frame(2*i-1);
wait until rising_edge(clk_mac_rx);
rx_d <= frame(2*i-2);
end loop;
for i in 1 to (frame'length/2) loop
wait until rising_edge(clk_mac_rx);
rx_d <= frame(2*i-1);
wait until rising_edge(clk_mac_rx);
rx_d <= frame(2*i-2);
end loop;
wait until rising_edge(clk_mac_rx);
rx_d <= x"0";
rx_dv <= '0';
end loop;
end process;
end behav;
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