diff --git a/hdl/dpram_generic.vhd b/hdl/dpram_generic.vhd
index 87fdd9a456e2b7cfff7eb5df2983317c2b191b0d..99d3637e059b26ab05c13887be76e8cb49b41bb0 100644
--- a/hdl/dpram_generic.vhd
+++ b/hdl/dpram_generic.vhd
@@ -9,11 +9,9 @@ use ieee.numeric_std.all;
entity dpram_generic is
-
generic (
g_addr_width : natural := 15;
g_data_width : natural := 42
-
);
port (
clk_i : in std_logic;
@@ -38,55 +36,51 @@ entity dpram_generic is
qb_o : out std_logic_vector(g_data_width-1 downto 0);
valid_a_o : out std_logic;
valid_b_o : out std_logic
-
-
);
end dpram_generic;
-
architecture rtl of dpram_generic is
component RAM1K18
--- generic (MEMORYFILE:string := "");
-
- port(A_DOUT : out std_logic_vector(17 downto 0);
- B_DOUT : out std_logic_vector(17 downto 0);
- BUSY : out std_logic;
- A_CLK : in std_logic := 'U';
- A_DOUT_CLK : in std_logic := 'U';
- A_ARST_N : in std_logic := 'U';
- A_DOUT_EN : in std_logic := 'U';
- A_BLK : in std_logic_vector(2 downto 0) := (others => 'U');
- A_DOUT_ARST_N : in std_logic := 'U';
- A_DOUT_SRST_N : in std_logic := 'U';
- A_DIN : in std_logic_vector(17 downto 0) := (others => 'U');
- A_ADDR : in std_logic_vector(13 downto 0) := (others => 'U');
- A_WEN : in std_logic_vector(1 downto 0) := (others => 'U');
- B_CLK : in std_logic := 'U';
- B_DOUT_CLK : in std_logic := 'U';
- B_ARST_N : in std_logic := 'U';
- B_DOUT_EN : in std_logic := 'U';
- B_BLK : in std_logic_vector(2 downto 0) := (others => 'U');
- B_DOUT_ARST_N : in std_logic := 'U';
- B_DOUT_SRST_N : in std_logic := 'U';
- B_DIN : in std_logic_vector(17 downto 0) := (others => 'U');
- B_ADDR : in std_logic_vector(13 downto 0) := (others => 'U');
- B_WEN : in std_logic_vector(1 downto 0) := (others => 'U');
- A_EN : in std_logic := 'U';
- A_DOUT_LAT : in std_logic := 'U';
- A_WIDTH : in std_logic_vector(2 downto 0) := (others => 'U');
- A_WMODE : in std_logic := 'U';
- B_EN : in std_logic := 'U';
- B_DOUT_LAT : in std_logic := 'U';
- B_WIDTH : in std_logic_vector(2 downto 0) := (others => 'U');
- B_WMODE : in std_logic := 'U';
- SII_LOCK : in std_logic := 'U'
- );
+ -- generic (MEMORYFILE:string := "");
+ port (
+ A_DOUT : out std_logic_vector(17 downto 0);
+ B_DOUT : out std_logic_vector(17 downto 0);
+ BUSY : out std_logic;
+ A_CLK : in std_logic := 'U';
+ A_DOUT_CLK : in std_logic := 'U';
+ A_ARST_N : in std_logic := 'U';
+ A_DOUT_EN : in std_logic := 'U';
+ A_BLK : in std_logic_vector(2 downto 0) := (others => 'U');
+ A_DOUT_ARST_N : in std_logic := 'U';
+ A_DOUT_SRST_N : in std_logic := 'U';
+ A_DIN : in std_logic_vector(17 downto 0) := (others => 'U');
+ A_ADDR : in std_logic_vector(13 downto 0) := (others => 'U');
+ A_WEN : in std_logic_vector(1 downto 0) := (others => 'U');
+ B_CLK : in std_logic := 'U';
+ B_DOUT_CLK : in std_logic := 'U';
+ B_ARST_N : in std_logic := 'U';
+ B_DOUT_EN : in std_logic := 'U';
+ B_BLK : in std_logic_vector(2 downto 0) := (others => 'U');
+ B_DOUT_ARST_N : in std_logic := 'U';
+ B_DOUT_SRST_N : in std_logic := 'U';
+ B_DIN : in std_logic_vector(17 downto 0) := (others => 'U');
+ B_ADDR : in std_logic_vector(13 downto 0) := (others => 'U');
+ B_WEN : in std_logic_vector(1 downto 0) := (others => 'U');
+ A_EN : in std_logic := 'U';
+ A_DOUT_LAT : in std_logic := 'U';
+ A_WIDTH : in std_logic_vector(2 downto 0) := (others => 'U');
+ A_WMODE : in std_logic := 'U';
+ B_EN : in std_logic := 'U';
+ B_DOUT_LAT : in std_logic := 'U';
+ B_WIDTH : in std_logic_vector(2 downto 0) := (others => 'U');
+ B_WMODE : in std_logic := 'U';
+ SII_LOCK : in std_logic := 'U'
+ );
end component;
signal qa, qb, da, db : std_logic_vector (g_data_width downto 0);
-
- signal addr_match : std_logic;
+ signal addr_match : std_logic;
signal lock_a_req, lock_b_req : std_logic;
signal lock_contention : std_logic;
@@ -94,21 +88,17 @@ architecture rtl of dpram_generic is
signal lock_a_grant, lock_b_grant, lock_a_grant_d, lock_b_grant_d : std_logic;
signal wea, web : std_logic_vector (39 downto 0);
-
-
+
signal qa_discard_32k, qb_discard_32k : std_logic_vector (17 downto 2);
- signal qa_discard_64k, qb_discard_64k : std_logic_vector (17 downto 1);
+ signal qa_discard_64k, qb_discard_64k : std_logic_vector (17 downto 1);
- signal rea, reb : std_logic;
- signal wa_voted, wb_voted : std_logic;
-attribute syn_radhardlevel : string;
-attribute syn_radhardlevel of rtl : architecture is "tmr";
+ signal wa_voted : std_logic;
+ attribute syn_radhardlevel : string;
+ attribute syn_radhardlevel of rtl : architecture is "tmr";
begin
-
-
addr_match <= '1' when (aa_i (7 downto 2) = ab_i (7 downto 2)) else '0'; --to save LUTs, overhead
- --is only 0.5% (random address)
+ --is only 0.5% (random address)
da <= "0" & da_i;
db <= "0" & db_i;
qa_o <= qa (g_data_width-1 downto 0);
@@ -118,43 +108,35 @@ begin
wa_voted <= ( (wa_i(1) and wa_i(2)) or (wa_i(1) and wa_i(3)) or (wa_i(2) and wa_i(3))) ;
process (lock_b_grant, lock_a_grant, addr_match, ra_i, rb_i, wa_voted, wb_i)
- begin
-
- if (lock_b_grant = '1') then
- valid_b_o <= '1';
+ begin
+ if (lock_b_grant = '1') then
+ valid_b_o <= '1';
else
valid_b_o <= '0' when (((rb_i and wa_voted) or lock_a_grant) and addr_match) else '1';
- end if;
+ end if;
- if (lock_a_grant = '1') then
+ if (lock_a_grant = '1') then
valid_a_o <= '1';
-else
- valid_a_o <= '0' when (((ra_i and wb_i) or lock_b_grant) and addr_match) else '1';
-end if;
-end process;
-
-
-tmr_signals : for i in 0 to 39 generate
- wea (i) <= ( (wa_i(1) and wa_i(2)) or (wa_i(1) and wa_i(3)) or (wa_i(2) and wa_i(3))) and valid_a_o;
- -- "web" signal not TMRed (it requires a block TMR of the scrubber)
- web (i) <= wb_i and valid_b_o;
-end generate;
-
-
-
+ else
+ valid_a_o <= '0' when (((ra_i and wb_i) or lock_b_grant) and addr_match) else '1';
+ end if;
+ end process;
+
+ tmr_signals : for i in 0 to 39 generate
+ wea (i) <= ( (wa_i(1) and wa_i(2)) or (wa_i(1) and wa_i(3)) or (wa_i(2) and wa_i(3))) and valid_a_o;
+ -- "web" signal not TMRed (it requires a block TMR of the scrubber)
+ web (i) <= wb_i and valid_b_o;
+ end generate;
lock_a_grant_o <= lock_a_grant;
lock_b_grant_o <= lock_b_grant;
lock_contention <= addr_match and lock_a_req_i and lock_b_req_i;
-
-
lock_a_req <= lock_a_req_i;
lock_b_req <= lock_b_req_i;
-assert ( (lock_a_grant_o and lock_b_grant_o and addr_match) = '0') report "error grant" severity error;
-
+ assert ( (lock_a_grant_o and lock_b_grant_o and addr_match) = '0') report "error grant" severity error;
process (clk_i, rst_i)
begin
@@ -162,19 +144,17 @@ assert ( (lock_a_grant_o and lock_b_grant_o and addr_match) = '0') report "error
if rst_i = '1' then
lock_a_grant_d <= '0';
lock_b_grant_d <= '0';
- else
- lock_a_grant_d <= lock_a_grant;
- lock_b_grant_d <= lock_b_grant;
-
+ else
+ lock_a_grant_d <= lock_a_grant;
+ lock_b_grant_d <= lock_b_grant;
+ end if;
end if;
- end if;
end process;
-- lock_a/b_req signal, after the write is done, will always be deasserted for at least one clock cycle
process (lock_contention, lock_a_req, lock_b_req, lock_a_grant_d, lock_b_grant_d)
begin
-
if (lock_contention = '0') then
lock_a_grant <= lock_a_req;
lock_b_grant <= lock_b_req;
@@ -184,198 +164,178 @@ assert ( (lock_a_grant_o and lock_b_grant_o and addr_match) = '0') report "error
lock_b_grant <= '1';
lock_a_grant <= '0';
elsif (lock_a_req = '1') then
- lock_a_grant <= '1';
- lock_b_grant <= '0';
- else
- lock_a_grant <= '0';
- lock_b_grant <= '0';
- end if;
- else
- lock_a_grant <= lock_a_grant_d;
- lock_b_grant <= lock_b_grant_d;
- end if;
+ lock_a_grant <= '1';
+ lock_b_grant <= '0';
+ else
+ lock_a_grant <= '0';
+ lock_b_grant <= '0';
+ end if;
+ else
+ lock_a_grant <= lock_a_grant_d;
+ lock_b_grant <= lock_b_grant_d;
+ end if;
end if;
-
end process;
- gen_32k_daec : if (g_addr_width = 15 and g_data_width = 42) generate
+ gen_32k_daec : if (g_addr_width = 15 and g_data_width = 42) generate
gen_bram : for i in 1 to 5 generate
gen_byte : for k in 0 to 3 generate
- sram_two_bit : RAM1K18
-
- port map(
- A_WIDTH => "001",
- B_WIDTH => "001",
- A_WMODE => '1', --write data appears on the corresponding read data port
- B_WMODE => '1', --write data appears on the corresponding read data port
- A_DOUT_LAT => '1',
- B_DOUT_LAT => '1',
- A_EN => '1',
- B_EN => '1',
- A_ARST_N => '1',
- B_ARST_N => '1',
- A_DOUT_EN => '1',
- B_DOUT_EN => '1',
- A_DOUT_SRST_N => '1',
- B_DOUT_SRST_N => '1',
- A_DOUT_ARST_N => '1',
- B_DOUT_ARST_N => '1',
- SII_LOCK => '1',
- A_DOUT_CLK => '1',
- B_DOUT_CLK => '1',
-
- A_CLK => clk_ram_i (8*(i-1)+k),
- B_CLK => clk_ram_i (8*(i-1)+k),
-
- A_WEN (1) => '0',
- A_WEN (0) => wea (8*(i-1)+2*k),
- B_WEN (1) => '0',
- B_WEN (0) => web (8*(i-1)+2*k),
-
- A_DIN (1 downto 0) => da(8*(i-1)+2*k+1 downto 8*(i-1)+2*k) ,
- A_DIN (17 downto 2) => (others => '0'),
- B_DIN (1 downto 0) => db(8*(i-1)+2*k+1 downto 8*(i-1)+2*k),
- B_DIN (17 downto 2) => (others => '0'),
-
- A_ADDR (0 downto 0) => "0",
- A_ADDR (13 downto 1) => aa_i(14 downto 2),
- B_ADDR (0 downto 0) => "0",
- B_ADDR (13 downto 1) => ab_i(14 downto 2),
-
-
- A_BLK => (others => '1'),
- B_BLK => (others => '1'),
-
-
- A_DOUT (17 downto 2) => qa_discard_32k (17 downto 2),
- A_DOUT (1 downto 0) => qa(8*(i-1)+2*k+1 downto 8*(i-1)+2*k),
- b_DOUT (17 downto 2) => qb_discard_32k (17 downto 2),
- B_DOUT (1 downto 0) => qb(8*(i-1)+2*k+1 downto 8*(i-1)+2*k)
-
- );
-
+ inst_sram_two_bit : RAM1K18
+
+ port map(
+ A_WIDTH => "001",
+ B_WIDTH => "001",
+ A_WMODE => '1', --write data appears on the corresponding read data port
+ B_WMODE => '1', --write data appears on the corresponding read data port
+ A_DOUT_LAT => '1',
+ B_DOUT_LAT => '1',
+ A_EN => '1',
+ B_EN => '1',
+ A_ARST_N => '1',
+ B_ARST_N => '1',
+ A_DOUT_EN => '1',
+ B_DOUT_EN => '1',
+ A_DOUT_SRST_N => '1',
+ B_DOUT_SRST_N => '1',
+ A_DOUT_ARST_N => '1',
+ B_DOUT_ARST_N => '1',
+ SII_LOCK => '1',
+ A_DOUT_CLK => '1',
+ B_DOUT_CLK => '1',
+
+ A_CLK => clk_ram_i (8*(i-1)+k),
+ B_CLK => clk_ram_i (8*(i-1)+k),
+
+ A_WEN (1) => '0',
+ A_WEN (0) => wea (8*(i-1)+2*k),
+ B_WEN (1) => '0',
+ B_WEN (0) => web (8*(i-1)+2*k),
+
+ A_DIN (1 downto 0) => da(8*(i-1)+2*k+1 downto 8*(i-1)+2*k) ,
+ A_DIN (17 downto 2) => (others => '0'),
+ B_DIN (1 downto 0) => db(8*(i-1)+2*k+1 downto 8*(i-1)+2*k),
+ B_DIN (17 downto 2) => (others => '0'),
+
+ A_ADDR (0 downto 0) => "0",
+ A_ADDR (13 downto 1) => aa_i(14 downto 2),
+ B_ADDR (0 downto 0) => "0",
+ B_ADDR (13 downto 1) => ab_i(14 downto 2),
+
+ A_BLK => (others => '1'),
+ B_BLK => (others => '1'),
+
+ A_DOUT (17 downto 2) => qa_discard_32k (17 downto 2),
+ A_DOUT (1 downto 0) => qa(8*(i-1)+2*k+1 downto 8*(i-1)+2*k),
+ b_DOUT (17 downto 2) => qb_discard_32k (17 downto 2),
+ B_DOUT (1 downto 0) => qb(8*(i-1)+2*k+1 downto 8*(i-1)+2*k)
+ );
end generate gen_byte;
-
end generate gen_bram;
- sram_two_bit : RAM1K18
-
- port map(
- A_WIDTH => "001",
- B_WIDTH => "001",
- A_WMODE => '1', --write data appears on the corresponding read data port
- B_WMODE => '1', --write data appears on the corresponding read data port
- A_DOUT_LAT => '1',
- B_DOUT_LAT => '1',
- A_EN => '1',
- B_EN => '1',
- A_ARST_N => '1',
- B_ARST_N => '1',
- A_DOUT_EN => '1',
- B_DOUT_EN => '1',
- A_DOUT_SRST_N => '1',
- B_DOUT_SRST_N => '1',
- A_DOUT_ARST_N => '1',
- B_DOUT_ARST_N => '1',
- SII_LOCK => '1',
- A_DOUT_CLK => '1',
- B_DOUT_CLK => '1',
-
- A_CLK => clk_i,
- B_CLK => clk_i,
-
- A_WEN (1) => '0',
- A_WEN (0) => wea (39),
- B_WEN (1) => '0',
- B_WEN (0) => web (39),
-
- A_DIN (1 downto 0) => da(41 downto 40),
- A_DIN (17 downto 2) => (others => '0'),
- B_DIN (1 downto 0) => db(41 downto 40),
- B_DIN (17 downto 2) => (others => '0'),
-
- A_ADDR (0 downto 0) => "0",
- A_ADDR (13 downto 1) => aa_i(14 downto 2),
- B_ADDR (0 downto 0) => "0",
- B_ADDR (13 downto 1) => ab_i(14 downto 2),
-
- A_BLK => (others => '1'),
- B_BLK => (others => '1'),
-
- A_DOUT (17 downto 2) => qa_discard_32k(17 downto 2),
- A_DOUT (1 downto 0) => qa(41 downto 40),
- b_DOUT (17 downto 2) => qb_discard_32k(17 downto 2),
- B_DOUT (1 downto 0) => qb(41 downto 40)
-
- );
-
-
+ sram_two_bit : RAM1K18
+ port map(
+ A_WIDTH => "001",
+ B_WIDTH => "001",
+ A_WMODE => '1', --write data appears on the corresponding read data port
+ B_WMODE => '1', --write data appears on the corresponding read data port
+ A_DOUT_LAT => '1',
+ B_DOUT_LAT => '1',
+ A_EN => '1',
+ B_EN => '1',
+ A_ARST_N => '1',
+ B_ARST_N => '1',
+ A_DOUT_EN => '1',
+ B_DOUT_EN => '1',
+ A_DOUT_SRST_N => '1',
+ B_DOUT_SRST_N => '1',
+ A_DOUT_ARST_N => '1',
+ B_DOUT_ARST_N => '1',
+ SII_LOCK => '1',
+ A_DOUT_CLK => '1',
+ B_DOUT_CLK => '1',
+
+ A_CLK => clk_i,
+ B_CLK => clk_i,
+
+ A_WEN (1) => '0',
+ A_WEN (0) => wea (39),
+ B_WEN (1) => '0',
+ B_WEN (0) => web (39),
+
+ A_DIN (1 downto 0) => da(41 downto 40),
+ A_DIN (17 downto 2) => (others => '0'),
+ B_DIN (1 downto 0) => db(41 downto 40),
+ B_DIN (17 downto 2) => (others => '0'),
+
+ A_ADDR (0 downto 0) => "0",
+ A_ADDR (13 downto 1) => aa_i(14 downto 2),
+ B_ADDR (0 downto 0) => "0",
+ B_ADDR (13 downto 1) => ab_i(14 downto 2),
+
+ A_BLK => (others => '1'),
+ B_BLK => (others => '1'),
+
+ A_DOUT (17 downto 2) => qa_discard_32k(17 downto 2),
+ A_DOUT (1 downto 0) => qa(41 downto 40),
+ b_DOUT (17 downto 2) => qb_discard_32k(17 downto 2),
+ B_DOUT (1 downto 0) => qb(41 downto 40)
+ );
end generate gen_32k_daec;
gen_64k : if g_addr_width = 16 generate
-
gen_bram : for i in 1 to 5 generate
-
gen_byte : for k in 0 to 7 generate
-
sram_bit : RAM1K18
-
- port map(
- A_WIDTH => "000",
- B_WIDTH => "000",
- A_WMODE => '1', --write data appears on the corresponding read data port
- B_WMODE => '1', --write data appears on the corresponding read data port
- A_DOUT_LAT => '1',
- B_DOUT_LAT => '1',
- A_EN => '1',
- B_EN => '1',
- A_ARST_N => '1',
- B_ARST_N => '1',
- A_DOUT_EN => '1',
- B_DOUT_EN => '1',
- A_DOUT_SRST_N => '1',
- B_DOUT_SRST_N => '1',
- A_DOUT_ARST_N => '1',
- B_DOUT_ARST_N => '1',
- SII_LOCK => '1',
- A_DOUT_CLK => '1',
- B_DOUT_CLK => '1',
-
- A_CLK => clk_ram_i (8*(i-1)+k),
- B_CLK => clk_ram_i (8*(i-1)+k),
-
- A_WEN (1) => '0',
- A_WEN (0) => wea (8*(i-1)+k),
- B_WEN (1) => '0',
- B_WEN (0) => web (8*(i-1)+k),
-
- A_DIN (0 downto 0) => da(8*(i-1)+k downto 8*(i-1)+k),
- A_DIN (17 downto 1) => (others => '0'),
- B_DIN (0 downto 0) => db(8*(i-1)+k downto 8*(i-1)+k),
- B_DIN (17 downto 1) => (others => '0'),
-
- --A_ADDR (0 downto 0) => "0",
- A_ADDR (13 downto 0) => aa_i(15 downto 2),
- --B_ADDR (0 downto 0) => "0",
- B_ADDR (13 downto 0) => ab_i(15 downto 2),
-
-
- A_BLK => (others => '1'),
- B_BLK => (others => '1'),
-
- A_DOUT (17 downto 1) => qa_discard_64k,
- A_DOUT (0 downto 0) => qa(8*(i-1)+k downto 8*(i-1)+k),
- b_DOUT (17 downto 1) => qb_discard_64k,
- B_DOUT (0 downto 0) => qb(8*(i-1)+k downto 8*(i-1)+k)
-
- );
+ port map(
+ A_WIDTH => "000",
+ B_WIDTH => "000",
+ A_WMODE => '1', --write data appears on the corresponding read data port
+ B_WMODE => '1', --write data appears on the corresponding read data port
+ A_DOUT_LAT => '1',
+ B_DOUT_LAT => '1',
+ A_EN => '1',
+ B_EN => '1',
+ A_ARST_N => '1',
+ B_ARST_N => '1',
+ A_DOUT_EN => '1',
+ B_DOUT_EN => '1',
+ A_DOUT_SRST_N => '1',
+ B_DOUT_SRST_N => '1',
+ A_DOUT_ARST_N => '1',
+ B_DOUT_ARST_N => '1',
+ SII_LOCK => '1',
+ A_DOUT_CLK => '1',
+ B_DOUT_CLK => '1',
+
+ A_CLK => clk_ram_i (8*(i-1)+k),
+ B_CLK => clk_ram_i (8*(i-1)+k),
+
+ A_WEN (1) => '0',
+ A_WEN (0) => wea (8*(i-1)+k),
+ B_WEN (1) => '0',
+ B_WEN (0) => web (8*(i-1)+k),
+
+ A_DIN (0 downto 0) => da(8*(i-1)+k downto 8*(i-1)+k),
+ A_DIN (17 downto 1) => (others => '0'),
+ B_DIN (0 downto 0) => db(8*(i-1)+k downto 8*(i-1)+k),
+ B_DIN (17 downto 1) => (others => '0'),
+
+ --A_ADDR (0 downto 0) => "0",
+ A_ADDR (13 downto 0) => aa_i(15 downto 2),
+ --B_ADDR (0 downto 0) => "0",
+ B_ADDR (13 downto 0) => ab_i(15 downto 2),
+
+ A_BLK => (others => '1'),
+ B_BLK => (others => '1'),
+
+ A_DOUT (17 downto 1) => qa_discard_64k,
+ A_DOUT (0 downto 0) => qa(8*(i-1)+k downto 8*(i-1)+k),
+ b_DOUT (17 downto 1) => qb_discard_64k,
+ B_DOUT (0 downto 0) => qb(8*(i-1)+k downto 8*(i-1)+k)
+ );
end generate gen_byte;
-
end generate gen_bram;
- end generate gen_64k;
-
-
-
- end architecture;
\ No newline at end of file
+ end generate gen_64k;
+end architecture;
diff --git a/hdl/ram_voter.vhd b/hdl/ram_voter.vhd
index 84f1cb8ce2ddd2df2b08c407edc6009f02646b04..1f6bc85583c79364acec5baea750998827121ea3 100644
--- a/hdl/ram_voter.vhd
+++ b/hdl/ram_voter.vhd
@@ -23,52 +23,40 @@ use ieee.numeric_std.all;
use work.voter.all;
entity ram_voter is
- generic (
- g_addr_width : natural := 15;
- g_data_width : natural := 38
-
- );
- port (
- da_vot_i : in t_voter_stdvector (open)(g_data_width-1 downto 0);
- aa_vot_i : in t_voter_stdvector (open) (g_addr_width-1 downto 0);
- wa_vot_i : in t_voter_stdlogic;
- ra_vot_i : in t_voter_stdlogic;
-
- lock_a_req_vot_i : in t_voter_stdlogic;
-
- da_o : out std_logic_vector (g_data_width-1 downto 0);
- aa_o : out std_logic_vector (g_addr_width-1 downto 0);
- wa_o : out std_logic;
- ra_o : out std_logic;
- lock_a_req_o : out std_logic
-
-
- );
-
-
+ generic (
+ g_addr_width : natural := 15;
+ g_data_width : natural := 38
+ );
+ port (
+ da_vot_i : in t_voter_stdvector (open)(g_data_width-1 downto 0);
+ aa_vot_i : in t_voter_stdvector (open) (g_addr_width-1 downto 0);
+ wa_vot_i : in t_voter_stdlogic;
+ ra_vot_i : in t_voter_stdlogic;
+
+ lock_a_req_vot_i : in t_voter_stdlogic;
+
+ da_o : out std_logic_vector (g_data_width-1 downto 0);
+ aa_o : out std_logic_vector (g_addr_width-1 downto 0);
+ wa_o : out std_logic;
+ ra_o : out std_logic;
+ lock_a_req_o : out std_logic
+ );
end ram_voter;
architecture rtl of ram_voter is
-
-
begin
da : for i in da_o'range generate
da_o(i) <= (da_vot_i(1)(i) and da_vot_i(2)(i)) or (da_vot_i(2)(i) and da_vot_i(3)(i)) or (da_vot_i(1)(i) and da_vot_i(3)(i));
-
end generate;
aa : for i in aa_o'range generate
aa_o(i) <= (aa_vot_i(1)(i) and aa_vot_i(2)(i)) or (aa_vot_i(2)(i) and aa_vot_i(3)(i)) or (aa_vot_i(1)(i) and aa_vot_i(3)(i));
-
end generate;
wa_o <= (wa_vot_i(1) and wa_vot_i(2)) or (wa_vot_i(2) and wa_vot_i(3)) or (wa_vot_i(1) and wa_vot_i(3));
ra_o <= (ra_vot_i(1) and ra_vot_i(2)) or (ra_vot_i(2) and ra_vot_i(3)) or (ra_vot_i(1) and ra_vot_i(3));
-
lock_a_req_o <= (lock_a_req_vot_i(1) and lock_a_req_vot_i(2)) or (lock_a_req_vot_i(2) and lock_a_req_vot_i(3)) or (lock_a_req_vot_i(1) and lock_a_req_vot_i(3));
-
-
end architecture;
diff --git a/hdl/secded_ecc.vhd b/hdl/secded_ecc.vhd
index 4650e2ce96ce8c5d7b0e22dd923e14788af1f687..9f5d17b5faed65b2b2c28e1f32fe8aa836801357 100644
--- a/hdl/secded_ecc.vhd
+++ b/hdl/secded_ecc.vhd
@@ -165,7 +165,6 @@ architecture rtl of secded_ecc is
end f_ecc_errors;
function f_ecc_one_error (syndrome : std_logic_vector (6 downto 0)) return std_logic is
- variable syndrome_bound_check : std_logic;
begin
if Is_x (syndrome (0)) then
return '0';
diff --git a/hdl/seu_counters.vhd b/hdl/seu_counters.vhd
index b86b2b0786fc38a71f14ded90ad1b57e10e88cf2..946ae7f96d52f0e97351222656f4a1c68602cb43 100644
--- a/hdl/seu_counters.vhd
+++ b/hdl/seu_counters.vhd
@@ -13,12 +13,8 @@ use work.wishbone_pkg.all;
--use smartfusion2.all;
use work.voter.all;
-use work.wb_voter_pkg.all;
-
-
entity seu_counters is
-
port (
clk_i : in std_logic;
rst_i : in std_logic;
@@ -34,16 +30,14 @@ entity seu_counters is
se_iram_o : out std_logic_vector (15 downto 0);
de_iram_o : out std_logic_vector (15 downto 0)
-
);
-
end entity seu_counters;
architecture rtl of seu_counters is
signal se_iram_counter,de_iram_counter,se_dram_counter,de_dram_counter : unsigned (15 downto 0);
- attribute syn_radhardlevel : string;
-attribute syn_radhardlevel of rtl : architecture is "tmr";
+ attribute syn_radhardlevel : string;
+ attribute syn_radhardlevel of rtl : architecture is "tmr";
begin
diff --git a/hdl/urv_core_DTMR.vhd b/hdl/urv_core_DTMR.vhd
index 9c0cfda5ef6eed2906c1426afd5870584c50e2e8..2d124197c20bfa4a61edeeb4193618ff83e064f5 100644
--- a/hdl/urv_core_DTMR.vhd
+++ b/hdl/urv_core_DTMR.vhd
@@ -187,12 +187,12 @@ end component;
signal im_addr, dm_addr, dram_addr : std_logic_vector(31 downto 0);
- signal im_data, im_data_cpu, im_data_bank1, dram_data_in, dram_data_out : std_logic_vector(31 downto 0);
- signal im_valid, im_valid_cpu, im_valid_bank1 : std_logic;
+ signal im_data, dram_data_in, dram_data_out : std_logic_vector(31 downto 0);
+ signal im_valid : std_logic;
- signal dm_data_s, dm_data_l, dm_data_ram, dm_wb_rdata : std_logic_vector(31 downto 0);
+ signal dm_data_s, dm_data_l, dm_wb_rdata : std_logic_vector(31 downto 0);
signal dm_data_select, dram_bwe : std_logic_vector(3 downto 0);
- signal dm_load, dm_store, dm_done, dm_ready, dram_we, dram_re : std_logic;
+ signal dm_load, dm_store, dram_we, dram_re : std_logic;
signal dram_done_r, dram_done_w : std_logic;
signal dm_is_wishbone, dm_cycle_in_progress, dm_load_done_wb, dm_store_done_wb : std_logic;
@@ -384,11 +384,11 @@ end generate;
dram_addr <= (others => '0');
else
-- signals from uRV data interface to the data-ram are sampled to improve fmax
- if (dram_done_r or dram_done_w) then
+ if (dram_done_r or dram_done_w) then
dram_we <= '0';
dram_re <= '0';
- end if;
-
+ end if;
+
if (dm_is_wishbone = '0' and (dm_load = '1' or dm_store = '1')) then
dram_addr <= dm_addr;
dram_data_in <= dm_data_s;
@@ -420,7 +420,7 @@ end generate;
dm_load_done_wb <= '0';
dm_cycle_in_progress <= '0';
end if;
-
+
else
if(cpu_dwb_i.stall = '0') then
cpu_dwb_o.stb <= '0';
diff --git a/hdl/urv_soc.vhd b/hdl/urv_soc.vhd
index 43683dbf66aa293720c0a2dd649f289f306726ca..852e1239c6f84d668ffea57bd2b5f30a4f471f5b 100644
--- a/hdl/urv_soc.vhd
+++ b/hdl/urv_soc.vhd
@@ -1,82 +1,69 @@
-
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use STD.textio.all;
-
library work;
use work.wishbone_pkg.all;
-
-
use work.voter.ALL;
use work.wb_master_voter_pkg.all;
use work.wb_slave_voter_pkg.all;
entity urv_soc is
-
port (
- clk_i : in std_logic;
- clk_ram_i : in std_logic_vector (39 downto 0);
- rst_i : in std_logic;
-
- DEVRST_I : in std_logic;
+ clk_i : in std_logic;
+ clk_ram_i : in std_logic_vector (39 downto 0);
+ rst_i : in std_logic;
+ DEVRST_I : in std_logic;
apb_psel_o : out std_logic;
- apb_pwr_o : out std_logic;
- apb_pen_o : out std_logic;
- apb_paddr_o : out std_logic_vector(31 downto 0);
- apb_pwdat_o : out std_logic_vector(31 downto 0);
- apb_prdat_i : in std_logic_vector(31 downto 0);
- apb_pready_i : in std_logic; --
- apb_pslverr_i : in std_logic; --
-
-
- uart_tx_o : out std_logic;
+ apb_pwr_o : out std_logic;
+ apb_pen_o : out std_logic;
+ apb_paddr_o : out std_logic_vector(31 downto 0);
+ apb_pwdat_o : out std_logic_vector(31 downto 0);
+ apb_prdat_i : in std_logic_vector(31 downto 0);
+ apb_pready_i : in std_logic; --
+ apb_pslverr_i : in std_logic; --
+ uart_tx_o : out std_logic;
--TX
- eth_tx_clk_i : in std_logic;
- eth_txd_o : out std_logic_vector (3 downto 0);
- eth_txen_o : out std_logic;
- eth_txerr_o : out std_logic;
+ eth_tx_clk_i : in std_logic;
+ eth_txd_o : out std_logic_vector (3 downto 0);
+ eth_txen_o : out std_logic;
+ eth_txerr_o : out std_logic;
--RX
- eth_rx_clk_i : in std_logic;
- eth_rxd_i : in std_logic_vector (3 downto 0);
- eth_rxdv_i : in std_logic;
- eth_rxerr_i : in std_logic;
-
+ eth_rx_clk_i : in std_logic;
+ eth_rxd_i : in std_logic_vector (3 downto 0);
+ eth_rxdv_i : in std_logic;
+ eth_rxerr_i : in std_logic;
--MIIM
- eth_mdc_o : out std_logic;
- eth_md_i : in std_logic;
- eth_md_o : out std_logic;
- eth_oe_o : out std_logic;
-
- eth_rst_o : out std_logic;
-
- reboot_o : out std_logic
- );
+ eth_mdc_o : out std_logic;
+ eth_md_i : in std_logic;
+ eth_md_o : out std_logic;
+ eth_oe_o : out std_logic;
+ eth_rst_o : out std_logic;
+
+ reboot_o : out std_logic
+ );
end entity urv_soc;
architecture rtl of urv_soc is
-
-
-constant g_dram_data_width : integer := 39;
-constant g_dram_addr_width : integer := 16;
-constant g_m2s090 : boolean := true;
+ constant g_dram_data_width : integer := 39;
+ constant g_dram_addr_width : integer := 16;
+ constant g_m2s090 : boolean := true;
function f_voter_stdlogic (a : std_logic; b : std_logic; c : std_logic) return std_logic is
begin
- return (a and b) or (a and c) or (b and c);
+ return (a and b) or (a and c) or (b and c);
end f_voter_stdlogic;
-
component uart
port (
reset_i : in std_logic;
@@ -88,863 +75,602 @@ constant g_m2s090 : boolean := true;
tx_req_i : in std_logic);
end component;
+ constant c_SLAVE_NUM : natural := 7;
+ -- only one master to reduce LUT
+ -- tested in radiation also with 2 masters, no problems
+ constant c_MASTER_NUM : natural := 1;
+
+ constant c_SLAVE_WD : integer := 0;
+ constant c_SLAVE_UART : integer := 1;
+ constant c_SLAVE_SEC : integer := 2;
+ constant c_SLAVE_ETH : integer := 3;
+ constant c_SLAVE_DRAM : integer := 4;
+ constant c_SLAVE_SUPERVISOR : integer := 5;
+ constant c_SLAVE_ENVM : integer := 6;
+
+ constant c_CNX_ADDRESS : t_wishbone_address_array(c_SLAVE_NUM-1 downto 0) := (
+ c_SLAVE_WD => x"81000000",
+ c_SLAVE_UART => x"82000000",
+ c_SLAVE_SEC => x"83000000",
+ c_SLAVE_ETH => x"84000000",
+ c_SLAVE_DRAM => x"85000000",
+ c_SLAVE_SUPERVISOR => x"86000000",
+ c_SLAVE_ENVM => x"87000000"
+ );
- component xwb_uart
-
- port(
- clk_sys_i : in std_logic;
- rst_i : in std_logic;
-
- -- Wishbone
- slave_i : in t_wishbone_slave_in;
- slave_o : out t_wishbone_slave_out;
- desc_o : out t_wishbone_device_descriptor;
-
--- Port for BIT field: 'TX busy' in reg: 'Status Register'
- uart_sr_tx_busy_i : in std_logic;
--- Port for MONOSTABLE field: 'TX trigger' in reg: 'Status Register'
- uart_sr_tx_send_o : out std_logic;
- uart_tdr_tx_data_o : out std_logic_vector(7 downto 0)
+ constant c_CNX_MASK : t_wishbone_address_array(c_SLAVE_NUM-1 downto 0) := (
+ c_SLAVE_WD => x"ff000000",
+ c_SLAVE_UART => x"ff000000",
+ c_SLAVE_SEC => x"ff000000",
+ c_SLAVE_ETH => x"FF000000",
+ c_SLAVE_DRAM => x"FF000000",
+ c_SLAVE_SUPERVISOR => x"ff000000",
+ c_SLAVE_ENVM => x"FF000000"
+ );
+ signal cnx_master_in : t_wishbone_master_in_array(c_SLAVE_NUM-1 downto 0);
+ signal cnx_master_out : t_wishbone_master_out_array(c_SLAVE_NUM-1 downto 0);
+ signal cnx_slave_in : t_wishbone_slave_in_array(c_MASTER_NUM-1 downto 0);
+ signal cnx_slave_out : t_wishbone_slave_out_array(c_MASTER_NUM-1 downto 0);
+
+
+ signal cpu_dwb_out_voted : t_wishbone_master_out;
+ signal cpu_dwb_out : t_voter_wb_master;
+ signal cpu_dwb_in : t_wishbone_master_in;
+
+ signal envm_wb_iram_in : t_wishbone_slave_in;
+ signal envm_wb_iram_out : t_wishbone_slave_out;
+
+ signal eth_m_wb_out : t_wishbone_master_out;
+ signal eth_m_wb_in : t_wishbone_master_in;
+
+ signal supervisor_wb_out : t_voter_wb_slave;
+ signal rst_cpu_sv, reboot_sv, boot_done_sv : std_logic_vector (3 downto 1);
+ signal reboot_sv_voted : std_logic;
+ signal boot_done : std_logic;
+
+ signal first_de : std_logic;
+
+ type fsm_uart_states is (idle, wait_write, wait_lf);
+ signal fsm_uart : fsm_uart_states := idle;
+
+ signal uart_ready, uart_ready_wb, dm_uart_write_done : std_logic;
+ signal uart_tx_data, uart_tx_data_wb : std_logic_vector (7 downto 0);
+
+ signal rst_cpu, rst_cpu_boot, rst_cpu_wd : std_logic;
+ signal wd_counter : unsigned (28 downto 0);
+
+ signal wd_heartbeat : std_logic;
+
+ signal tx_req, tx_req_wb : std_logic;
+
+
+ signal q_cpu_iram : t_voter_stdvector (open)(38 downto 0);
+ signal q_cpu_dram : t_voter_stdvector(open)(g_dram_data_width-1 downto 0);
+ signal a_cpu_iram : t_voter_stdvector (open)(15 downto 0);
+ signal a_cpu_dram : t_voter_stdvector (open)(g_dram_addr_width-1 downto 0);
+ signal we_cpu_iram, we_cpu_dram : std_logic_vector (3 downto 1);
+ signal re_cpu_iram, re_cpu_dram : t_voter_stdlogic;
+ signal lock_cpu_dram_req, lock_cpu_iram_req : t_voter_stdlogic;
+ signal d_cpu_iram, d_wb_iram : std_logic_vector (38 downto 0);
+ signal d_cpu_dram, d_wb_dram : std_logic_vector (g_dram_data_width-1 downto 0);
+ signal q_cpu_iram_voted, q_wb_iram : std_logic_vector (38 downto 0);
+ signal q_cpu_dram_voted, q_wb_dram : std_logic_vector (g_dram_data_width-1 downto 0);
+
+ signal a_cpu_iram_voted, a_wb_iram : std_logic_vector (15 downto 0);
+ signal a_cpu_dram_voted, a_wb_dram : std_logic_vector (g_dram_addr_width-1 downto 0);
+ signal re_cpu_iram_voted, re_cpu_dram_voted, re_wb_dram, re_wb_iram : std_logic;
+ signal we_wb_dram, we_wb_iram : std_logic;
+ signal lock_cpu_dram_req_voted, lock_wb_dram_req : std_logic;
+ signal lock_cpu_iram_req_voted, lock_wb_iram_req : std_logic;
+ signal lock_cpu_dram_grant, lock_wb_dram_grant : std_logic;
+ signal lock_wb_iram_grant, lock_cpu_iram_grant : std_logic;
+ signal valid_cpu_iram, valid_cpu_dram, valid_wb_iram, valid_wb_dram : std_logic;
+
+ signal se_iram, se_dram : std_logic_vector (1 to 3);
+ signal de_iram, de_dram : std_logic_vector (1 to 3);
+
+ signal se_iram_voted, se_dram_voted, de_iram_voted, de_dram_voted : std_logic;
+ signal se_iram_scrubber, de_iram_scrubber : std_logic;
+ signal se_dram_scrubber, de_dram_scrubber : std_logic;
+
+ signal reboot_board : std_logic;
+
+ signal irq_eth : std_logic;
+ signal se_iram_counts, de_iram_counts, se_dram_counts, de_dram_counts : std_logic_vector (15 downto 0);
+
+ signal first_time : std_logic;
+
+ attribute syn_radhardlevel : string;
+ attribute syn_radhardlevel of rtl : architecture is "tmr";
+begin
+ rst_cpu <= rst_cpu_boot;
+
+ reboot_board <= rst_cpu_wd or reboot_sv_voted; --(not rst_cpu and (de_iram_voted or de_dram_voted or de_iram_scrubber or de_dram_scrubber)) ;
+ reboot_o <= reboot_board;
+
+ iram : entity work.dpram_generic
+ generic map (
+ g_addr_width => 16,
+ g_data_width => 39)
+ port map (
+ clk_i => clk_i,
+ clk_ram_i => clk_ram_i,
+ rst_i => rst_i,
+ da_i => q_cpu_iram_voted,
+ db_i => q_wb_iram,
+ aa_i => a_cpu_iram_voted,
+ ab_i => a_wb_iram,
+ wa_i => we_cpu_iram,--we_cpu_iram_voted,
+ wb_i => we_wb_iram,
+ ra_i => re_cpu_iram_voted,
+ rb_i => re_wb_iram,
+
+ lock_a_req_i => lock_cpu_iram_req_voted,
+ lock_b_req_i => lock_wb_iram_req,
+ lock_a_grant_o => lock_cpu_iram_grant,
+ lock_b_grant_o => lock_wb_iram_grant,
+
+ qa_o => d_cpu_iram,
+ qb_o => d_wb_iram,
+ valid_a_o => valid_cpu_iram,
+ valid_b_o => valid_wb_iram
);
- end component;
-
-
- component xwb_seu_regs
-
- port(
- clk_sys_i : in std_logic;
- rst_i : in std_logic;
-
- -- Wishbone
- slave_i : in t_wishbone_slave_in;
- slave_o : out t_wishbone_slave_out;
- desc_o : out t_wishbone_device_descriptor;
-
-
- iram_seu_regs_see_se_i : in std_logic_vector(15 downto 0);
- iram_seu_regs_see_de_i : in std_logic_vector(15 downto 0);
- dram_seu_regs_see_se_i : in std_logic_vector(15 downto 0);
- dram_seu_regs_see_de_i : in std_logic_vector(15 downto 0)
+ iram_voter : entity work.ram_voter
+ generic map (
+ g_addr_width => 16,
+ g_data_width => 39
+ )
+ port map (
+ da_vot_i => q_cpu_iram,
+ aa_vot_i => a_cpu_iram,
+ wa_vot_i => (others => '0'), --we_cpu_iram,
+ ra_vot_i => re_cpu_iram,
+
+ lock_a_req_vot_i => lock_cpu_iram_req,
+ lock_a_req_o => lock_cpu_iram_req_voted,
+
+ da_o => q_cpu_iram_voted,
+ aa_o => a_cpu_iram_voted,
+ -- wa_o => we_cpu_iram_voted,
+ ra_o => re_cpu_iram_voted
);
- end component;
-
-
- component xwb_wd_reg
-
- port(
- clk_sys_i : in std_logic;
- rst_i : in std_logic;
+ dram : entity work.dpram_generic
+ generic map (
+ g_addr_width => g_dram_addr_width,
+ g_data_width => g_dram_data_width)
+ port map (
+ clk_i => clk_i,
+ clk_ram_i => clk_ram_i,
+ rst_i => rst_i,
+ da_i => q_cpu_dram_voted,
+ db_i => q_wb_dram,
+ aa_i => a_cpu_dram_voted,
+ ab_i => a_wb_dram,
+ wa_i => we_cpu_dram,--we_cpu_dram_voted,
+ wb_i => we_wb_dram,
+ ra_i => re_cpu_dram_voted,
+ rb_i => re_wb_dram,
+
+ lock_a_req_i => lock_cpu_dram_req_voted,
+ lock_b_req_i => lock_wb_dram_req,
+ lock_a_grant_o => lock_cpu_dram_grant,
+ lock_b_grant_o => lock_wb_dram_grant,
+
+ qa_o => d_cpu_dram,
+ qb_o => d_wb_dram,
+ valid_a_o => valid_cpu_dram,
+ valid_b_o => valid_wb_dram
+ );
+
+ dram_voter : entity work.ram_voter
+ generic map(
+ g_addr_width => g_dram_addr_width,
+ g_data_width => g_dram_data_width)
+ port map (
+ da_vot_i => q_cpu_dram,
+ aa_vot_i => a_cpu_dram,
+ wa_vot_i => (others => '0'), --we_cpu_dram,
+ ra_vot_i => re_cpu_dram,
+
+ lock_a_req_vot_i => lock_cpu_dram_req,
+ lock_a_req_o => lock_cpu_dram_req_voted,
+
+ da_o => q_cpu_dram_voted,
+ aa_o => a_cpu_dram_voted,
+ --wa_o => we_cpu_dram_voted,
+ ra_o => re_cpu_dram_voted
+ );
+
+ gen_cores : for k in 1 to 3 generate
+
+ urv_core : entity work.urv_core_DTMR
+ generic map (
+ g_m2s090 => g_m2s090,
+ g_dram_data_width => g_dram_data_width,
+ g_dram_addr_width => g_dram_addr_width
+ )
+ port map (
+ clk_i => clk_i,
+ rst_i => rst_cpu or rst_cpu_sv (k), --(1)rst_cpu_sv(k), --rst_cpu,
+
+ -- to the IRAM primitive
+ d_iram_i => d_cpu_iram,
+ q_iram_o => q_cpu_iram(k),
+ a_iram_o => a_cpu_iram(k),
+ we_iram_o => we_cpu_iram(k),
+ re_iram_o => re_cpu_iram(k),
+ valid_iram_i => valid_cpu_iram,
+ lock_iram_req_o => lock_cpu_iram_req(k),
+ lock_iram_grant_i => lock_cpu_iram_grant,
+
+ -- to the DRAM primitive
+ d_dram_i => d_cpu_dram,
+ q_dram_o => q_cpu_dram(k),
+ a_dram_o => a_cpu_dram(k),
+ we_dram_o => we_cpu_dram(k),
+ re_dram_o => re_cpu_dram(k),
+ valid_dram_i => valid_cpu_dram,
+ lock_dram_req_o => lock_cpu_dram_req(k),
+ lock_dram_grant_i => lock_cpu_dram_grant,
+
+ iram_single_error_p_o => se_iram(k),
+ iram_double_error_p_o => de_iram(k),
+
+ dram_single_error_p_o => se_dram(k),
+ dram_double_error_p_o => de_dram(k),
+ irq_i => irq_eth,
+ -- to the Wishbone xbar
+ cpu_dwb_o => cpu_dwb_out(k),
+ cpu_dwb_i => cpu_dwb_in
+ );
+
+ supervisor : entity work.urv_supervisor
+ generic map (
+ g_cpu_id => k)
+ port map(
+ clk_i => clk_i,
+ rst_i => rst_i,
+
+ slave_i => cnx_master_out(c_SLAVE_SUPERVISOR),
+ slave_o => supervisor_wb_out (k),
+
+ pc_i => a_cpu_iram,
+ stall_i => ('0', '0', '0'),
+ boot_done_o => boot_done_sv (k),
+ rst_cpu_o => rst_cpu_sv (k),
+ reboot_o => reboot_sv (k)
+ );
+ end generate;
+
+ wb_cpu_voter : entity work.wb_master_voter
+ port map (
+ m_wb_i => cpu_dwb_out,
+ m_wb_o => cpu_dwb_out_voted
+ );
- -- Wishbone
- slave_i : in t_wishbone_slave_in;
- slave_o : out t_wishbone_slave_out;
- desc_o : out t_wishbone_device_descriptor;
- -- Port for MONOSTABLE field: 'Heartbeat' in reg: 'Watchdog'
- wd_reg_heartbeat_o : out std_logic
+ wb_supervisor_voter : entity work.wb_slave_voter
+ port map (
+ s_wb_i => supervisor_wb_out,
+ s_wb_o => cnx_master_in(c_SLAVE_SUPERVISOR)
);
- end component;
+ reboot_sv_voted <= f_voter_stdlogic (reboot_sv(1), reboot_sv(2), reboot_sv(3));
+ boot_done <= f_voter_stdlogic (boot_done_sv (1), boot_done_sv(2),boot_done_sv(3));
+
+ se_iram_voted <= f_voter_stdlogic(se_iram (1), se_iram(2), se_iram(3));
+ se_dram_voted <= f_voter_stdlogic(se_dram (1), se_dram(2), se_dram(3));
+ de_iram_voted <= f_voter_stdlogic(de_iram (1), de_iram(2), de_iram(3));
+ de_dram_voted <= f_voter_stdlogic(de_dram (1), de_dram(2), de_dram(3));
+ envm_wb : entity work.wb_envm
+ port map (
+ clk_i => clk_i,
+ rst_i => rst_i,
+ rst_cpu_o => rst_cpu_boot,
- component xwb_ram_adapter
+ apb_psel_o => apb_psel_o,
+ apb_pwr_o => apb_pwr_o,
+ apb_pen_o => apb_pen_o,
+ apb_paddr_o => apb_paddr_o,
+ apb_pwdat_o => apb_pwdat_o,
+ apb_prdat_i => apb_prdat_i,
+ apb_pready_i => apb_pready_i,
- generic (
- g_addr_width : natural := 15;
- g_data_width :natural := 38;
- g_is_iram : boolean := false;
- g_is_dram : boolean := false
+ master_i => envm_wb_iram_out,
+ master_o => envm_wb_iram_in,
+ slave_i => cnx_master_out (c_SLAVE_ENVM),
+ slave_o => cnx_master_in (c_SLAVE_ENVM)
);
- port (
- clk_i : in std_logic;
- rst_i : in std_logic;
- boot_done_i : in std_logic;
+
+ xwb_iram : entity work.xwb_ram_adapter
+ generic map (
+ g_addr_width => 16,
+ g_data_width => 39,
+ g_is_iram => true,
+ g_is_dram => false
+ )
+ port map(
+ clk_i => clk_i,
+ rst_i => rst_i,
+ boot_done_i => boot_done,
-- Wishbone
- slave_i : in t_wishbone_slave_in;
- slave_o : out t_wishbone_slave_out;
+ slave_i => envm_wb_iram_in,
+ slave_o => envm_wb_iram_out,
-- ram interface
- d_ram_i : in std_logic_vector (g_data_width-1 downto 0);
- q_ram_o : out std_logic_vector (g_data_width-1 downto 0);
- a_ram_o : out std_logic_vector (g_addr_width-1 downto 0);
- we_ram_o : out std_logic;
- re_ram_o : out std_logic;
- valid_ram_i : in std_logic;
- lock_req_o : out std_logic;
- lock_grant_i : in std_logic;
- single_error_p_o : out std_logic;
- double_error_p_o : out std_logic
-
- );
- end component;
-
-
-
- component dpram_generic
-
- generic (
- g_addr_width : natural := 15;
- g_data_width : natural := 38
+ d_ram_i => d_wb_iram,
+ q_ram_o => q_wb_iram,
+ a_ram_o => a_wb_iram,
+ we_ram_o => we_wb_iram,
+ re_ram_o => re_wb_iram,
+ valid_ram_i => valid_wb_iram,
+ lock_req_o => lock_wb_iram_req,
+ lock_grant_i => lock_wb_iram_grant,
+ single_error_p_o => se_iram_scrubber,
+ double_error_p_o => de_iram_scrubber
);
- port (
- clk_i : in std_logic;
- rst_i : in std_logic;
- clk_ram_i : in std_logic_vector (39 downto 0);
- da_i : in std_logic_vector(g_data_width-1 downto 0);
- db_i : in std_logic_vector(g_data_width-1 downto 0);
- aa_i : in std_logic_vector(g_addr_width-1 downto 0);
- ab_i : in std_logic_vector(g_addr_width-1 downto 0);
- wa_i : in std_logic_vector (3 downto 1);
- wb_i : in std_logic;
- ra_i : in std_logic;
- rb_i : in std_logic;
-
- qa_o : out std_logic_vector(g_data_width-1 downto 0);
- qb_o : out std_logic_vector(g_data_width-1 downto 0);
-
- lock_a_req_i : in std_logic;
- lock_b_req_i : in std_logic;
- lock_a_grant_o : out std_logic;
- lock_b_grant_o : out std_logic;
-
- valid_a_o : out std_logic;
- valid_b_o : out std_logic
-
-
- );
- end component;
-
-
-
-
- component ram_voter
- generic (
- g_addr_width : natural := 15;
- g_data_width : natural := 38
-
- );
- port (
-
-
- da_vot_i : in t_voter_stdvector;
- aa_vot_i : in t_voter_stdvector;
- wa_vot_i : in t_voter_stdlogic;
- ra_vot_i : in t_voter_stdlogic;
-
- lock_a_req_vot_i : in t_voter_stdlogic;
-
- da_o : out std_logic_vector(g_data_width-1 downto 0);
- aa_o : out std_logic_vector(g_addr_width-1 downto 0);
- wa_o : out std_logic;
- ra_o : out std_logic;
- lock_a_req_o : out std_logic
- );
-
-
- end component;
-
-
-
-
-component seu_counters is
- port (
- clk_i : in std_logic;
- rst_i : in std_logic;
-
- event_se_iram : in std_logic;
- event_de_iram : in std_logic;
- event_se_dram : in std_logic;
- event_de_dram : in std_logic;
-
-
- se_dram_o : out std_logic_vector (15 downto 0);
- de_dram_o : out std_logic_vector (15 downto 0);
-
- se_iram_o : out std_logic_vector (15 downto 0);
- de_iram_o : out std_logic_vector (15 downto 0)
-
- );
-
-end component;
-
-
- constant c_SLAVE_NUM : natural := 7;
- -- only one master to reduce LUT
- -- tested in radiation also with 2 masters, no problems
- constant c_MASTER_NUM : natural := 1;
-
- constant c_SLAVE_WD : integer := 0;
- constant c_SLAVE_UART : integer := 1;
- constant c_SLAVE_SEC : integer := 2;
- constant c_SLAVE_ETH : integer := 3;
- constant c_SLAVE_DRAM : integer := 4;
- constant c_SLAVE_SUPERVISOR : integer := 5;
- constant c_SLAVE_ENVM : integer := 6;
-
- constant c_CNX_ADDRESS : t_wishbone_address_array(c_SLAVE_NUM-1 downto 0) := (
- c_SLAVE_WD => x"81000000",
- c_SLAVE_UART => x"82000000",
- c_SLAVE_SEC => x"83000000",
- c_SLAVE_ETH => x"84000000",
- c_SLAVE_DRAM => x"85000000",
- c_SLAVE_SUPERVISOR => x"86000000",
- c_SLAVE_ENVM => x"87000000"
- );
-
- constant c_CNX_MASK : t_wishbone_address_array(c_SLAVE_NUM-1 downto 0) := (
- c_SLAVE_WD => x"ff000000",
- c_SLAVE_UART => x"ff000000",
- c_SLAVE_SEC => x"ff000000",
- c_SLAVE_ETH => x"FF000000",
- c_SLAVE_DRAM => x"FF000000",
- c_SLAVE_SUPERVISOR => x"ff000000",
- c_SLAVE_ENVM => x"FF000000"
-
- );
-
- signal cnx_master_in : t_wishbone_master_in_array(c_SLAVE_NUM-1 downto 0);
- signal cnx_master_out : t_wishbone_master_out_array(c_SLAVE_NUM-1 downto 0);
- signal cnx_slave_in : t_wishbone_slave_in_array(c_MASTER_NUM-1 downto 0);
- signal cnx_slave_out : t_wishbone_slave_out_array(c_MASTER_NUM-1 downto 0);
-
-
- signal cpu_dwb_out_voted : t_wishbone_master_out;
- signal cpu_dwb_out : t_voter_wb_master;
- signal cpu_dwb_in : t_wishbone_master_in;
-
- signal envm_wb_iram_in: t_wishbone_slave_in;
- signal envm_wb_iram_out : t_wishbone_slave_out;
-
- signal eth_m_wb_out : t_wishbone_master_out;
- signal eth_m_wb_in : t_wishbone_master_in;
-
- signal supervisor_wb_out : t_voter_wb_slave;
- signal rst_cpu_sv, reboot_sv, boot_done_sv : std_logic_vector (3 downto 1);
- signal rst_cpu_sv_voted, reboot_sv_voted : std_logic;
- signal boot_done : std_logic;
-
- signal cpu_rst, cpu_rst_d : std_logic;
-
-
-
- signal first_de : std_logic;
-
- signal de_counter, se_counter : unsigned (15 downto 0);
-
- type fsm_uart_states is (idle, wait_write, wait_lf);
- signal fsm_uart : fsm_uart_states := idle;
-
- signal uart_ready, uart_ready_wb, dm_uart_write_done : std_logic;
- signal uart_tx_data, uart_tx_data_wb : std_logic_vector (7 downto 0);
- signal dm_counter_read_done, dm_uart_read_done : std_logic;
-
- signal rst_cpu, rst_cpu_boot, rst_cpu_wd : std_logic;
- signal wd_counter : unsigned (28 downto 0);
- signal dm_counter_write_done : std_logic;
-
- signal wd_heartbeat : std_logic;
-
- signal tx_req, tx_req_wb : std_logic;
-
-
- signal q_cpu_iram : t_voter_stdvector (open)(38 downto 0);
- signal q_cpu_dram : t_voter_stdvector(open)(g_dram_data_width-1 downto 0);
- signal a_cpu_iram : t_voter_stdvector (open)(15 downto 0);
- signal a_cpu_dram : t_voter_stdvector (open)(g_dram_addr_width-1 downto 0);
- signal we_cpu_iram, we_cpu_dram : std_logic_vector (3 downto 1);
- signal re_cpu_iram, re_cpu_dram : t_voter_stdlogic;
- signal lock_cpu_dram_req, lock_cpu_iram_req : t_voter_stdlogic;
-signal selector : std_logic;
- signal d_cpu_iram, d_wb_iram, d_cpu_iram_seu : std_logic_vector (38 downto 0);
- signal d_cpu_dram, d_wb_dram : std_logic_vector (g_dram_data_width-1 downto 0);
- signal q_cpu_iram_voted, q_wb_iram : std_logic_vector (38 downto 0);
-signal q_cpu_dram_voted, q_wb_dram : std_logic_vector (g_dram_data_width-1 downto 0);
-
- signal a_cpu_iram_voted, a_wb_iram : std_logic_vector (15 downto 0);
- signal a_cpu_dram_voted, a_wb_dram : std_logic_vector (g_dram_addr_width-1 downto 0);
- signal re_cpu_iram_voted, re_cpu_dram_voted, re_wb_dram, re_wb_iram : std_logic;
- signal we_cpu_iram_voted, we_cpu_dram_voted, we_wb_dram, we_wb_iram : std_logic;
- signal lock_cpu_dram_req_voted, lock_wb_dram_req, lock_cpu_dram_grant, lock_wb_dram_grant : std_logic;
- signal lock_cpu_iram_req_voted, lock_wb_iram_req, lock_wb_iram_grant, lock_cpu_iram_grant : std_logic;
- signal valid_cpu_iram, valid_cpu_dram, valid_wb_iram, valid_wb_dram : std_logic;
-
- signal se_iram, se_dram : std_logic_vector (1 to 3);
- signal de_iram, de_dram : std_logic_vector (1 to 3);
-
- signal se_iram_voted, se_dram_voted, de_iram_voted, de_dram_voted : std_logic;
- signal se_iram_scrubber, de_iram_scrubber : std_logic;
- signal se_dram_scrubber, de_dram_scrubber : std_logic;
-
- signal reboot_board, reboot_board_f : std_logic;
-
- signal irq_eth : std_logic;
- signal uart_debug_ready, tx_debug_req : std_logic;
- signal uart_debug_data : std_logic_vector (7 downto 0);
- signal se_iram_counts, de_iram_counts, se_dram_counts, de_dram_counts : std_logic_vector (15 downto 0);
-
-
- signal first_time : std_logic;
-
- attribute syn_radhardlevel : string;
- attribute syn_radhardlevel of rtl : architecture is "tmr";
-
- begin
-
- rst_cpu <= rst_cpu_boot;
-
- reboot_board <= rst_cpu_wd or reboot_sv_voted; --(not rst_cpu and (de_iram_voted or de_dram_voted or de_iram_scrubber or de_dram_scrubber)) ;
- reboot_o <= reboot_board;
-
-
-
- iram : dpram_generic
- generic map (
- g_addr_width => 16,
- g_data_width => 39)
- port map (
- clk_i => clk_i,
- clk_ram_i => clk_ram_i,
- rst_i => rst_i,
- da_i => q_cpu_iram_voted,
- db_i => q_wb_iram,
- aa_i => a_cpu_iram_voted,
- ab_i => a_wb_iram,
- wa_i => we_cpu_iram,--we_cpu_iram_voted,
- wb_i => we_wb_iram,
- ra_i => re_cpu_iram_voted,
- rb_i => re_wb_iram,
-
- lock_a_req_i => lock_cpu_iram_req_voted,
- lock_b_req_i => lock_wb_iram_req,
- lock_a_grant_o => lock_cpu_iram_grant,
- lock_b_grant_o => lock_wb_iram_grant,
-
- qa_o => d_cpu_iram,
- qb_o => d_wb_iram,
- valid_a_o => valid_cpu_iram,
- valid_b_o => valid_wb_iram
-
- );
-
-
-
- iram_voter : ram_voter
- generic map(
- g_addr_width => 16,
- g_data_width => 39
- )
- port map (
- da_vot_i => q_cpu_iram,
- aa_vot_i => a_cpu_iram,
- wa_vot_i => (others => '0'), --we_cpu_iram,
- ra_vot_i => re_cpu_iram,
-
- lock_a_req_vot_i => lock_cpu_iram_req,
- lock_a_req_o => lock_cpu_iram_req_voted,
-
- da_o => q_cpu_iram_voted,
- aa_o => a_cpu_iram_voted,
- -- wa_o => we_cpu_iram_voted,
- ra_o => re_cpu_iram_voted
- );
-
-
- dram : dpram_generic
- generic map (
- g_addr_width => g_dram_addr_width,
- g_data_width => g_dram_data_width)
- port map (
- clk_i => clk_i,
- clk_ram_i => clk_ram_i,
- rst_i => rst_i,
- da_i => q_cpu_dram_voted,
- db_i => q_wb_dram,
- aa_i => a_cpu_dram_voted,
- ab_i => a_wb_dram,
- wa_i => we_cpu_dram,--we_cpu_dram_voted,
- wb_i => we_wb_dram,
- ra_i => re_cpu_dram_voted,
- rb_i => re_wb_dram,
-
-
- lock_a_req_i => lock_cpu_dram_req_voted,
- lock_b_req_i => lock_wb_dram_req,
- lock_a_grant_o => lock_cpu_dram_grant,
- lock_b_grant_o => lock_wb_dram_grant,
-
- qa_o => d_cpu_dram,
- qb_o => d_wb_dram,
- valid_a_o => valid_cpu_dram,
- valid_b_o => valid_wb_dram
-
-
- );
+ xwb_dram : entity work.xwb_ram_adapter
+ generic map (
+ g_addr_width => g_dram_addr_width,
+ g_data_width => g_dram_data_width,
+ g_is_iram => false,
+ g_is_dram => true
+ )
+ port map(
+ clk_i => clk_i,
+ rst_i => rst_i,
+ boot_done_i => boot_done,
-
-
- dram_voter : ram_voter
- generic map(
- g_addr_width => g_dram_addr_width,
- g_data_width => g_dram_data_width)
- port map (
- da_vot_i => q_cpu_dram,
- aa_vot_i => a_cpu_dram,
- wa_vot_i => (others => '0'), --we_cpu_dram,
- ra_vot_i => re_cpu_dram,
-
- lock_a_req_vot_i => lock_cpu_dram_req,
- lock_a_req_o => lock_cpu_dram_req_voted,
-
- da_o => q_cpu_dram_voted,
- aa_o => a_cpu_dram_voted,
- --wa_o => we_cpu_dram_voted,
- ra_o => re_cpu_dram_voted
- );
-
-
-
+ -- Wishbone
+ slave_i => eth_m_wb_out, --cnx_master_out(c_SLAVE_DRAM),
+ slave_o => eth_m_wb_in,--cnx_master_in(c_SLAVE_DRAM),
- gen_cores : for k in 1 to 3 generate
-
- urv_core : entity work.urv_core_DTMR
-
- generic map(
- g_m2s090 => g_m2s090,
- g_dram_data_width => g_dram_data_width,
- g_dram_addr_width => g_dram_addr_width
- )
- port map (
- clk_i => clk_i,
- rst_i => rst_cpu or rst_cpu_sv (k), --(1)rst_cpu_sv(k), --rst_cpu,
-
- -- to the IRAM primitive
- d_iram_i => d_cpu_iram,
- q_iram_o => q_cpu_iram(k),
- a_iram_o => a_cpu_iram(k),
- we_iram_o => we_cpu_iram(k),
- re_iram_o => re_cpu_iram(k),
- valid_iram_i => valid_cpu_iram,
- lock_iram_req_o => lock_cpu_iram_req(k),
- lock_iram_grant_i => lock_cpu_iram_grant,
-
-
-
- -- to the DRAM primitive
- d_dram_i => d_cpu_dram,
- q_dram_o => q_cpu_dram(k),
- a_dram_o => a_cpu_dram(k),
- we_dram_o => we_cpu_dram(k),
- re_dram_o => re_cpu_dram(k),
- valid_dram_i => valid_cpu_dram,
- lock_dram_req_o => lock_cpu_dram_req(k),
- lock_dram_grant_i => lock_cpu_dram_grant,
-
- iram_single_error_p_o => se_iram(k),
- iram_double_error_p_o => de_iram(k),
-
- dram_single_error_p_o => se_dram(k),
- dram_double_error_p_o => de_dram(k),
- irq_i => irq_eth,
- -- to the Wishbone xbar
- cpu_dwb_o => cpu_dwb_out(k),
- cpu_dwb_i => cpu_dwb_in
-
- );
-
- supervisor : entity work.urv_supervisor
- generic map (
- g_cpu_id => k)
- port map(
- clk_i => clk_i,
- rst_i => rst_i,
-
- slave_i => cnx_master_out(c_SLAVE_SUPERVISOR),
- slave_o => supervisor_wb_out (k),
-
- pc_i => a_cpu_iram,
- stall_i => ('0', '0', '0'),
- boot_done_o => boot_done_sv (k),
- rst_cpu_o => rst_cpu_sv (k),
- reboot_o => reboot_sv (k)
-
- );
-
-
- end generate;
-
- wb_cpu_voter : entity work.wb_master_voter
- port map (
- m_wb_i => cpu_dwb_out,
- m_wb_o => cpu_dwb_out_voted
- );
-
- wb_supervisor_voter : entity work.wb_slave_voter
- port map (
- s_wb_i => supervisor_wb_out,
- s_wb_o => cnx_master_in(c_SLAVE_SUPERVISOR)
- );
-
- reboot_sv_voted <= f_voter_stdlogic (reboot_sv(1), reboot_sv(2), reboot_sv(3));
- boot_done <= f_voter_stdlogic (boot_done_sv (1), boot_done_sv(2),boot_done_sv(3));
-
- se_iram_voted <= f_voter_stdlogic(se_iram (1), se_iram(2), se_iram(3));
- se_dram_voted <= f_voter_stdlogic(se_dram (1), se_dram(2), se_dram(3));
- de_iram_voted <= f_voter_stdlogic(de_iram (1), de_iram(2), de_iram(3));
- de_dram_voted <= f_voter_stdlogic(de_dram (1), de_dram(2), de_dram(3));
+ -- ram interface
+ d_ram_i => d_wb_dram,
+ q_ram_o => q_wb_dram,
+ a_ram_o => a_wb_dram,
+ we_ram_o => we_wb_dram,
+ re_ram_o => re_wb_dram,
+ valid_ram_i => valid_wb_dram,
+ lock_req_o => lock_wb_dram_req,
+ lock_grant_i => lock_wb_dram_grant,
+ single_error_p_o => se_dram_scrubber,
+ double_error_p_o => de_dram_scrubber
+ );
-
- envm_wb : entity work.wb_envm
- port map (
- clk_i => clk_i,
- rst_i => rst_i,
- rst_cpu_o => rst_cpu_boot,
-
- apb_psel_o => apb_psel_o,
- apb_pwr_o => apb_pwr_o,
- apb_pen_o => apb_pen_o,
- apb_paddr_o => apb_paddr_o,
- apb_pwdat_o => apb_pwdat_o,
- apb_prdat_i => apb_prdat_i,
- apb_pready_i => apb_pready_i,
-
- master_i => envm_wb_iram_out,
- master_o => envm_wb_iram_in,
-
- slave_i => cnx_master_out (c_SLAVE_ENVM),
- slave_o => cnx_master_in (c_SLAVE_ENVM)
- );
-
-
-
-
- xwb_iram : xwb_ram_adapter
- generic map (
- g_addr_width => 16,
- g_data_width => 39,
- g_is_iram => true,
- g_is_dram => false
- )
- port map(
- clk_i => clk_i,
- rst_i => rst_i,
- boot_done_i => boot_done,
-
- -- Wishbone
- slave_i => envm_wb_iram_in,
- slave_o => envm_wb_iram_out,
-
- -- ram interface
- d_ram_i => d_wb_iram,
- q_ram_o => q_wb_iram,
- a_ram_o => a_wb_iram,
- we_ram_o => we_wb_iram,
- re_ram_o => re_wb_iram,
- valid_ram_i => valid_wb_iram,
- lock_req_o => lock_wb_iram_req,
- lock_grant_i => lock_wb_iram_grant,
- single_error_p_o => se_iram_scrubber,
- double_error_p_o => de_iram_scrubber
- );
-
-
+ U_Local_Interconnect : entity work.xwb_crossbar
+ generic map (
+ g_NUM_MASTERS => 1,
+ g_NUM_SLAVES => c_SLAVE_NUM,
+ g_REGISTERED => true,
+ g_ADDRESS => c_CNX_ADDRESS,
+ g_MASK => c_CNX_MASK)
+ port map (
+ clk_sys_i => clk_i,
+ rst_n_i => not rst_i,
+ slave_i => cnx_slave_in, --cpu_dwb_out,
+ slave_o => cnx_slave_out, --cpu_dwb_in,
+ master_i => cnx_master_in,
+ master_o => cnx_master_out);
+
+ cnx_slave_in(0) <= cpu_dwb_out_voted;
+ cpu_dwb_in <= cnx_slave_out(0);
+
+
+ mac : entity work.ueth
+ port map (
+
+ clk_i => clk_i,
+ rst_i => rst_i,
+
+ --TX
+ phy0_tx_clk_i => eth_tx_clk_i,
+ phy0_txd_o => eth_txd_o,
+ phy0_txen_o => eth_txen_o,
+ -- phy0_txerr_o => eth_txerr_o,
+
+ --RX
+ phy0_rx_clk_i => eth_rx_clk_i,
+ phy0_rxd_i => eth_rxd_i,
+ phy0_rxdv_i => eth_rxdv_i,
+ phy0_rxerr_i => eth_rxerr_i,
+
+ --TX
+ phy1_tx_clk_i => eth_tx_clk_i,
+ phy1_txd_o => open,
+ phy1_txen_o => open,
+ -- phy1_txerr_o => open,
+
+ --RX
+ phy1_rx_clk_i => eth_rx_clk_i,
+ phy1_rxd_i => (others =>'0'),
+ phy1_rxdv_i => '0',
+ phy1_rxerr_i => '0',
+
+
+ --MIIM
+ phy_mdc_o => eth_mdc_o,
+ phy_md_i => eth_md_i,
+ phy_md_o => eth_md_o,
+ phy_oe_o => eth_oe_o,
+
+ phy_rst_o => eth_rst_o,
+ irq_o => irq_eth,
+ -- Wishbone regs
+ slave_i => cnx_master_out(c_SLAVE_ETH),
+ slave_o => cnx_master_in(c_SLAVE_ETH),
+
+ -- Wishbone DMA
+ master_i => eth_m_wb_in,
+ master_o => eth_m_wb_out
+ );
+ U_seu_regs : entity work.xwb_seu_regs
+ port map(
+ clk_sys_i => clk_i,
+ rst_i => rst_i,
+ -- Wishbone
+ slave_i => cnx_master_out(c_SLAVE_SEC),
+ slave_o => cnx_master_in(c_SLAVE_SEC),
+ iram_seu_regs_see_se_i => se_iram_counts,
+ iram_seu_regs_see_de_i => de_iram_counts,
+ dram_seu_regs_see_se_i => se_dram_counts,
+ dram_seu_regs_see_de_i => de_dram_counts
+ );
+ inst_seu_counters: entity work.seu_counters
+ port map(
+ clk_i => clk_i,
+ rst_i => rst_i,
- xwb_dram : xwb_ram_adapter
- generic map (
- g_addr_width => g_dram_addr_width,
- g_data_width => g_dram_data_width,
- g_is_iram => false,
- g_is_dram => true
- )
- port map(
- clk_i => clk_i,
- rst_i => rst_i,
- boot_done_i => boot_done,
-
- -- Wishbone
- slave_i => eth_m_wb_out, --cnx_master_out(c_SLAVE_DRAM),
- slave_o => eth_m_wb_in,--cnx_master_in(c_SLAVE_DRAM),
-
- -- ram interface
- d_ram_i => d_wb_dram,
- q_ram_o => q_wb_dram,
- a_ram_o => a_wb_dram,
- we_ram_o => we_wb_dram,
- re_ram_o => re_wb_dram,
- valid_ram_i => valid_wb_dram,
- lock_req_o => lock_wb_dram_req,
- lock_grant_i => lock_wb_dram_grant,
- single_error_p_o => se_dram_scrubber,
- double_error_p_o => de_dram_scrubber
- );
-
-
-
-
-
- U_Local_Interconnect : xwb_crossbar
- generic map (
- g_NUM_MASTERS => 1,
- g_NUM_SLAVES => c_SLAVE_NUM,
- g_REGISTERED => true,
- g_ADDRESS => c_CNX_ADDRESS,
- g_MASK => c_CNX_MASK)
- port map (
- clk_sys_i => clk_i,
- rst_n_i => not rst_i,
- slave_i => cnx_slave_in, --cpu_dwb_out,
- slave_o => cnx_slave_out, --cpu_dwb_in,
- master_i => cnx_master_in,
- master_o => cnx_master_out);
-
- cnx_slave_in(0) <= cpu_dwb_out_voted;
- cpu_dwb_in <= cnx_slave_out(0);
-
-
-mac : entity work.ueth
-port map (
-
- clk_i => clk_i,
- rst_i => rst_i,
-
- --TX
- phy0_tx_clk_i => eth_tx_clk_i,
- phy0_txd_o => eth_txd_o,
- phy0_txen_o => eth_txen_o,
- -- phy0_txerr_o => eth_txerr_o,
-
- --RX
- phy0_rx_clk_i => eth_rx_clk_i,
- phy0_rxd_i => eth_rxd_i,
- phy0_rxdv_i => eth_rxdv_i,
- phy0_rxerr_i => eth_rxerr_i,
-
- --TX
- phy1_tx_clk_i => eth_tx_clk_i,
- phy1_txd_o => open,
- phy1_txen_o => open,
- -- phy1_txerr_o => open,
-
- --RX
- phy1_rx_clk_i => eth_rx_clk_i,
- phy1_rxd_i => (others =>'0'),
- phy1_rxdv_i => '0',
- phy1_rxerr_i => '0',
-
-
- --MIIM
- phy_mdc_o => eth_mdc_o,
- phy_md_i => eth_md_i,
- phy_md_o => eth_md_o,
- phy_oe_o => eth_oe_o,
-
- phy_rst_o => eth_rst_o,
- irq_o => irq_eth,
- -- Wishbone regs
- slave_i => cnx_master_out(c_SLAVE_ETH),
- slave_o => cnx_master_in(c_SLAVE_ETH),
-
- -- Wishbone DMA
- master_i => eth_m_wb_in,
- master_o => eth_m_wb_out
-
-);
-
-
-
-
-
- U_seu_regs : xwb_seu_regs
- port map(
- clk_sys_i => clk_i,
- rst_i => rst_i,
-
- -- Wishbone
- slave_i => cnx_master_out(c_SLAVE_SEC),
- slave_o => cnx_master_in(c_SLAVE_SEC),
-
- iram_seu_regs_see_se_i => se_iram_counts,
- iram_seu_regs_see_de_i => de_iram_counts,
- dram_seu_regs_see_se_i => se_dram_counts,
- dram_seu_regs_see_de_i => de_dram_counts
- );
-
- inst_seu_counters: seu_counters
-
- port map(
- clk_i => clk_i,
- rst_i => rst_i,
-
- event_se_iram => se_iram_voted or se_iram_scrubber,
- event_de_iram => de_iram_voted or de_iram_scrubber,
-
- event_se_dram => se_dram_voted or se_dram_scrubber,
- event_de_dram => de_dram_voted or de_dram_scrubber,
-
-
- se_iram_o => se_iram_counts,
- de_iram_o => de_iram_counts,
- se_dram_o => se_dram_counts,
- de_dram_o => de_dram_counts
-
-
-
- );
+ event_se_iram => se_iram_voted or se_iram_scrubber,
+ event_de_iram => de_iram_voted or de_iram_scrubber,
+ event_se_dram => se_dram_voted or se_dram_scrubber,
+ event_de_dram => de_dram_voted or de_dram_scrubber,
+ se_iram_o => se_iram_counts,
+ de_iram_o => de_iram_counts,
+ se_dram_o => se_dram_counts,
+ de_dram_o => de_dram_counts
+ );
- U_wd_regs : xwb_wd_reg
- port map(
- clk_sys_i => clk_i,
- rst_i => rst_i,
- -- Wishbone
- slave_i => cnx_master_out(c_SLAVE_WD),
- slave_o => cnx_master_in(c_SLAVE_WD),
+ U_wd_regs : entity work.xwb_wd_reg
+ port map(
+ clk_sys_i => clk_i,
+ rst_i => rst_i,
- wd_reg_heartbeat_o => wd_heartbeat
- );
+ -- Wishbone
+ slave_i => cnx_master_out(c_SLAVE_WD),
+ slave_o => cnx_master_in(c_SLAVE_WD),
+ wd_reg_heartbeat_o => wd_heartbeat
+ );
+ wd : process (clk_i)
+ begin
+ if rst_i = '1' then
+ rst_cpu_wd <= '0';
+ wd_counter <= (others => '0');
+ elsif rising_edge(clk_i) then
+ rst_cpu_wd <= '0';
+
+ wd_counter <= wd_counter + 1;
+
+ if (wd_heartbeat = '1') then
+ wd_counter <= (others => '0');
+ end if;
+ if (wd_counter = (wd_counter'range => '1')) then
+ rst_cpu_wd <= '1';
+ end if;
+ end if;
+ end process;
+
+ U_UART_regs : entity work.xwb_uart
+ port map (
+ clk_sys_i => clk_i,
+ rst_i => rst_i,
+ slave_i => cnx_master_out(c_SLAVE_UART),
+ slave_o => cnx_master_in(c_SLAVE_UART),
+ uart_sr_tx_busy_i => uart_ready_wb,
+ uart_sr_tx_send_o => tx_req_wb,
+ uart_tdr_tx_data_o => uart_tx_data_wb
+ );
+ uart_tx : uart
+ port map (
+ reset_i => devrst_i,
+ clk_i => clk_i,
+ txd_o => uart_tx_o,
+ tx_data_i => uart_tx_data,
+ tx_wdone_o => dm_uart_write_done,
+ tx_ready_o => uart_ready,
+ tx_req_i => tx_req);
- wd : process (clk_i)
- begin
- if rst_i = '1' then
- rst_cpu_wd <= '0';
- wd_counter <= (others => '0');
- elsif rising_edge(clk_i) then
- rst_cpu_wd <= '0';
-
- wd_counter <= wd_counter + 1;
-
- if (wd_heartbeat = '1') then
- wd_counter <= (others => '0');
- end if;
- if (wd_counter = (wd_counter'range => '1')) then
- rst_cpu_wd <= '1';
- end if;
- end if;
- end process;
+ process (clk_i)
+ begin
+ if devrst_i = '1' then
+ first_time <= '1';
+ uart_ready_wb <= '0';
+ fsm_uart <= idle;
+ tx_req <= '0';
+ first_de <= '1';
+ elsif rising_edge (clk_i) then
+ if (rst_i) then
+ first_de <= '1';
+
+ end if;
+ case (fsm_uart) is
+ when idle =>
+ uart_ready_wb <= uart_ready;
+ tx_req <= tx_req_wb;
+ uart_tx_data <= uart_tx_data_wb;
+
+ if (first_de and (de_iram_voted or de_dram_voted or de_iram_scrubber or de_iram_scrubber)) then
+ fsm_uart <= wait_write;
+ uart_tx_data <= x"23"; -- 23#
+ tx_req <= '1';
+ first_de <= '0';
+ end if;
+ if (reboot_sv_voted = '1') then
+ fsm_uart <= wait_write;
+ uart_tx_data <= x"24"; -- $
+ tx_req <= '1';
+ end if;
+ if (rst_i = '1') then
+ -- fsm_uart <= wait_write;
+ -- uart_tx_data <= x"25"; -- %
+ -- tx_req <= '1';
+ end if;
+ if (first_time = '1') then
+ first_time <= '0';
+ uart_tx_data <= x"40"; -- @
+ tx_req <= '1';
+ fsm_uart <= wait_write;
+ end if;
+
+
+ when wait_write =>
+ if (uart_ready = '1') then
+ tx_req <= '1';
+ uart_tx_data <= x"0A";
+ fsm_uart <= wait_lf;
+ end if;
+
+ when wait_lf =>
+ if (uart_ready = '1') then
+ tx_req <= '0';
+ fsm_uart <= idle;
+ end if;
+ when others => fsm_uart <= idle;
+ end case;
+ end if;
+ end process;
+
+ -- synthesis translate_off
+ process
+ begin
+ loop
+ wait until rising_edge(clk_i);
+ if (tx_req = '1') then
+ --std.textio.write(std.textio.output, to_string(uart_tx_data));
-
- U_UART_regs : xwb_uart
-
- port map (
- clk_sys_i => clk_i,
- rst_i => rst_i,
- slave_i => cnx_master_out(c_SLAVE_UART),
- slave_o => cnx_master_in(c_SLAVE_UART),
- uart_sr_tx_busy_i => uart_ready_wb,
- uart_sr_tx_send_o => tx_req_wb,
- uart_tdr_tx_data_o => uart_tx_data_wb
- );
-
- uart_tx : uart
- port map (
- reset_i => devrst_i,
- clk_i => clk_i,
- txd_o => uart_tx_o,
- tx_data_i => uart_tx_data,
- tx_wdone_o => dm_uart_write_done,
- tx_ready_o => uart_ready,
- tx_req_i => tx_req);
-
-
- process (clk_i)
- begin
- if devrst_i = '1' then
- first_time <= '1';
- uart_ready_wb <= '0';
- fsm_uart <= idle;
- tx_req <= '0';
- first_de <= '1';
- elsif rising_edge (clk_i) then
- if (rst_i) then
- first_de <= '1';
-
- end if;
- case (fsm_uart) is
- when idle =>
- uart_ready_wb <= uart_ready;
- tx_req <= tx_req_wb;
- uart_tx_data <= uart_tx_data_wb;
-
- if (first_de and (de_iram_voted or de_dram_voted or de_iram_scrubber or de_iram_scrubber)) then
- fsm_uart <= wait_write;
- uart_tx_data <= x"23"; -- 23#
- tx_req <= '1';
- first_de <= '0';
- end if;
- if (reboot_sv_voted = '1') then
- fsm_uart <= wait_write;
- uart_tx_data <= x"24"; -- $
- tx_req <= '1';
- end if;
- if (rst_i = '1') then
- -- fsm_uart <= wait_write;
- -- uart_tx_data <= x"25"; -- %
- -- tx_req <= '1';
- end if;
- if (first_time = '1') then
- first_time <= '0';
- uart_tx_data <= x"40"; -- @
- tx_req <= '1';
- fsm_uart <= wait_write;
- end if;
-
-
- when wait_write =>
- if (uart_ready = '1') then
- tx_req <= '1';
- uart_tx_data <= x"0A";
- fsm_uart <= wait_lf;
- end if;
-
- when wait_lf =>
- if (uart_ready = '1') then
- tx_req <= '0';
- fsm_uart <= idle;
- end if;
- when others => fsm_uart <= idle;
- end case;
- end if;
- end process;
-
-
-
-
- -- synthesis translate_off
-
-
- process
- begin
- loop
- wait until rising_edge(clk_i);
- if (tx_req = '1') then
- --std.textio.write(std.textio.output, to_string(uart_tx_data));
-
-
- WRITE (output, (1 => character'val (to_integer(unsigned(uart_tx_data)))));
- end if;
-
- end loop;
- end process;
- -- synthesis translate_on
-
-
-
-
+ WRITE (output, (1 => character'val (to_integer(unsigned(uart_tx_data)))));
+ end if;
- end architecture;
\ No newline at end of file
+ end loop;
+ end process;
+ -- synthesis translate_on
+end architecture;
diff --git a/hdl/urv_supervisor.vhd b/hdl/urv_supervisor.vhd
index 4c5f0a0a0298237754007fc191e634a52020d2bd..3231790ae0dacdb4310e380e194a14269b779d51 100644
--- a/hdl/urv_supervisor.vhd
+++ b/hdl/urv_supervisor.vhd
@@ -13,7 +13,6 @@ use work.wishbone_pkg.all;
--use smartfusion2.all;
use work.voter.all;
-use work.wb_voter_pkg.all;
@@ -48,7 +47,6 @@ architecture rtl of urv_supervisor is
signal state_cpu_1, state_cpu_2, state_cpu_3 : std_logic;
signal state_cpu : std_logic_vector (3 downto 1);
- signal release_cpu : std_logic;
type fsm_states is (boot, boot_cnt, voting, lock_step, fatal, fatal_2);
constant recovery_dunc : std_logic_vector (15 downto 0) := x"0000";
diff --git a/hdl/wb_envm.vhd b/hdl/wb_envm.vhd
index 0cd6b191def46dcff961c53f5d7d3d575a108def..fcf68683cc4c0592c7635e1260a110beb7817c4f 100644
--- a/hdl/wb_envm.vhd
+++ b/hdl/wb_envm.vhd
@@ -7,19 +7,18 @@ use work.wishbone_pkg.all;
entity wb_envm is
-
port (
- clk_i : in std_logic;
- rst_i : in std_logic;
- rst_cpu_o : out std_logic;
+ clk_i : in std_logic;
+ rst_i : in std_logic;
+ rst_cpu_o : out std_logic;
- apb_psel_o : out std_logic;
- apb_pwr_o : out std_logic;
- apb_pen_o : out std_logic;
- apb_paddr_o : out std_logic_vector(31 downto 0);
- apb_pwdat_o : out std_logic_vector(31 downto 0);
- apb_prdat_i : in std_logic_vector(31 downto 0);
- apb_pready_i : in std_logic; --
+ apb_psel_o : out std_logic;
+ apb_pwr_o : out std_logic;
+ apb_pen_o : out std_logic;
+ apb_paddr_o : out std_logic_vector(31 downto 0);
+ apb_pwdat_o : out std_logic_vector(31 downto 0);
+ apb_prdat_i : in std_logic_vector(31 downto 0);
+ apb_pready_i : in std_logic; --
-- to the Wishbone xbar
master_i : in t_wishbone_master_in;
@@ -27,266 +26,269 @@ entity wb_envm is
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out
-
);
end entity wb_envm;
architecture rtl of wb_envm is
+ constant bootloader_addr : std_logic_vector (31 downto 0) := x"60012000"; -- (bits from 11 to 0 must be 0)
+ constant bootloader_size : integer := 256; -- words (max 256)
-constant bootloader_addr : std_logic_vector (31 downto 0) := x"60012000"; -- (bits from 11 to 0 must be 0)
-constant bootloader_size : integer := 256; -- words (max 256)
+ type fsm_apb_states is (idle, setup, accessing);
+ type fsm_envm_states is (idle, check_status, poll_bit, data);
+ type fsm_bootstrap_states is (cold_start, poll_bit, fetch_word, wait_apb, wait_wb, checksum, done);
+ type fsm_wb_master_states is (idle, wait_ack);
-type fsm_apb_states is (idle, setup, accessing);
-type fsm_envm_states is (idle, check_status, poll_bit, data);
-type fsm_bootstrap_states is (cold_start, poll_bit, fetch_word, wait_apb, wait_wb, checksum, done);
-type fsm_wb_master_states is (idle, wait_ack);
+ signal apb_fsm : fsm_apb_states := idle;
+ signal envm_fsm : fsm_envm_states := idle;
+ signal bootstrap_fsm : fsm_bootstrap_states := cold_start;
+ signal wb_fsm : fsm_wb_master_states := idle;
-signal apb_fsm : fsm_apb_states := idle;
-signal envm_fsm : fsm_envm_states := idle;
-signal bootstrap_fsm : fsm_bootstrap_states := cold_start;
-signal wb_fsm : fsm_wb_master_states := idle;
+ signal apb_addr, apb_addr_boot, apb_addr_wb, envm_addr, envm_data, apb_data, wb_data, wb_data_reg : std_logic_vector (31 downto 0);
-signal apb_addr, apb_addr_boot, apb_addr_wb, envm_addr, envm_data, apb_data, wb_data, wb_data_reg : std_logic_vector (31 downto 0);
-
-signal envm_read_req_p, apb_read_req, apb_read_req_boot, apb_read_req_wb, apb_read_ack : std_logic;
-signal wb_write_req, wb_write_req_boot, wb_write_req_wb, wb_write_ack : std_logic;
-signal wb_addr, wb_addr_boot, wb_addr_wb : std_logic_vector (16 downto 0);
+ signal envm_read_req_p, apb_read_req, apb_read_req_boot, apb_read_req_wb, apb_read_ack:std_logic;
+ signal wb_write_req, wb_write_req_boot, wb_write_req_wb, wb_write_ack : std_logic;
+ signal wb_addr, wb_addr_boot, wb_addr_wb : std_logic_vector (16 downto 0);
signal counter : unsigned (9 downto 0);
-attribute syn_encoding : string;
-attribute syn_encoding of bootstrap_fsm, wb_fsm, apb_fsm, envm_fsm : signal is "safe,onehot";
+ attribute syn_encoding : string;
+ attribute syn_encoding of bootstrap_fsm, wb_fsm, apb_fsm, envm_fsm : signal is "safe,onehot";
-attribute syn_radhardlevel : string;
-attribute syn_radhardlevel of rtl : architecture is "tmr";
+ attribute syn_radhardlevel : string;
+ attribute syn_radhardlevel of rtl : architecture is "tmr";
begin
-apb_addr <= apb_addr_boot when (rst_cpu_o = '1') else apb_addr_wb;
-apb_read_req <= apb_read_req_boot when (rst_cpu_o = '1') else apb_read_req_wb;
+ apb_addr <= apb_addr_boot when (rst_cpu_o = '1') else apb_addr_wb;
+ apb_read_req <= apb_read_req_boot when (rst_cpu_o = '1') else apb_read_req_wb;
-process (clk_i)
-begin
-if rising_edge (clk_i) then
- if rst_i = '1' then
- rst_cpu_o <= '1';
- bootstrap_fsm <= cold_start;
- wb_write_req_boot <= '0';
- else
- case (bootstrap_fsm) is
- when cold_start =>
- rst_cpu_o <= '1';
- bootstrap_fsm <= poll_bit;
- counter <= (others => '0');
- wb_write_req_boot <= '0';
- apb_addr_boot <= x"60080120";
- apb_read_req_boot <= '1';
- when poll_bit =>
- apb_read_req_boot <= '0';
- if (apb_read_ack = '1') then
- if (apb_data (0) = '1') then -- busy bit
- bootstrap_fsm <= fetch_word;
- else
- apb_read_req_boot <= '1';
- end if;
- end if;
- when fetch_word =>
- apb_read_req_boot <= '1';
- apb_addr_boot (31 downto 12) <= bootloader_addr (31 downto 12);
- apb_addr_boot (11 downto 2) <= std_logic_vector(counter);
- apb_addr_boot (1 downto 0) <= (others => '0');
- bootstrap_fsm <= wait_apb;
- when wait_apb =>
- apb_read_req_boot <= '0';
- if (apb_read_ack = '1') then
- bootstrap_fsm <= wait_wb;
- wb_write_req_boot <= '1';
- wb_addr_boot <= (others => '0');
- wb_addr_boot (11 downto 2) <= std_logic_vector(counter);
- end if;
- when wait_wb =>
- wb_write_req_boot <= '0';
- if (wb_write_ack = '1') then
- if (counter >= to_unsigned(bootloader_size-4, counter'length)) then
- bootstrap_fsm <= checksum;
- else
- bootstrap_fsm <= fetch_word;
- counter <= counter + 1;
- end if;
- end if;
- when checksum =>
- -- to be done
- bootstrap_fsm <= done;
- when done =>
- rst_cpu_o <= '0';
- when others =>
- bootstrap_fsm <= done;
- end case;
- end if;
-end if;
-end process;
+ -- Start FSM: copy from NVM to RAM.
+ process (clk_i)
+ begin
+ if rising_edge (clk_i) then
+ if rst_i = '1' then
+ rst_cpu_o <= '1';
+ bootstrap_fsm <= cold_start;
+ wb_write_req_boot <= '0';
+ else
+ case (bootstrap_fsm) is
+ when cold_start =>
+ -- Init
+ rst_cpu_o <= '1';
+ bootstrap_fsm <= poll_bit;
+ counter <= (others => '0');
+ wb_write_req_boot <= '0';
+ apb_addr_boot <= x"60080120";
+ apb_read_req_boot <= '1';
+ when poll_bit =>
+ -- Wait NVM ready
+ apb_read_req_boot <= '0';
+ if (apb_read_ack = '1') then
+ if (apb_data (0) = '1') then -- busy bit
+ bootstrap_fsm <= fetch_word;
+ else
+ apb_read_req_boot <= '1';
+ end if;
+ end if;
+ when fetch_word =>
+ -- Read a word from the NVM
+ apb_read_req_boot <= '1';
+ apb_addr_boot (31 downto 12) <= bootloader_addr (31 downto 12);
+ apb_addr_boot (11 downto 2) <= std_logic_vector(counter);
+ apb_addr_boot (1 downto 0) <= (others => '0');
+ bootstrap_fsm <= wait_apb;
+ when wait_apb =>
+ -- Wait NVM word
+ apb_read_req_boot <= '0';
+ if (apb_read_ack = '1') then
+ bootstrap_fsm <= wait_wb;
+ wb_write_req_boot <= '1';
+ wb_addr_boot <= (others => '0');
+ wb_addr_boot (11 downto 2) <= std_logic_vector(counter);
+ end if;
+ when wait_wb =>
+ -- Write to RAM
+ wb_write_req_boot <= '0';
+ if (wb_write_ack = '1') then
+ if (counter >= to_unsigned(bootloader_size-4, counter'length)) then
+ bootstrap_fsm <= checksum;
+ else
+ bootstrap_fsm <= fetch_word;
+ counter <= counter + 1;
+ end if;
+ end if;
+ when checksum =>
+ -- to be done
+ bootstrap_fsm <= done;
+ when done =>
+ rst_cpu_o <= '0';
+ when others =>
+ bootstrap_fsm <= done;
+ end case;
+ end if;
+ end if;
+ end process;
-wb_addr <= wb_addr_boot when (rst_cpu_o = '1') else wb_addr_wb;
-wb_write_req <= wb_write_req_boot when (rst_cpu_o = '1') else wb_write_req_wb;
-wb_data <= apb_data when (rst_cpu_o = '1') else wb_data_reg;
+ wb_addr <= wb_addr_boot when (rst_cpu_o = '1') else wb_addr_wb;
+ wb_write_req <= wb_write_req_boot when (rst_cpu_o = '1') else wb_write_req_wb;
+ wb_data <= apb_data when (rst_cpu_o = '1') else wb_data_reg;
-process (clk_i)
-begin
-if rising_edge (clk_i) then
- if rst_i = '1' then
- wb_fsm <= idle;
- master_o.cyc <= '0';
- master_o.stb <= '0';
- master_o.adr <= (others => '0');
- else
- case (wb_fsm) is
- when idle =>
- master_o.cyc <= '0';
- master_o.stb <= '0';
- wb_write_ack <= '0';
- if (wb_write_req = '1' and wb_write_ack = '0') then
- wb_fsm <= wait_ack;
- master_o.cyc <= '1';
- master_o.stb <= '1';
- master_o.we <= '1';
- master_o.sel <= "1111";
- master_o.adr (wb_addr'left downto 0) <= wb_addr;
- master_o.dat <= wb_data;
- end if;
- when wait_ack =>
- if (master_i.ack = '1') then
- master_o.cyc <= '0';
- master_o.stb <= '0';
- master_o.we <= '0';
- wb_write_ack <= '1';
- wb_fsm <= idle;
- end if;
- when others =>
- wb_fsm <= idle;
- end case;
-
-
- end if;
-end if;
-end process;
+ -- WB fsm
+ process (clk_i)
+ begin
+ if rising_edge (clk_i) then
+ if rst_i = '1' then
+ wb_fsm <= idle;
+ master_o.cyc <= '0';
+ master_o.stb <= '0';
+ master_o.adr <= (others => '0');
+ else
+ case (wb_fsm) is
+ when idle =>
+ master_o.cyc <= '0';
+ master_o.stb <= '0';
+ wb_write_ack <= '0';
+ if (wb_write_req = '1' and wb_write_ack = '0') then
+ wb_fsm <= wait_ack;
+ master_o.cyc <= '1';
+ master_o.stb <= '1';
+ master_o.we <= '1';
+ master_o.sel <= "1111";
+ master_o.adr (wb_addr'left downto 0) <= wb_addr;
+ master_o.dat <= wb_data;
+ end if;
+ when wait_ack =>
+ if (master_i.ack = '1') then
+ master_o.cyc <= '0';
+ master_o.stb <= '0';
+ master_o.we <= '0';
+ wb_write_ack <= '1';
+ wb_fsm <= idle;
+ end if;
+ when others =>
+ wb_fsm <= idle;
+ end case;
+ end if;
+ end if;
+ end process;
-process (clk_i)
-begin
-if rising_edge(clk_i) then
- if rst_i = '1' then
- apb_fsm <= idle;
- apb_psel_o <= '0';
- apb_pen_o <= '0';
- apb_pwr_o <= '0';
+ -- APB fsm
+ process (clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if rst_i = '1' then
+ apb_fsm <= idle;
+ apb_psel_o <= '0';
+ apb_pen_o <= '0';
+ apb_pwr_o <= '0';
apb_read_ack <= '0';
- else
- case (apb_fsm) is
- when idle =>
- apb_read_ack <= '0';
- if (apb_read_req = '1' and apb_read_ack = '0') then
- apb_fsm <= setup;
- apb_psel_o <= '1';
- apb_paddr_o <= apb_addr;
- end if;
- when setup =>
- apb_pen_o <= '1';
- apb_fsm <= accessing;
- when accessing =>
- if (apb_pready_i = '1') then
- apb_data <= apb_prdat_i;
- apb_fsm <= idle;
- apb_pen_o <= '0';
- apb_psel_o <= '0';
- apb_read_ack <= '1';
- end if;
- when others =>
- apb_fsm <= idle;
- end case;
- end if;
-end if;
-end process;
-
-process (clk_i)
-begin
-if rising_edge (clk_i) then
- if rst_i = '1' then
- envm_fsm <= idle;
- apb_read_req_wb <= '0';
- else
- case (envm_fsm) is
- when idle =>
- if (envm_read_req_p = '1') then
- envm_fsm <= check_status;
- end if;
- when check_status =>
- if (apb_fsm = idle) then
- apb_addr_wb <= x"60080120";
- apb_read_req_wb <= '1';
- envm_fsm <= poll_bit;
- end if;
- when poll_bit =>
- apb_read_req_wb <= '0';
- if (apb_read_ack = '1') then
- if (apb_data (0) = '1') then -- busy bit
- envm_fsm <= data;
- apb_addr_wb <= envm_addr;
- apb_read_req_wb <= '1';
- else
- apb_read_req_wb <= '1'; -- retry
- end if;
- end if;
- when data =>
- apb_read_req_wb <= '0';
- if (apb_read_ack = '1') then
- envm_data <= apb_data;
- envm_fsm <= idle;
- end if;
- when others =>
- envm_fsm <= idle;
- end case;
-end if;
-end if;
-end process;
-
-process (clk_i)
-begin
-if rising_edge (clk_i) then
- envm_read_req_p <= '0';
- wb_write_req_wb <= '0';
- slave_o.ack <= '0';
- if (slave_i.stb = '1' and slave_i.cyc = '1' and slave_o.ack = '0') then
- slave_o.ack <= '1';
- if (slave_i.adr(4 downto 2) = "000") then
- slave_o.dat (31 downto 1) <= (others => '0');
- slave_o.dat (0) <= '1' when envm_fsm /= idle else '0';
- elsif (slave_i.adr (4 downto 2) = "001") then
- slave_o.dat <= slave_i.dat;
- if (slave_i.we = '1') then
- envm_addr <= slave_i.dat;
- envm_read_req_p <= '1';
- end if;
- elsif (slave_i.adr (4 downto 2) = "010") then
- slave_o.dat <= envm_data;
- elsif (slave_i.adr (4 downto 2) = "100") then
- slave_o.dat <= slave_i.dat;
- if (slave_i.we = '1') then
- wb_addr_wb <= slave_i.dat (wb_addr_wb'left downto 0);
- end if;
- elsif (slave_i.adr (4 downto 2) = "101") then
- slave_o.dat <= slave_i.dat;
- if (slave_i.we = '1') then
- wb_data_reg <= slave_i.dat;
- wb_write_req_wb <= '1';
- end if;
- end if;
- end if;
-end if;
-end process;
-
-
-
-
-
+ else
+ case (apb_fsm) is
+ when idle =>
+ apb_read_ack <= '0';
+ if (apb_read_req = '1' and apb_read_ack = '0') then
+ apb_fsm <= setup;
+ apb_psel_o <= '1';
+ apb_paddr_o <= apb_addr;
+ end if;
+ when setup =>
+ apb_pen_o <= '1';
+ apb_fsm <= accessing;
+ when accessing =>
+ if (apb_pready_i = '1') then
+ apb_data <= apb_prdat_i;
+ apb_fsm <= idle;
+ apb_pen_o <= '0';
+ apb_psel_o <= '0';
+ apb_read_ack <= '1';
+ end if;
+ when others =>
+ apb_fsm <= idle;
+ end case;
+ end if;
+ end if;
+ end process;
+ process (clk_i)
+ begin
+ if rising_edge (clk_i) then
+ if rst_i = '1' then
+ envm_fsm <= idle;
+ apb_read_req_wb <= '0';
+ else
+ case (envm_fsm) is
+ when idle =>
+ if (envm_read_req_p = '1') then
+ envm_fsm <= check_status;
+ end if;
+ when check_status =>
+ if (apb_fsm = idle) then
+ apb_addr_wb <= x"60080120";
+ apb_read_req_wb <= '1';
+ envm_fsm <= poll_bit;
+ end if;
+ when poll_bit =>
+ apb_read_req_wb <= '0';
+ if (apb_read_ack = '1') then
+ if (apb_data (0) = '1') then -- busy bit
+ envm_fsm <= data;
+ apb_addr_wb <= envm_addr;
+ apb_read_req_wb <= '1';
+ else
+ apb_read_req_wb <= '1'; -- retry
+ end if;
+ end if;
+ when data =>
+ apb_read_req_wb <= '0';
+ if (apb_read_ack = '1') then
+ envm_data <= apb_data;
+ envm_fsm <= idle;
+ end if;
+ when others =>
+ envm_fsm <= idle;
+ end case;
+ end if;
+ end if;
+ end process;
+ -- WB slave: decode accesses
+ process (clk_i)
+ begin
+ if rising_edge (clk_i) then
+ envm_read_req_p <= '0';
+ wb_write_req_wb <= '0';
+ slave_o.ack <= '0';
+ if (slave_i.stb = '1' and slave_i.cyc = '1' and slave_o.ack = '0') then
+ slave_o.ack <= '1';
+ if (slave_i.adr(4 downto 2) = "000") then
+ -- Status
+ slave_o.dat (31 downto 1) <= (others => '0');
+ slave_o.dat (0) <= '1' when envm_fsm /= idle else '0';
+ elsif (slave_i.adr (4 downto 2) = "001") then
+ -- Start NVM read access
+ slave_o.dat <= slave_i.dat;
+ if (slave_i.we = '1') then
+ envm_addr <= slave_i.dat;
+ envm_read_req_p <= '1';
+ end if;
+ elsif (slave_i.adr (4 downto 2) = "010") then
+ -- NVM data
+ slave_o.dat <= envm_data;
+ elsif (slave_i.adr (4 downto 2) = "100") then
+ -- ???
+ slave_o.dat <= slave_i.dat;
+ if (slave_i.we = '1') then
+ wb_addr_wb <= slave_i.dat (wb_addr_wb'left downto 0);
+ end if;
+ elsif (slave_i.adr (4 downto 2) = "101") then
+ -- Start NVM write
+ slave_o.dat <= slave_i.dat;
+ if (slave_i.we = '1') then
+ wb_data_reg <= slave_i.dat;
+ wb_write_req_wb <= '1';
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
end architecture;
diff --git a/hdl/xwb_ram_adapter.vhdl b/hdl/xwb_ram_adapter.vhdl
index 2651baf73ed6275c5c204c0bea6360047f0b4f1b..e0df90c293dcdf455e1abaaca4b5c59b66c8b058 100644
--- a/hdl/xwb_ram_adapter.vhdl
+++ b/hdl/xwb_ram_adapter.vhdl
@@ -39,8 +39,8 @@ entity xwb_ram_adapter is
lock_req_o : out std_logic;
lock_grant_i : in std_logic;
- single_error_p_o : out std_logic;
- double_error_p_o : out std_logic
+ single_error_p_o : out std_logic;
+ double_error_p_o : out std_logic
);
end entity xwb_ram_adapter;
@@ -122,22 +122,18 @@ architecture rtl of xwb_ram_adapter is
read_fault_p_o : out std_logic;
write_fault_p_o : out std_logic
);
-
-
end component;
-
signal addr_scrubber : unsigned (15 downto 0);
signal timeout_wb : unsigned (3 downto 0);
- signal pwr, wr : std_logic;
type fsm_states is (idle, process_wb, scrubber_read);
signal fsm : fsm_states := idle;
- signal we, re : std_logic;
- signal addr : std_logic_vector (g_addr_width-1 downto 0);
- signal data_in, data_out : std_logic_vector (31 downto 0);
-signal bwe : std_logic_vector (3 downto 0);
+ signal we, re : std_logic;
+ signal addr : std_logic_vector (g_addr_width-1 downto 0);
+ signal data_in, data_out : std_logic_vector (31 downto 0);
+ signal bwe : std_logic_vector (3 downto 0);
attribute syn_radhardlevel : string;
attribute syn_radhardlevel of rtl : architecture is "tmr";
@@ -145,178 +141,165 @@ signal bwe : std_logic_vector (3 downto 0);
signal ack, done_r, done_w : std_logic;
- signal data_read : std_logic_vector (31 downto 0);
-
-attribute syn_encoding : string;
-attribute syn_encoding of fsm : signal is "safe,onehot";
-
+ attribute syn_encoding : string;
+ attribute syn_encoding of fsm : signal is "safe,onehot";
begin
-
-
slave_o.ack <= ack;
slave_o.stall <= (not ack) and slave_i.cyc and slave_i.stb;
slave_o.err <= '0';
- slave_o.int <= '0';
- slave_o.rty <= '0';
+ slave_o.rty <= '0';
+
process (clk_i)
begin
-
if rising_edge (clk_i) then
- if rst_i = '1' then
- fsm <= idle;
- addr_scrubber <= (x"0000");
- we <= '0';
- re <= '0';
- ack <= '0';
- timeout_wb <= (others => '0');
- addr <= (others => '0');
- else
-
- if (timeout_wb /= (timeout_wb'range => '1')) then
- timeout_wb <= timeout_wb + 1;
- end if;
+ if rst_i = '1' then
+ fsm <= idle;
+ addr_scrubber <= (x"0000");
+ we <= '0';
+ re <= '0';
+ ack <= '0';
+ timeout_wb <= (others => '0');
+ addr <= (others => '0');
+ else
+
+ if (timeout_wb /= (timeout_wb'range => '1')) then
+ timeout_wb <= timeout_wb + 1;
+ end if;
+
+ case (fsm) is
+ when idle =>
+ we <= '0';
+ re <= '0';
+ ack <= '0';
+ if (slave_i.stb = '1' and slave_i.cyc = '1' and ack = '0') then
+ fsm <= process_wb;
+ we <= slave_i.we;
- case (fsm) is
- when idle =>
- we <= '0';
- re <= '0';
- ack <= '0';
- if (slave_i.stb = '1' and slave_i.cyc = '1' and ack = '0') then
- fsm <= process_wb;
- we <= slave_i.we;
-
- if boot_done_i = '0' then
+ if boot_done_i = '0' then
we <= slave_i.we;
- elsif (g_is_iram and slave_i.we = '1') then
- we <= '0';
- fsm <= idle;
+ elsif (g_is_iram and slave_i.we = '1') then
report "Attempt to write iram in runtime" severity error;
- elsif (g_is_dram and slave_i.we = '1') then
- if (g_addr_width = 15 and slave_i.adr (g_addr_width-1 downto g_addr_width-3) /= "111") then
we <= '0';
fsm <= idle;
- report "Attempt to write lower part of dram in runtime" severity error;
+ elsif (g_is_dram and slave_i.we = '1') then
+ if (g_addr_width = 15 and slave_i.adr (g_addr_width-1 downto g_addr_width-3) /= "111") then
+ we <= '0';
+ fsm <= idle;
+ report "Attempt to write lower part of dram in runtime" severity error;
+ end if;
+
+ if (g_addr_width = 16 and slave_i.adr (g_addr_width-1 downto g_addr_width-4) /= "1111") then
+ we <= '0';
+ fsm <= idle;
+ report "Attempt to write lower part of dram in runtime" severity error;
+ end if;
end if;
-
- if (g_addr_width = 16 and slave_i.adr (g_addr_width-1 downto g_addr_width-4) /= "1111") then
- we <= '0';
- fsm <= idle;
- report "Attempt to write lower part of dram in runtime" severity error;
- end if;
- end if;
- bwe <= slave_i.sel;
- re <= not slave_i.we;
- data_in <= slave_i.dat;
- addr <= slave_i.adr (g_addr_width-1 downto 0);
- elsif (boot_done_i = '1' and timeout_wb = (timeout_wb'range => '1')) then
- fsm <= scrubber_read;
- re <= '1';
- addr <= std_logic_vector(addr_scrubber(g_addr_width-1 downto 0));
- end if;
- when process_wb =>
-
- slave_o.dat <= data_out;
-
- if ((re = '1' and done_r = '1') or (we = '1' and done_w = '1')) then
+ bwe <= slave_i.sel;
+ re <= not slave_i.we;
+ data_in <= slave_i.dat;
+ addr <= slave_i.adr (g_addr_width-1 downto 0);
+ elsif (boot_done_i = '1' and timeout_wb = (timeout_wb'range => '1')) then
+ fsm <= scrubber_read;
+ re <= '1';
+ addr <= std_logic_vector(addr_scrubber(g_addr_width-1 downto 0));
+ end if;
+
+ when process_wb =>
+ slave_o.dat <= data_out;
+ if ((re = '1' and done_r = '1') or (we = '1' and done_w = '1')) then
re <= '0';
we <= '0';
fsm <= idle;
ack <= '1';
timeout_wb <= (others => '0');
- end if;
-
-
- when scrubber_read =>
-
- if (done_r = '1') then
- re <= '0';
- fsm <= idle;
- addr_scrubber <= addr_scrubber+4;
- end if;
- when others =>
- fsm <= idle;
- end case;
+ end if;
+
+ when scrubber_read =>
+ if (done_r = '1') then
+ re <= '0';
+ fsm <= idle;
+ addr_scrubber <= addr_scrubber+4;
+ end if;
+ when others =>
+ fsm <= idle;
+ end case;
+ end if;
end if;
-end if;
end process;
-ecc_simple : if g_data_width = 39 generate
- ecc_circuitry : secded_ecc
- generic map (
- g_addr_width => g_addr_width
- )
- port map (
- clk_i => clk_i,
- rst_i => rst_i,
-
-
- d_i => data_in,
- a_i => addr,
- we_i => we and not done_w,
- bwe_i => bwe,
- re_i => re and not done_r,
-
- q_o => data_out,
- done_r_o => done_r,
- done_w_o => done_w,
-
- --to the BRAM
- d_ram_i => d_ram_i,
- q_ram_o => q_ram_o,
- a_ram_o => a_ram_o,
- we_ram_o => we_ram_o,
- re_ram_o => re_ram_o,
- valid_ram_i => valid_ram_i,
-
- lock_req_o => lock_req_o,
- lock_grant_i => lock_grant_i,
-
- single_error_p_o => single_error_p_o,
- double_error_p_o => double_error_p_o,
- read_fault_p_o => open,
- write_fault_p_o => open
- );
-end generate ecc_simple;
-
-ecc_daec : if g_data_width = 42 generate
- ecc_circuitry : secded_ecc_daec
- generic map (
- g_addr_width => g_addr_width
- )
- port map (
- clk_i => clk_i,
- rst_i => rst_i,
-
-
- d_i => data_in,
- a_i => addr,
- we_i => we and not done_w,
- bwe_i => bwe,
- re_i => re and not done_r,
-
- q_o => data_out,
- done_r_o => done_r,
- done_w_o => done_w,
-
- --to the BRAM
- d_ram_i => d_ram_i,
- q_ram_o => q_ram_o,
- a_ram_o => a_ram_o,
- we_ram_o => we_ram_o,
- re_ram_o => re_ram_o,
- valid_ram_i => valid_ram_i,
-
- lock_req_o => lock_req_o,
- lock_grant_i => lock_grant_i,
-
- single_error_p_o => single_error_p_o,
- double_error_p_o => double_error_p_o,
- read_fault_p_o => open,
- write_fault_p_o => open
- );
-
-end generate ecc_daec;
-
-
+ ecc_simple : if g_data_width = 39 generate
+ ecc_circuitry : secded_ecc
+ generic map (
+ g_addr_width => g_addr_width
+ )
+ port map (
+ clk_i => clk_i,
+ rst_i => rst_i,
+
+
+ d_i => data_in,
+ a_i => addr,
+ we_i => we and not done_w,
+ bwe_i => bwe,
+ re_i => re and not done_r,
+
+ q_o => data_out,
+ done_r_o => done_r,
+ done_w_o => done_w,
+
+ --to the BRAM
+ d_ram_i => d_ram_i,
+ q_ram_o => q_ram_o,
+ a_ram_o => a_ram_o,
+ we_ram_o => we_ram_o,
+ re_ram_o => re_ram_o,
+ valid_ram_i => valid_ram_i,
+
+ lock_req_o => lock_req_o,
+ lock_grant_i => lock_grant_i,
+
+ single_error_p_o => single_error_p_o,
+ double_error_p_o => double_error_p_o,
+ read_fault_p_o => open,
+ write_fault_p_o => open
+ );
+ end generate ecc_simple;
+
+ ecc_daec : if g_data_width = 42 generate
+ ecc_circuitry : secded_ecc_daec
+ generic map (
+ g_addr_width => g_addr_width
+ )
+ port map (
+ clk_i => clk_i,
+ rst_i => rst_i,
+
+ d_i => data_in,
+ a_i => addr,
+ we_i => we and not done_w,
+ bwe_i => bwe,
+ re_i => re and not done_r,
+
+ q_o => data_out,
+ done_r_o => done_r,
+ done_w_o => done_w,
+
+ --to the BRAM
+ d_ram_i => d_ram_i,
+ q_ram_o => q_ram_o,
+ a_ram_o => a_ram_o,
+ we_ram_o => we_ram_o,
+ re_ram_o => re_ram_o,
+ valid_ram_i => valid_ram_i,
+
+ lock_req_o => lock_req_o,
+ lock_grant_i => lock_grant_i,
+
+ single_error_p_o => single_error_p_o,
+ double_error_p_o => double_error_p_o,
+ read_fault_p_o => open,
+ write_fault_p_o => open
+ );
+ end generate ecc_daec;
end architecture;
\ No newline at end of file
diff --git a/hdl/xwb_seu_reg.vhd b/hdl/xwb_seu_reg.vhd
index 0d13842ceae7081f247e64fe5da0eff43a32ab87..a2f030c66c53691f66f066703bdb4a67a7a522f9 100644
--- a/hdl/xwb_seu_reg.vhd
+++ b/hdl/xwb_seu_reg.vhd
@@ -83,8 +83,7 @@ begin
slave_o.err <= '0';
slave_o.rty <= '0';
- slave_o.int <='0';
-
+
desc_o <= (others => '0');
diff --git a/hdl/xwb_uart.vhd b/hdl/xwb_uart.vhd
index d8c4f26dd4398dae246a1f8d02f3a14e7243e446..37a645f42fef96302f637006a9347b5b8f7583e8 100644
--- a/hdl/xwb_uart.vhd
+++ b/hdl/xwb_uart.vhd
@@ -78,7 +78,6 @@ begin
slave_o.err <= '0';
slave_o.rty <= '0';
- slave_o.int <='0';
desc_o <= (others => '0');
diff --git a/hdl/xwb_wd_reg.vhd b/hdl/xwb_wd_reg.vhd
index bb73699a2de6424d28e7dd97e7fb9fc2d10fe2d5..01190f01578d58b6fd7526256373fb7ace0b2e48 100644
--- a/hdl/xwb_wd_reg.vhd
+++ b/hdl/xwb_wd_reg.vhd
@@ -70,7 +70,6 @@ begin
slave_o.err <= '0';
slave_o.rty <= '0';
- slave_o.int <='0';
desc_o <= (others => '0');