diff --git a/hdl/rtl/hydra_core.vhd b/hdl/rtl/hydra_core.vhd
index 659b23ec5b74a131d1ee42aac617ba0cf7e7ec44..3c884e09f058fbbbf35f73fbf9aac0d33b0af1b6 100644
--- a/hdl/rtl/hydra_core.vhd
+++ b/hdl/rtl/hydra_core.vhd
@@ -50,7 +50,9 @@ entity hydra_core is
     --  IRAM write access (during reset)
     iram_addr : in  std_logic_vector(g_IRAM_LOG_SIZE - 1 downto 2);
     iram_we   : in  std_logic;
-    iram_data : in  std_logic_vector(31 downto 0)
+    iram_data : in  std_logic_vector(31 downto 0);
+
+    cpu_err_o : out std_logic
   );
 end hydra_core;
 
@@ -83,7 +85,7 @@ architecture arch of hydra_core is
     return x;
   end function f_x_to_zero;
 
-  signal cpu_rst        : std_logic_vector(1 to 3);
+  signal cpu_rst, cpu_rst2        : std_logic_vector(1 to 3);
   signal cpu_rst_err    : std_logic;
   signal cpu_sync       : std_logic_vector(1 to 3);
 
@@ -141,10 +143,13 @@ architecture arch of hydra_core is
 begin
   dwb_o <= dwb_out;
 
+  cpu_rst2 <= "111" when rst_n_i = '0' or cpu_rst_n_i = '0' else "000";
+  cpu_err_o <= '1' when cpu_rst /= "111" else '0';
+      
   inst_cpus : entity work.hydra_triple_cpu
     port map (
       clk_i            => clk_sys_i,
-      cpu_rst_i        => cpu_rst,
+      cpu_rst_i        => cpu_rst2,
       im_addr_o        => im_addr,
       im_rd_o          => im_rd,
       im_data_i        => im_data,
diff --git a/hdl/top/sf2-test/sf2_test.vhd b/hdl/top/sf2-test/sf2_test.vhd
index 68788f37545b6347b34bf7833328d21b3ab24251..de18fb1d5b3f77217c1c1a425533a56750fdf8eb 100644
--- a/hdl/top/sf2-test/sf2_test.vhd
+++ b/hdl/top/sf2-test/sf2_test.vhd
@@ -77,6 +77,7 @@ architecture behav of sf2_test is
   signal dwb_out : t_wishbone_master_out;
   signal dwb_in  : t_wishbone_master_in;
 
+  signal cpu_err : std_logic;
 begin
   inst_hydra: entity work.hydra_core
     generic map (
@@ -92,7 +93,8 @@ begin
       dwb_i => dwb_in,
       iram_addr => iram_addr,
       iram_data => iram_data,
-      iram_we => iram_we
+      iram_we => iram_we,
+      cpu_err_o => cpu_err
     );
 
   inst_uart: entity work.uart
@@ -126,14 +128,31 @@ begin
   rst_n <= POWER_ON_RESET_N and LOCK and MSS_RESET_N_M2F;
   
   proc_led: process (clk_100)
+    variable led1_cnt : natural;
   begin
     if rising_edge(clk_100) then
       if rst_n = '0' then
-        led1_o <= '1';
+        led1_o <= '0';
         led2_o <= '0';
+        led1_cnt := 0;
       else
-        led1_o <= counter (25);
-        led2_o <= counter (23);
+        --  led1 is the led on the right (close to USB)
+        if led1_cnt /= 0 then
+          led1_cnt := led1_cnt - 1;
+        else
+          led1_o <= '0';
+        end if;
+        if cpu_err = '1' then
+          led1_o <= '1';
+          led1_cnt := 10_000_000;
+        end if;
+
+        --  led1_o <= counter (25);
+        --  led2 is the led on the left (close to the hole).
+        --  A led is on (emits light) when its input is 1.
+        if state = DONE and counter (26) = '1' then
+          led2_o <= '1';
+        end if;
       end if;
     end if;
   end process;