From defc6aef130b3cd908e98e4c774b4f2d82eaa10f Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tristan.gingold@cern.ch>
Date: Tue, 3 May 2022 10:21:39 +0200
Subject: [PATCH] hydra_core.vhd: rework watchdog period
---
hdl/rtl/hydra_core.vhd | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/hdl/rtl/hydra_core.vhd b/hdl/rtl/hydra_core.vhd
index fa1b83e..5dbb69b 100644
--- a/hdl/rtl/hydra_core.vhd
+++ b/hdl/rtl/hydra_core.vhd
@@ -130,6 +130,9 @@ architecture arch of hydra_core is
signal reset_cause_cpu, reset_cause_ecc, reset_cause_wd : std_logic;
signal dram_scrub_period, iram_scrub_period : std_logic_vector(15 downto 0);
+ -- Initial watchdog period.
+ constant wd_init : std_logic_vector(31 downto 0) := x"0000_0400";
+
signal wd_period, wd_period_val, wd_counter, wd_key_val : std_logic_vector(31 downto 0);
signal wd_period_wr, wd_key_wr, wd_timeout : std_logic;
@@ -424,20 +427,21 @@ begin
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
- wd_period <= x"0000_0400";
- wd_counter <= x"0000_0400";
+ wd_period <= wd_init;
+ wd_counter <= wd_init;
wd_timeout <= '0';
else
wd_timeout <= '0';
if wd_period_wr = '1' then
-- Period change
+ -- Note: counter doesn't change.
wd_period <= wd_period_val;
- wd_counter <= wd_period_val;
else
if wd_counter = (wd_counter'range => '0') then
-- Timeout
wd_timeout <= '1';
- wd_counter <= wd_period;
+ -- Use the initial (small) period
+ wd_counter <= wd_init;
elsif cpu_rst = "111" or (wd_key_wr = '1' and wd_key_val = x"c0423bc9") then
-- Key -> reload
-- Also restart the watchdog if the cpu is reset.
--
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