From da859fe58eaf8029414cc6536b5424f415af8c6f Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tristan.gingold@cern.ch>
Date: Mon, 2 May 2022 15:35:54 +0200
Subject: [PATCH] iram: don't scrub during cpu reset
---
hdl/rtl/hydra_core.vhd | 1 +
hdl/rtl/hydra_iram.vhd | 8 +++++---
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/hdl/rtl/hydra_core.vhd b/hdl/rtl/hydra_core.vhd
index 3c884e0..80e67a6 100644
--- a/hdl/rtl/hydra_core.vhd
+++ b/hdl/rtl/hydra_core.vhd
@@ -191,6 +191,7 @@ begin
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
+ cpu_rst_n_i => cpu_rst_n_i,
-- uRV data read from iRAM
r1_addr_i => reg_dm_addr(g_IRAM_LOG_SIZE - 1 downto 2),
diff --git a/hdl/rtl/hydra_iram.vhd b/hdl/rtl/hydra_iram.vhd
index 2229e94..84bb475 100644
--- a/hdl/rtl/hydra_iram.vhd
+++ b/hdl/rtl/hydra_iram.vhd
@@ -37,6 +37,7 @@ entity hydra_iram is
-- Note: only writes are allowed during reset.
clk_i : in std_logic;
rst_n_i : in std_logic;
+ cpu_rst_n_i : in std_logic;
-- Port 1: read access (high priority)
-- RDONE_O is a pulse.
@@ -97,7 +98,7 @@ begin
-- The raw ram.
p_ram: process (clk_i)
is
- variable iram : t_ram39_type(0 to RAM_WSIZE - 1);
+ variable iram : t_ram39_type(0 to RAM_WSIZE - 1) := (others => (others => '1'));
variable d : std_logic_vector(38 downto 0);
variable err : std_logic_vector(38 downto 0) := (0 => '1', others => '0');
variable sim_cnt : natural;
@@ -227,8 +228,9 @@ begin
ren <= '1';
n_r2_done <= '1';
n_last_raddr <= r2_addr_i;
- elsif rst_n_i = '1' then
- -- scrub if idle (but not during reset)
+ elsif cpu_rst_n_i = '1' then
+ -- scrub if idle (but not during reset, as write is high priority
+ -- and is a single pulse).
raddr <= scrub_addr;
ren <= '1';
n_scrub_done <= '1';
--
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