diff --git a/hydra.prjx b/hydra.prjx index 8fb2a43652c1420378efe1c2babb5d15fb82a8b1..470a64aad2b440c0016c517545f98e63508e4dc3 100644 --- a/hydra.prjx +++ b/hydra.prjx @@ -31,7 +31,7 @@ KEY VendorTechnology_VCCI_1.8_VOLTR "COM" KEY VendorTechnology_VCCI_2.5_VOLTR "COM" KEY VendorTechnology_VCCI_3.3_VOLTR "COM" KEY VendorTechnology_VOLTR "IND" -KEY ProjectLocation "C:\Users\mattia\Downloads\hydra-master (4)\hydra-master" +KEY ProjectLocation "C:\Users\mattia\Downloads\hydra-master (5)\hydra-master" KEY ProjectDescription "" KEY Pa4PeripheralNewSeq "GOOD" KEY SimulationType "VERILOG" @@ -41,120 +41,137 @@ LIST REVISIONS VALUE="Impl1",NUM=1 VALUE="Impl2",NUM=2 VALUE="Impl3",NUM=3 -CURREV=3 +VALUE="Impl4",NUM=4 +CURREV=4 ENDLIST LIST FileManager VALUE "<project>\component\Actel\SmartFusion2MSS\MSS\1.1.500\MSS.cxf,actgen_cxf" STATE="utd" -TIME="1607943296" +TIME="1607954613" SIZE="526" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" ENDFILE +VALUE "<project>\component\Actel\SmartFusion2MSS\MSS\1.1.500\peripheral_init.bfm,sim" +STATE="utd" +TIME="1607954613" +SIZE="8450" +PARENT="<project>\component\Actel\SmartFusion2MSS\MSS\1.1.500\MSS.cxf" +ENDFILE VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_CCC\1.0.100\MSS_CCC.cxf,actgen_cxf" STATE="utd" -TIME="1607943296" +TIME="1607954613" SIZE="253" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" ENDFILE VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_CC\1.0.100\MSS_CC.cxf,actgen_cxf" STATE="utd" -TIME="1607943296" +TIME="1607954613" SIZE="252" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" ENDFILE VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_CFGM\1.1.100\MSS_CFGM.cxf,actgen_cxf" STATE="utd" -TIME="1607943297" +TIME="1607954613" SIZE="254" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" ENDFILE VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_CM3\1.0.200\MSS_CM3.cxf,actgen_cxf" STATE="utd" -TIME="1607943297" +TIME="1607954613" SIZE="253" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" ENDFILE VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_DDRB\1.0.200\MSS_DDRB.cxf,actgen_cxf" STATE="utd" -TIME="1607943297" +TIME="1607954613" SIZE="254" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" ENDFILE VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_EDAC\1.0.101\MSS_EDAC.cxf,actgen_cxf" STATE="utd" -TIME="1607943297" +TIME="1607954613" SIZE="254" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" ENDFILE VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_ENVM\1.0.101\MSS_ENVM.cxf,actgen_cxf" STATE="utd" -TIME="1607943297" +TIME="1607954613" SIZE="254" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" ENDFILE VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_FIC32\1.0.100\MSS_FIC32.cxf,actgen_cxf" STATE="utd" -TIME="1607943297" +TIME="1607954613" SIZE="255" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" ENDFILE VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_INTR\1.0.200\MSS_INTR.cxf,actgen_cxf" STATE="utd" -TIME="1607943297" +TIME="1607954613" SIZE="254" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" ENDFILE VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_RESET\1.0.100\MSS_RESET.cxf,actgen_cxf" STATE="utd" -TIME="1607943297" +TIME="1607954613" SIZE="255" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" ENDFILE VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_RTC\1.0.201\MSS_RTC.cxf,actgen_cxf" STATE="utd" -TIME="1607943297" +TIME="1607954614" SIZE="253" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" ENDFILE VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_SECURITY\1.0.100\MSS_SECURITY.cxf,actgen_cxf" STATE="utd" -TIME="1607943297" +TIME="1607954614" SIZE="258" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" ENDFILE VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_SWITCH\1.0.101\MSS_SWITCH.cxf,actgen_cxf" STATE="utd" -TIME="1607943297" +TIME="1607954614" SIZE="256" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" ENDFILE VALUE "<project>\component\work\hydra\hydra.cxf,actgen_cxf" STATE="utd" -TIME="1607943297" +TIME="1607954614" SIZE="4639" ENDFILE VALUE "<project>\component\work\hydra\hydra.v,hdl" STATE="utd" -TIME="1607943297" +TIME="1607954614" SIZE="8204" PARENT="<project>\component\work\hydra\hydra.cxf" IS_READONLY="TRUE" ENDFILE +VALUE "<project>\component\work\hydra\subsystem.bfm,sim" +STATE="utd" +TIME="1607954614" +SIZE="602" +ENDFILE +VALUE "<project>\component\work\hydra_MSS\CM3_compile_bfm.tcl,sim" +STATE="utd" +TIME="1607954614" +SIZE="500" +ENDFILE VALUE "<project>\component\work\hydra_MSS\hydra_MSS.cxf,actgen_cxf" STATE="utd" -TIME="1607943298" +TIME="1607954614" SIZE="11844" ENDFILE VALUE "<project>\component\work\hydra_MSS\hydra_MSS.v,hdl" STATE="utd" -TIME="1607943298" +TIME="1607954614" SIZE="48497" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" IS_READONLY="TRUE" ENDFILE VALUE "<project>\component\work\hydra_MSS\hydra_MSS_pre.v,hdl" STATE="utd" -TIME="1607943298" +TIME="1607954615" SIZE="64284" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" BEGIN_USE_CONSTRAINT @@ -166,7 +183,7 @@ IS_READONLY="TRUE" ENDFILE VALUE "<project>\component\work\hydra_MSS\hydra_MSS_pre.vhd,hdl" STATE="utd" -TIME="1607943298" +TIME="1607954615" SIZE="80667" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" BEGIN_USE_CONSTRAINT @@ -178,7 +195,7 @@ IS_READONLY="TRUE" ENDFILE VALUE "<project>\component\work\hydra_MSS\hydra_MSS_syn.v,hdl" STATE="utd" -TIME="1607943298" +TIME="1607954615" SIZE="56527" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" BEGIN_USE_CONSTRAINT @@ -188,380 +205,415 @@ END_USE_CONSTRAINT USE_FOR_ANY_TOOL="FALSE" IS_READONLY="TRUE" ENDFILE +VALUE "<project>\component\work\hydra_MSS\test.bfm,sim" +STATE="utd" +TIME="1607954615" +SIZE="734" +ENDFILE +VALUE "<project>\component\work\hydra_MSS\user.bfm,sim" +STATE="utd" +TIME="1607954615" +SIZE="555" +ENDFILE VALUE "<project>\constraint\fp\user.pdc,fp_pdc" STATE="utd" -TIME="1607943298" +TIME="1607954615" SIZE="891" IS_TARGET="TRUE" ENDFILE VALUE "<project>\constraint\io\m2s050_som.io.pdc,io_pdc" STATE="utd" -TIME="1607943298" +TIME="1607954615" SIZE="3087" ENDFILE VALUE "<project>\constraint\timing.sdc,sdc" STATE="utd" -TIME="1607943298" +TIME="1607954615" SIZE="2151" ENDFILE -VALUE "<project>\designer\impl3\hydra.ide_des,ide_des" +VALUE "<project>\designer\impl4\hydra.ide_des,ide_des" STATE="utd" -TIME="1607943329" +TIME="1607954645" SIZE="212" ENDFILE VALUE "<project>\hdl\axis_assert.vhd,hdl" STATE="utd" -TIME="1607943299" +TIME="1607954615" SIZE="5469" ENDFILE VALUE "<project>\hdl\axis_fifo_cdc.vhd,hdl" STATE="utd" -TIME="1607943299" +TIME="1607954615" SIZE="12441" ENDFILE VALUE "<project>\hdl\clock_buffer.vhd,hdl" STATE="utd" -TIME="1607943299" +TIME="1607954615" SIZE="1021" ENDFILE VALUE "<project>\hdl\dpram_generic.vhd,hdl" STATE="utd" -TIME="1607943299" +TIME="1607954615" SIZE="12853" ENDFILE VALUE "<project>\hdl\ram_voter.vhd,hdl" STATE="utd" -TIME="1607943299" +TIME="1607954616" SIZE="2129" ENDFILE VALUE "<project>\hdl\reset_gen.vhd,hdl" STATE="utd" -TIME="1607943299" +TIME="1607954616" SIZE="1664" ENDFILE VALUE "<project>\hdl\rst_filter.vhd,hdl" STATE="utd" -TIME="1607943299" +TIME="1607954616" SIZE="866" ENDFILE VALUE "<project>\hdl\sdram_cdc_r.vhd,hdl" STATE="utd" -TIME="1607943299" +TIME="1607954616" SIZE="1664" ENDFILE VALUE "<project>\hdl\secded_ecc.vhd,hdl" STATE="utd" -TIME="1607943299" +TIME="1607954616" SIZE="12912" ENDFILE VALUE "<project>\hdl\secded_ecc_daec.vhd,hdl" STATE="utd" -TIME="1607943299" +TIME="1607954616" SIZE="17193" ENDFILE VALUE "<project>\hdl\seu_counters.vhd,hdl" STATE="utd" -TIME="1607943299" +TIME="1607954616" SIZE="2092" ENDFILE VALUE "<project>\hdl\uart.v,hdl" STATE="utd" -TIME="1607943299" +TIME="1607954616" SIZE="2316" ENDFILE VALUE "<project>\hdl\ueth.vhd,hdl" STATE="utd" -TIME="1607943299" +TIME="1607954616" SIZE="4891" ENDFILE VALUE "<project>\hdl\ueth_crc.vhd,hdl" STATE="utd" -TIME="1607943299" +TIME="1607954616" SIZE="3177" ENDFILE VALUE "<project>\hdl\ueth_dma.vhd,hdl" STATE="utd" -TIME="1607943299" +TIME="1607954616" SIZE="19463" ENDFILE VALUE "<project>\hdl\ueth_hub.vhd,hdl" STATE="utd" -TIME="1607943300" +TIME="1607954616" SIZE="7485" ENDFILE VALUE "<project>\hdl\ueth_mac.vhd,hdl" STATE="utd" -TIME="1607943300" +TIME="1607954616" SIZE="15827" ENDFILE VALUE "<project>\hdl\ueth_miim.vhd,hdl" STATE="utd" -TIME="1607943300" +TIME="1607954616" SIZE="5655" ENDFILE VALUE "<project>\hdl\ueth_uphy.vhd,hdl" STATE="utd" -TIME="1607943300" +TIME="1607954616" SIZE="4713" ENDFILE VALUE "<project>\hdl\urv_core_DTMR.vhd,hdl" STATE="utd" -TIME="1607943300" +TIME="1607954616" SIZE="13440" ENDFILE VALUE "<project>\hdl\urv_soc.vhd,hdl" STATE="utd" -TIME="1607943300" +TIME="1607954616" SIZE="30808" ENDFILE VALUE "<project>\hdl\urv_supervisor.vhd,hdl" STATE="utd" -TIME="1607943300" +TIME="1607954616" SIZE="4646" ENDFILE VALUE "<project>\hdl\wb_envm.vhd,hdl" STATE="utd" -TIME="1607943300" +TIME="1607954617" SIZE="7675" ENDFILE VALUE "<project>\hdl\wb_master_voter.vhd,hdl" STATE="utd" -TIME="1607943300" +TIME="1607954617" SIZE="1685" ENDFILE VALUE "<project>\hdl\wb_seu_reg.vhdl,hdl" STATE="utd" -TIME="1607943300" +TIME="1607954617" SIZE="4684" ENDFILE VALUE "<project>\hdl\wb_slave_voter.vhd,hdl" STATE="utd" -TIME="1607943300" +TIME="1607954617" SIZE="1154" ENDFILE VALUE "<project>\hdl\wb_uart.vhdl,hdl" STATE="utd" -TIME="1607943300" +TIME="1607954617" SIZE="7444" ENDFILE VALUE "<project>\hdl\wb_wd_reg.vhdl,hdl" STATE="utd" -TIME="1607943300" +TIME="1607954617" SIZE="5376" ENDFILE VALUE "<project>\hdl\xwb_ram_adapter.vhdl,hdl" STATE="utd" -TIME="1607943300" +TIME="1607954617" SIZE="8791" ENDFILE VALUE "<project>\hdl\xwb_seu_reg.vhd,hdl" STATE="utd" -TIME="1607943300" +TIME="1607954617" SIZE="3180" ENDFILE VALUE "<project>\hdl\xwb_supervisor_reg.vhd,hdl" STATE="utd" -TIME="1607943300" +TIME="1607954617" SIZE="2854" ENDFILE VALUE "<project>\hdl\xwb_uart.vhd,hdl" STATE="utd" -TIME="1607943301" +TIME="1607954617" SIZE="2888" ENDFILE VALUE "<project>\hdl\xwb_wd_reg.vhd,hdl" STATE="utd" -TIME="1607943301" +TIME="1607954617" SIZE="2215" ENDFILE VALUE "<project>\simulation\CM3_compile_bfm.tcl,sim" STATE="utd" -TIME="1607943298" +TIME="1607954614" SIZE="500" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" ENDFILE VALUE "<project>\simulation\peripheral_init.bfm,sim" STATE="utd" -TIME="1607943296" +TIME="1607954613" SIZE="8450" PARENT="<project>\component\Actel\SmartFusion2MSS\MSS\1.1.500\MSS.cxf" ENDFILE VALUE "<project>\simulation\subsystem.bfm,sim" STATE="utd" -TIME="1607943298" +TIME="1607954614" SIZE="602" PARENT="<project>\component\work\hydra\hydra.cxf" ENDFILE VALUE "<project>\simulation\test.bfm,sim" STATE="utd" -TIME="1607943298" +TIME="1607954615" SIZE="734" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" ENDFILE VALUE "<project>\simulation\user.bfm,sim" STATE="utd" -TIME="1607943298" +TIME="1607954615" SIZE="555" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" ENDFILE VALUE "<project>\synthesis\hydra_syn.prj,prj" STATE="utd" -TIME="1607943628" -SIZE="6757" +TIME="1607954753" +SIZE="6758" ENDFILE VALUE "<project>\synthesis\rev_1\hydra.edn,syn_edn" -STATE="utd" -TIME="1607943440" -SIZE="24833985" +STATE="ood" +TIME="1607954750" +SIZE="24833984" ENDFILE VALUE "<project>\synthesis\rev_1\hydra.so,so" STATE="utd" -TIME="1607943627" -SIZE="246" -ENDFILE -VALUE "<project>\synthesis\rev_1\hydra.v,syn_hdl" -STATE="utd" -TIME="1607943641" -SIZE="7337797" +TIME="1607954752" +SIZE="241" ENDFILE VALUE "<project>\synthesis\rev_1\hydra.vm,syn_vm" STATE="utd" -TIME="1607943624" -SIZE="7783225" -ENDFILE -VALUE "<project>\synthesis\rev_1\hydra_sdc.sdc,syn_sdc" -STATE="utd" -TIME="1607943439" -SIZE="2066" +TIME="1607955470" +SIZE="7783669" ENDFILE VALUE "<project>\synthesis\rev_1\hydra_vm.sdc,syn_sdc" STATE="utd" -TIME="1607943625" +TIME="1607955472" SIZE="2066" ENDFILE -VALUE "G:\Users\r\rizzi\powerlink\urv-core-irq-patched\rtl\urv_config.v,hdl" -LINKFILEROOT "G:/Users/r/rizzi/powerlink/urv-core-irq-patched/rtl" +VALUE "C:\Users\mattia\Downloads\hydra-master (5)\hydra-master\dependencies\urv-core\rtl\urv_config.v,hdl" +LINKFILEROOT "C:/Users/mattia/Downloads/hydra-master (5)/hydra-master/dependencies/urv-core/rtl" STATE="utd" -TIME="1564556834" +TIME="1607954862" SIZE="1435" IS_READONLY="TRUE" ENDFILE -VALUE "G:\Users\r\rizzi\powerlink\urv-core-irq-patched\rtl\urv_cpu.v,hdl" -LINKFILEROOT "G:/Users/r/rizzi/powerlink/urv-core-irq-patched/rtl" +VALUE "C:\Users\mattia\Downloads\hydra-master (5)\hydra-master\dependencies\urv-core\rtl\urv_cpu.v,hdl" +LINKFILEROOT "C:/Users/mattia/Downloads/hydra-master (5)/hydra-master/dependencies/urv-core/rtl" STATE="utd" -TIME="1568367999" -SIZE="11642" +TIME="1607954862" +SIZE="11222" IS_READONLY="TRUE" ENDFILE -VALUE "G:\Users\r\rizzi\powerlink\urv-core-irq-patched\rtl\urv_csr.v,hdl" -LINKFILEROOT "G:/Users/r/rizzi/powerlink/urv-core-irq-patched/rtl" +VALUE "C:\Users\mattia\Downloads\hydra-master (5)\hydra-master\dependencies\urv-core\rtl\urv_csr.v,hdl" +LINKFILEROOT "C:/Users/mattia/Downloads/hydra-master (5)/hydra-master/dependencies/urv-core/rtl" STATE="utd" -TIME="1592987380" +TIME="1607954862" SIZE="4434" IS_READONLY="TRUE" ENDFILE -VALUE "G:\Users\r\rizzi\powerlink\urv-core-irq-patched\rtl\urv_decode.v,hdl" -LINKFILEROOT "G:/Users/r/rizzi/powerlink/urv-core-irq-patched/rtl" +VALUE "C:\Users\mattia\Downloads\hydra-master (5)\hydra-master\dependencies\urv-core\rtl\urv_debug.v,hdl" +LINKFILEROOT "C:/Users/mattia/Downloads/hydra-master (5)/hydra-master/dependencies/urv-core/rtl" +STATE="utd" +TIME="1607954862" +SIZE="3915" +IS_READONLY="TRUE" +ENDFILE +VALUE "C:\Users\mattia\Downloads\hydra-master (5)\hydra-master\dependencies\urv-core\rtl\urv_decode.v,hdl" +LINKFILEROOT "C:/Users/mattia/Downloads/hydra-master (5)/hydra-master/dependencies/urv-core/rtl" STATE="utd" -TIME="1564556834" +TIME="1607954862" SIZE="9979" IS_READONLY="TRUE" ENDFILE -VALUE "G:\Users\r\rizzi\powerlink\urv-core-irq-patched\rtl\urv_defs.v,hdl" -LINKFILEROOT "G:/Users/r/rizzi/powerlink/urv-core-irq-patched/rtl" +VALUE "C:\Users\mattia\Downloads\hydra-master (5)\hydra-master\dependencies\urv-core\rtl\urv_defs.v,hdl" +LINKFILEROOT "C:/Users/mattia/Downloads/hydra-master (5)/hydra-master/dependencies/urv-core/rtl" STATE="utd" -TIME="1568114320" -SIZE="3493" +TIME="1607954862" +SIZE="3492" IS_READONLY="TRUE" ENDFILE -VALUE "G:\Users\r\rizzi\powerlink\urv-core-irq-patched\rtl\urv_exceptions.v,hdl" -LINKFILEROOT "G:/Users/r/rizzi/powerlink/urv-core-irq-patched/rtl" +VALUE "C:\Users\mattia\Downloads\hydra-master (5)\hydra-master\dependencies\urv-core\rtl\urv_divide.v,hdl" +LINKFILEROOT "C:/Users/mattia/Downloads/hydra-master (5)/hydra-master/dependencies/urv-core/rtl" STATE="utd" -TIME="1568731323" +TIME="1607954862" +SIZE="4004" +IS_READONLY="TRUE" +ENDFILE +VALUE "C:\Users\mattia\Downloads\hydra-master (5)\hydra-master\dependencies\urv-core\rtl\urv_exceptions.v,hdl" +LINKFILEROOT "C:/Users/mattia/Downloads/hydra-master (5)/hydra-master/dependencies/urv-core/rtl" +STATE="utd" +TIME="1607954862" SIZE="4261" IS_READONLY="TRUE" ENDFILE -VALUE "G:\Users\r\rizzi\powerlink\urv-core-irq-patched\rtl\urv_exec.v,hdl" -LINKFILEROOT "G:/Users/r/rizzi/powerlink/urv-core-irq-patched/rtl" +VALUE "C:\Users\mattia\Downloads\hydra-master (5)\hydra-master\dependencies\urv-core\rtl\urv_exec.v,hdl" +LINKFILEROOT "C:/Users/mattia/Downloads/hydra-master (5)/hydra-master/dependencies/urv-core/rtl" STATE="utd" -TIME="1604860468" +TIME="1607954862" SIZE="14520" IS_READONLY="TRUE" ENDFILE -VALUE "G:\Users\r\rizzi\powerlink\urv-core-irq-patched\rtl\urv_fetch.v,hdl" -LINKFILEROOT "G:/Users/r/rizzi/powerlink/urv-core-irq-patched/rtl" +VALUE "C:\Users\mattia\Downloads\hydra-master (5)\hydra-master\dependencies\urv-core\rtl\urv_fetch.v,hdl" +LINKFILEROOT "C:/Users/mattia/Downloads/hydra-master (5)/hydra-master/dependencies/urv-core/rtl" STATE="utd" -TIME="1568104439" +TIME="1607954862" SIZE="4881" IS_READONLY="TRUE" ENDFILE -VALUE "G:\Users\r\rizzi\powerlink\urv-core-irq-patched\rtl\urv_regfile.v,hdl" -LINKFILEROOT "G:/Users/r/rizzi/powerlink/urv-core-irq-patched/rtl" +VALUE "C:\Users\mattia\Downloads\hydra-master (5)\hydra-master\dependencies\urv-core\rtl\urv_iram.v,hdl" +LINKFILEROOT "C:/Users/mattia/Downloads/hydra-master (5)/hydra-master/dependencies/urv-core/rtl" STATE="utd" -TIME="1568723867" -SIZE="4712" +TIME="1607954862" +SIZE="12223" IS_READONLY="TRUE" ENDFILE -VALUE "G:\Users\r\rizzi\powerlink\urv-core-irq-patched\rtl\urv_shifter.v,hdl" -LINKFILEROOT "G:/Users/r/rizzi/powerlink/urv-core-irq-patched/rtl" +VALUE "C:\Users\mattia\Downloads\hydra-master (5)\hydra-master\dependencies\urv-core\rtl\urv_multiply.v,hdl" +LINKFILEROOT "C:/Users/mattia/Downloads/hydra-master (5)/hydra-master/dependencies/urv-core/rtl" STATE="utd" -TIME="1564556834" +TIME="1607954862" +SIZE="6610" +IS_READONLY="TRUE" +ENDFILE +VALUE "C:\Users\mattia\Downloads\hydra-master (5)\hydra-master\dependencies\urv-core\rtl\urv_regfile.v,hdl" +LINKFILEROOT "C:/Users/mattia/Downloads/hydra-master (5)/hydra-master/dependencies/urv-core/rtl" +STATE="utd" +TIME="1607954862" +SIZE="4521" +IS_READONLY="TRUE" +ENDFILE +VALUE "C:\Users\mattia\Downloads\hydra-master (5)\hydra-master\dependencies\urv-core\rtl\urv_shifter.v,hdl" +LINKFILEROOT "C:/Users/mattia/Downloads/hydra-master (5)/hydra-master/dependencies/urv-core/rtl" +STATE="utd" +TIME="1607954862" SIZE="2999" IS_READONLY="TRUE" ENDFILE -VALUE "G:\Users\r\rizzi\powerlink\urv-core-irq-patched\rtl\urv_timer.v,hdl" -LINKFILEROOT "G:/Users/r/rizzi/powerlink/urv-core-irq-patched/rtl" +VALUE "C:\Users\mattia\Downloads\hydra-master (5)\hydra-master\dependencies\urv-core\rtl\urv_timer.v,hdl" +LINKFILEROOT "C:/Users/mattia/Downloads/hydra-master (5)/hydra-master/dependencies/urv-core/rtl" STATE="utd" -TIME="1568104993" +TIME="1607954862" SIZE="2311" IS_READONLY="TRUE" ENDFILE -VALUE "G:\Users\r\rizzi\powerlink\urv-core-irq-patched\rtl\urv_writeback.v,hdl" -LINKFILEROOT "G:/Users/r/rizzi/powerlink/urv-core-irq-patched/rtl" +VALUE "C:\Users\mattia\Downloads\hydra-master (5)\hydra-master\dependencies\urv-core\rtl\urv_writeback.v,hdl" +LINKFILEROOT "C:/Users/mattia/Downloads/hydra-master (5)/hydra-master/dependencies/urv-core/rtl" STATE="utd" -TIME="1564556834" +TIME="1607954862" SIZE="4472" IS_READONLY="TRUE" ENDFILE -VALUE "G:\Users\r\rizzi\powerlink\wb_crossbar\sdb_rom.vhd,hdl" -LINKFILEROOT "G:/Users/r/rizzi/powerlink/wb_crossbar" +VALUE "C:\Users\mattia\Downloads\hydra-master (5)\hydra-master\dependencies\urv-core\rtl\xurv_core.vhd,hdl" +LINKFILEROOT "C:/Users/mattia/Downloads/hydra-master (5)/hydra-master/dependencies/urv-core/rtl" +STATE="utd" +TIME="1607954862" +SIZE="8950" +IS_READONLY="TRUE" +ENDFILE +VALUE "C:\Users\mattia\Downloads\hydra-master (5)\hydra-master\dependencies\wb_crossbar\sdb_rom.vhd,hdl" +LINKFILEROOT "C:/Users/mattia/Downloads/hydra-master (5)/hydra-master/dependencies/wb_crossbar" STATE="utd" -TIME="1503998412" +TIME="1607954615" SIZE="5750" IS_READONLY="TRUE" ENDFILE -VALUE "G:\Users\r\rizzi\powerlink\wb_crossbar\wb_skidpad.vhd,hdl" -LINKFILEROOT "G:/Users/r/rizzi/powerlink/wb_crossbar" +VALUE "C:\Users\mattia\Downloads\hydra-master (5)\hydra-master\dependencies\wb_crossbar\wb_skidpad.vhd,hdl" +LINKFILEROOT "C:/Users/mattia/Downloads/hydra-master (5)/hydra-master/dependencies/wb_crossbar" STATE="utd" -TIME="1503998412" +TIME="1607954615" SIZE="2027" IS_READONLY="TRUE" ENDFILE -VALUE "G:\Users\r\rizzi\powerlink\wb_crossbar\wishbone_pkg.vhd,hdl" -LINKFILEROOT "G:/Users/r/rizzi/powerlink/wb_crossbar" +VALUE "C:\Users\mattia\Downloads\hydra-master (5)\hydra-master\dependencies\wb_crossbar\wishbone_pkg.vhd,hdl" +LINKFILEROOT "C:/Users/mattia/Downloads/hydra-master (5)/hydra-master/dependencies/wb_crossbar" STATE="utd" -TIME="1564130312" +TIME="1607954615" SIZE="87625" IS_READONLY="TRUE" ENDFILE -VALUE "G:\Users\r\rizzi\powerlink\wb_crossbar\xwb_crossbar.vhd,hdl" -LINKFILEROOT "G:/Users/r/rizzi/powerlink/wb_crossbar" +VALUE "C:\Users\mattia\Downloads\hydra-master (5)\hydra-master\dependencies\wb_crossbar\xwb_crossbar.vhd,hdl" +LINKFILEROOT "C:/Users/mattia/Downloads/hydra-master (5)/hydra-master/dependencies/wb_crossbar" STATE="utd" -TIME="1561473300" +TIME="1607954615" SIZE="16801" IS_READONLY="TRUE" ENDFILE -VALUE "G:\Users\r\rizzi\powerlink\wb_crossbar\xwb_register_link.vhd,hdl" -LINKFILEROOT "G:/Users/r/rizzi/powerlink/wb_crossbar" +VALUE "C:\Users\mattia\Downloads\hydra-master (5)\hydra-master\dependencies\wb_crossbar\xwb_register_link.vhd,hdl" +LINKFILEROOT "C:/Users/mattia/Downloads/hydra-master (5)/hydra-master/dependencies/wb_crossbar" STATE="utd" -TIME="1503998412" +TIME="1607954615" SIZE="3016" IS_READONLY="TRUE" ENDFILE -VALUE "G:\Users\r\rizzi\powerlink\wb_crossbar\xwb_sdb_crossbar.vhd,hdl" -LINKFILEROOT "G:/Users/r/rizzi/powerlink/wb_crossbar" +VALUE "C:\Users\mattia\Downloads\hydra-master (5)\hydra-master\dependencies\wb_crossbar\xwb_sdb_crossbar.vhd,hdl" +LINKFILEROOT "C:/Users/mattia/Downloads/hydra-master (5)/hydra-master/dependencies/wb_crossbar" STATE="utd" -TIME="1503998412" +TIME="1607954615" SIZE="9627" IS_READONLY="TRUE" ENDFILE @@ -573,6 +625,7 @@ LIST "hydra::work" FILE "<project>\component\work\hydra\hydra.v,hdl" LIST Other_Association VALUE "<project>\simulation\subsystem.bfm,sim" +VALUE "<project>\component\work\hydra\subsystem.bfm,sim" ENDLIST LIST UserCustomizedFileList LIST "ideCOMPILENETLIST" @@ -644,6 +697,25 @@ VALUE "<project>\synthesis\rev_1\hydra.vm,syn_vm" VALUE "<project>\synthesis\rev_1\hydra_sdc.sdc,syn_sdc" ENDUsed_File_List ENDLIST +LIST Impl4 +ideSYNTHESIS(<project>\synthesis\rev_1\hydra.vm,syn_vm)=StateSuccess +LIST FlowOptions +UsePhySynth=FALSE +UseSynth=TRUE +UseFhbAutoInst=FALSE +ENDLIST +Used_File_List +VALUE "<project>\synthesis\hydra.edn,syn_edn" +VALUE "<project>\synthesis\hydra.v,syn_hdl" +VALUE "<project>\phy_synthesis\hydra_palace.edn,palace_edn" +VALUE "<project>\phy_synthesis\hydra_palace.gcf,palace_gcf" +VALUE "<project>\phy_synthesis\hydra_palace.pdc,palace_pdc" +VALUE "<project>\phy_synthesis\hydra_palace.sdc,palace_sdc" +VALUE "<project>\phy_synthesis\hydra_palace.v,palace_hdl" +VALUE "<project>\synthesis\rev_1\hydra.vm,syn_vm" +VALUE "<project>\synthesis\rev_1\hydra_sdc.sdc,syn_sdc" +ENDUsed_File_List +ENDLIST ENDLIST ENDLIST LIST "hydra_MSS::work" @@ -653,6 +725,10 @@ VALUE "<project>\simulation\CM3_compile_bfm.tcl,sim" VALUE "<project>\simulation\user.bfm,sim" VALUE "<project>\simulation\test.bfm,sim" VALUE "<project>\simulation\peripheral_init.bfm,sim" +VALUE "<project>\component\work\hydra_MSS\CM3_compile_bfm.tcl,sim" +VALUE "<project>\component\work\hydra_MSS\user.bfm,sim" +VALUE "<project>\component\work\hydra_MSS\test.bfm,sim" +VALUE "<project>\component\Actel\SmartFusion2MSS\MSS\1.1.500\peripheral_init.bfm,sim" ENDLIST ENDLIST ENDLIST @@ -661,12 +737,17 @@ ENDLIST LIST Other_Association LIST hydra VALUE "<project>\simulation\subsystem.bfm,sim" +VALUE "<project>\component\work\hydra\subsystem.bfm,sim" ENDLIST LIST hydra_MSS VALUE "<project>\simulation\CM3_compile_bfm.tcl,sim" VALUE "<project>\simulation\user.bfm,sim" VALUE "<project>\simulation\test.bfm,sim" VALUE "<project>\simulation\peripheral_init.bfm,sim" +VALUE "<project>\component\work\hydra_MSS\CM3_compile_bfm.tcl,sim" +VALUE "<project>\component\work\hydra_MSS\user.bfm,sim" +VALUE "<project>\component\work\hydra_MSS\test.bfm,sim" +VALUE "<project>\component\Actel\SmartFusion2MSS\MSS\1.1.500\peripheral_init.bfm,sim" ENDLIST ENDLIST LIST SimulationOptions @@ -734,8 +815,8 @@ NAME="Synplify Pro ME" FUNCTION="Synthesis" TOOL="Synplify Pro ME" LOCATION="C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\bin\synplify_pro.exe" -PARAM="" -BATCH=0 +PARAM="-licensetype synplifypro_actel -batch -log synplify.log" +BATCH=1 LICENSE="" IS32BIT="1" EndProfile @@ -824,6 +905,25 @@ VALUE "<project>\synthesis\rev_1\hydra.vm,syn_vm" VALUE "<project>\synthesis\rev_1\hydra_sdc.sdc,syn_sdc" ENDUsed_File_List ENDLIST +LIST Impl4 +ideSYNTHESIS(<project>\synthesis\rev_1\hydra.vm,syn_vm)=StateSuccess +LIST FlowOptions +UsePhySynth=FALSE +UseSynth=TRUE +UseFhbAutoInst=FALSE +ENDLIST +Used_File_List +VALUE "<project>\synthesis\hydra.edn,syn_edn" +VALUE "<project>\synthesis\hydra.v,syn_hdl" +VALUE "<project>\phy_synthesis\hydra_palace.edn,palace_edn" +VALUE "<project>\phy_synthesis\hydra_palace.gcf,palace_gcf" +VALUE "<project>\phy_synthesis\hydra_palace.pdc,palace_pdc" +VALUE "<project>\phy_synthesis\hydra_palace.sdc,palace_sdc" +VALUE "<project>\phy_synthesis\hydra_palace.v,palace_hdl" +VALUE "<project>\synthesis\rev_1\hydra.vm,syn_vm" +VALUE "<project>\synthesis\rev_1\hydra_sdc.sdc,syn_sdc" +ENDUsed_File_List +ENDLIST ENDLIST ENDLIST LIST ExcludePackageForSimulation @@ -846,22 +946,25 @@ ENDLIST ENDLIST LIST OpenedFileList ORIENTATION;HORIZONTAL -Constraint Manager;Constraint Manager;0 -HDL;constraint\timing.sdc;0 -HDL;hdl\axis_assert.vhd;0 -StartPage;StartPage;0 -HDL;constraint\io\m2s050_som.io.pdc;0 Reports;Reports;0 -ReportsCurrentItem;Synthesize:hydra_compile_netlist_resources.xml -HDL;hdl\axis_fifo_cdc.vhd;0 -HDL;constraint\fp\user.pdc;0 -HDL;hdl\urv_soc.vhd;0 -HDL;hdl\dpram_generic.vhd;0 +ReportsCurrentItem;Place and Route:hydra_layout_log.log +HDL;dependencies\wb_crossbar\wishbone_pkg.vhd;0 HDL;hdl\ueth_dma.vhd;0 -HDL;component\work\hydra\hydra.v;0 -HDL;hdl\reset_gen.vhd;0 +HDL;dependencies\wb_crossbar\xwb_crossbar.vhd;0 +HDL;hdl\ram_voter.vhd;0 +Constraint Manager;Constraint Manager;0 +HDL;hdl\urv_soc.vhd;0 +HDL;constraint\fp\user.pdc;0 +HDL;hdl\axis_fifo_cdc.vhd;0 +HDL;constraint\io\m2s050_som.io.pdc;0 +StartPage;StartPage;0 HDL;synthesis\hydra.srr;0 -ACTIVEVIEW;Constraint Manager +HDL;hdl\reset_gen.vhd;0 +HDL;component\work\hydra\hydra.v;0 +HDL;hdl\dpram_generic.vhd;0 +HDL;constraint\timing.sdc;0 +HDL;hdl\axis_assert.vhd;0 +ACTIVEVIEW;Reports ENDLIST LIST ModuleSubBlockList LIST "axis_assert::work","hdl\axis_assert.vhd","FALSE","FALSE" @@ -890,7 +993,7 @@ LIST "reset_gen::work","hdl\reset_gen.vhd","FALSE","FALSE" ENDLIST LIST "rst_filter::work","hdl\rst_filter.vhd","FALSE","FALSE" ENDLIST -LIST "sdb_rom::work::wishbone_pkg","G:\Users\r\rizzi\powerlink\wb_crossbar\sdb_rom.vhd","FALSE","FALSE" +LIST "sdb_rom::work::wishbone_pkg","dependencies\wb_crossbar\sdb_rom.vhd","FALSE","FALSE" ENDLIST LIST "sdpram_cdc_r::work","hdl\sdram_cdc_r.vhd","FALSE","FALSE" ENDLIST @@ -928,35 +1031,46 @@ LIST "urv_core_DTMR::work","hdl\urv_core_DTMR.vhd","FALSE","FALSE" SUBBLOCK "rst_filter::work","hdl\rst_filter.vhd","FALSE","FALSE" SUBBLOCK "secded_ecc::work","hdl\secded_ecc.vhd","FALSE","FALSE" SUBBLOCK "secded_ecc_daec::work","hdl\secded_ecc_daec.vhd","FALSE","FALSE" -SUBBLOCK "urv_cpu::work","G:\Users\r\rizzi\powerlink\urv-core-irq-patched\rtl\urv_cpu.v","FALSE","FALSE" +SUBBLOCK "urv_cpu::work","dependencies\urv-core\rtl\urv_cpu.v","FALSE","FALSE" ENDLIST -LIST "urv_cpu::work","G:\Users\r\rizzi\powerlink\urv-core-irq-patched\rtl\urv_cpu.v","FALSE","FALSE" -SUBBLOCK "urv_decode::work","G:\Users\r\rizzi\powerlink\urv-core-irq-patched\rtl\urv_decode.v","FALSE","FALSE" -SUBBLOCK "urv_exec::work","G:\Users\r\rizzi\powerlink\urv-core-irq-patched\rtl\urv_exec.v","FALSE","FALSE" -SUBBLOCK "urv_fetch::work","G:\Users\r\rizzi\powerlink\urv-core-irq-patched\rtl\urv_fetch.v","FALSE","FALSE" -SUBBLOCK "urv_regfile::work","G:\Users\r\rizzi\powerlink\urv-core-irq-patched\rtl\urv_regfile.v","FALSE","FALSE" -SUBBLOCK "urv_timer::work","G:\Users\r\rizzi\powerlink\urv-core-irq-patched\rtl\urv_timer.v","FALSE","FALSE" -SUBBLOCK "urv_writeback::work","G:\Users\r\rizzi\powerlink\urv-core-irq-patched\rtl\urv_writeback.v","FALSE","FALSE" +LIST "urv_cpu::work","dependencies\urv-core\rtl\urv_cpu.v","FALSE","FALSE" +SUBBLOCK "urv_decode::work","dependencies\urv-core\rtl\urv_decode.v","FALSE","FALSE" +SUBBLOCK "urv_exec::work","dependencies\urv-core\rtl\urv_exec.v","FALSE","FALSE" +SUBBLOCK "urv_fetch::work","dependencies\urv-core\rtl\urv_fetch.v","FALSE","FALSE" +SUBBLOCK "urv_regfile::work","dependencies\urv-core\rtl\urv_regfile.v","FALSE","FALSE" +SUBBLOCK "urv_timer::work","dependencies\urv-core\rtl\urv_timer.v","FALSE","FALSE" +SUBBLOCK "urv_writeback::work","dependencies\urv-core\rtl\urv_writeback.v","FALSE","FALSE" ENDLIST -LIST "urv_csr::work","G:\Users\r\rizzi\powerlink\urv-core-irq-patched\rtl\urv_csr.v","FALSE","FALSE" +LIST "urv_csr::work","dependencies\urv-core\rtl\urv_csr.v","FALSE","FALSE" ENDLIST -LIST "urv_decode::work","G:\Users\r\rizzi\powerlink\urv-core-irq-patched\rtl\urv_decode.v","FALSE","FALSE" +LIST "urv_debug::work","dependencies\urv-core\rtl\urv_debug.v","FALSE","FALSE" ENDLIST -LIST "urv_exceptions::work","G:\Users\r\rizzi\powerlink\urv-core-irq-patched\rtl\urv_exceptions.v","FALSE","FALSE" +LIST "urv_decode::work","dependencies\urv-core\rtl\urv_decode.v","FALSE","FALSE" ENDLIST -LIST "urv_exec::work","G:\Users\r\rizzi\powerlink\urv-core-irq-patched\rtl\urv_exec.v","FALSE","FALSE" -SUBBLOCK "urv_csr::work","G:\Users\r\rizzi\powerlink\urv-core-irq-patched\rtl\urv_csr.v","FALSE","FALSE" -SUBBLOCK "urv_exceptions::work","G:\Users\r\rizzi\powerlink\urv-core-irq-patched\rtl\urv_exceptions.v","FALSE","FALSE" -SUBBLOCK "urv_shifter::work","G:\Users\r\rizzi\powerlink\urv-core-irq-patched\rtl\urv_shifter.v","FALSE","FALSE" +LIST "urv_divide::work","dependencies\urv-core\rtl\urv_divide.v","FALSE","FALSE" ENDLIST -LIST "urv_fetch::work","G:\Users\r\rizzi\powerlink\urv-core-irq-patched\rtl\urv_fetch.v","FALSE","FALSE" +LIST "urv_exceptions::work","dependencies\urv-core\rtl\urv_exceptions.v","FALSE","FALSE" ENDLIST -LIST "urv_regfile::work","G:\Users\r\rizzi\powerlink\urv-core-irq-patched\rtl\urv_regfile.v","FALSE","FALSE" -SUBBLOCK "urv_regmem::work","G:\Users\r\rizzi\powerlink\urv-core-irq-patched\rtl\urv_regfile.v","FALSE","FALSE" +LIST "urv_exec::work","dependencies\urv-core\rtl\urv_exec.v","FALSE","FALSE" +SUBBLOCK "urv_csr::work","dependencies\urv-core\rtl\urv_csr.v","FALSE","FALSE" +SUBBLOCK "urv_exceptions::work","dependencies\urv-core\rtl\urv_exceptions.v","FALSE","FALSE" +SUBBLOCK "urv_shifter::work","dependencies\urv-core\rtl\urv_shifter.v","FALSE","FALSE" ENDLIST -LIST "urv_regmem::work","G:\Users\r\rizzi\powerlink\urv-core-irq-patched\rtl\urv_regfile.v","FALSE","FALSE" +LIST "urv_fetch::work","dependencies\urv-core\rtl\urv_fetch.v","FALSE","FALSE" ENDLIST -LIST "urv_shifter::work","G:\Users\r\rizzi\powerlink\urv-core-irq-patched\rtl\urv_shifter.v","FALSE","FALSE" +LIST "urv_iram::work","dependencies\urv-core\rtl\urv_iram.v","FALSE","FALSE" +ENDLIST +LIST "urv_mult18x18::work","dependencies\urv-core\rtl\urv_multiply.v","FALSE","FALSE" +ENDLIST +LIST "urv_multiply::work","dependencies\urv-core\rtl\urv_multiply.v","FALSE","FALSE" +SUBBLOCK "urv_mult18x18::work","dependencies\urv-core\rtl\urv_multiply.v","FALSE","FALSE" +ENDLIST +LIST "urv_regfile::work","dependencies\urv-core\rtl\urv_regfile.v","FALSE","FALSE" +SUBBLOCK "urv_regmem::work","dependencies\urv-core\rtl\urv_regfile.v","FALSE","FALSE" +ENDLIST +LIST "urv_regmem::work","dependencies\urv-core\rtl\urv_regfile.v","FALSE","FALSE" +ENDLIST +LIST "urv_shifter::work","dependencies\urv-core\rtl\urv_shifter.v","FALSE","FALSE" ENDLIST LIST "urv_soc::work","hdl\urv_soc.vhd","FALSE","FALSE" SUBBLOCK "dpram_generic::work","hdl\dpram_generic.vhd","FALSE","FALSE" @@ -969,7 +1083,7 @@ SUBBLOCK "urv_supervisor::work","hdl\urv_supervisor.vhd","FALSE","FALSE" SUBBLOCK "wb_envm::work","hdl\wb_envm.vhd","FALSE","FALSE" SUBBLOCK "wb_master_voter::work","hdl\wb_master_voter.vhd","FALSE","FALSE" SUBBLOCK "wb_slave_voter::work","hdl\wb_slave_voter.vhd","FALSE","FALSE" -SUBBLOCK "xwb_crossbar::work::wishbone_pkg","G:\Users\r\rizzi\powerlink\wb_crossbar\xwb_crossbar.vhd","FALSE","FALSE" +SUBBLOCK "xwb_crossbar::work::wishbone_pkg","dependencies\wb_crossbar\xwb_crossbar.vhd","FALSE","FALSE" SUBBLOCK "xwb_ram_adapter::work","hdl\xwb_ram_adapter.vhdl","FALSE","FALSE" SUBBLOCK "xwb_seu_regs::work","hdl\xwb_seu_reg.vhd","FALSE","FALSE" SUBBLOCK "xwb_uart::work","hdl\xwb_uart.vhd","FALSE","FALSE" @@ -978,9 +1092,9 @@ ENDLIST LIST "urv_supervisor::work","hdl\urv_supervisor.vhd","FALSE","FALSE" SUBBLOCK "xwb_supervisor_reg::work","hdl\xwb_supervisor_reg.vhd","FALSE","FALSE" ENDLIST -LIST "urv_timer::work","G:\Users\r\rizzi\powerlink\urv-core-irq-patched\rtl\urv_timer.v","FALSE","FALSE" +LIST "urv_timer::work","dependencies\urv-core\rtl\urv_timer.v","FALSE","FALSE" ENDLIST -LIST "urv_writeback::work","G:\Users\r\rizzi\powerlink\urv-core-irq-patched\rtl\urv_writeback.v","FALSE","FALSE" +LIST "urv_writeback::work","dependencies\urv-core\rtl\urv_writeback.v","FALSE","FALSE" ENDLIST LIST "voter::work","hdl\ram_voter.vhd","FALSE","FALSE" ENDLIST @@ -1008,7 +1122,7 @@ LIST "wb_simple_pwm::work","","FALSE","FALSE" ENDLIST LIST "wb_simple_uart::work","","FALSE","FALSE" ENDLIST -LIST "wb_skidpad::work::wishbone_pkg","G:\Users\r\rizzi\powerlink\wb_crossbar\wb_skidpad.vhd","FALSE","FALSE" +LIST "wb_skidpad::work::wishbone_pkg","dependencies\wb_crossbar\wb_skidpad.vhd","FALSE","FALSE" ENDLIST LIST "wb_slave_adapter::work","","FALSE","FALSE" ENDLIST @@ -1028,8 +1142,8 @@ LIST "wb_vic::work","","FALSE","FALSE" ENDLIST LIST "wd_regs::work","hdl\wb_wd_reg.vhdl","FALSE","FALSE" ENDLIST -LIST "wishbone_pkg::work","G:\Users\r\rizzi\powerlink\wb_crossbar\wishbone_pkg.vhd","FALSE","FALSE" -SUBBLOCK "sdb_rom::work::wishbone_pkg","G:\Users\r\rizzi\powerlink\wb_crossbar\sdb_rom.vhd","FALSE","FALSE" +LIST "wishbone_pkg::work","dependencies\wb_crossbar\wishbone_pkg.vhd","FALSE","FALSE" +SUBBLOCK "sdb_rom::work::wishbone_pkg","dependencies\wb_crossbar\sdb_rom.vhd","FALSE","FALSE" SUBBLOCK "wb_async_bridge::work","","FALSE","FALSE" SUBBLOCK "wb_gpio_port::work","","FALSE","FALSE" SUBBLOCK "wb_i2c_bridge::work","","FALSE","FALSE" @@ -1038,7 +1152,7 @@ SUBBLOCK "wb_onewire_master::work","","FALSE","FALSE" SUBBLOCK "wb_serial_lcd::work","","FALSE","FALSE" SUBBLOCK "wb_simple_pwm::work","","FALSE","FALSE" SUBBLOCK "wb_simple_uart::work","","FALSE","FALSE" -SUBBLOCK "wb_skidpad::work::wishbone_pkg","G:\Users\r\rizzi\powerlink\wb_crossbar\wb_skidpad.vhd","FALSE","FALSE" +SUBBLOCK "wb_skidpad::work::wishbone_pkg","dependencies\wb_crossbar\wb_skidpad.vhd","FALSE","FALSE" SUBBLOCK "wb_slave_adapter::work","","FALSE","FALSE" SUBBLOCK "wb_spi::work","","FALSE","FALSE" SUBBLOCK "wb_spi_flash::work","","FALSE","FALSE" @@ -1047,7 +1161,7 @@ SUBBLOCK "wb_vic::work","","FALSE","FALSE" SUBBLOCK "xwb_async_bridge::work","","FALSE","FALSE" SUBBLOCK "xwb_bus_fanout::work","","FALSE","FALSE" SUBBLOCK "xwb_clock_crossing::work","","FALSE","FALSE" -SUBBLOCK "xwb_crossbar::work::wishbone_pkg","G:\Users\r\rizzi\powerlink\wb_crossbar\xwb_crossbar.vhd","FALSE","FALSE" +SUBBLOCK "xwb_crossbar::work::wishbone_pkg","dependencies\wb_crossbar\xwb_crossbar.vhd","FALSE","FALSE" SUBBLOCK "xwb_dma::work","","FALSE","FALSE" SUBBLOCK "xwb_dpram::work","","FALSE","FALSE" SUBBLOCK "xwb_dpram_mixed::work","","FALSE","FALSE" @@ -1055,8 +1169,8 @@ SUBBLOCK "xwb_gpio_port::work","","FALSE","FALSE" SUBBLOCK "xwb_i2c_master::work","","FALSE","FALSE" SUBBLOCK "xwb_lm32::work","","FALSE","FALSE" SUBBLOCK "xwb_onewire_master::work","","FALSE","FALSE" -SUBBLOCK "xwb_register_link::work::wishbone_pkg","G:\Users\r\rizzi\powerlink\wb_crossbar\xwb_register_link.vhd","FALSE","FALSE" -SUBBLOCK "xwb_sdb_crossbar::work::wishbone_pkg","G:\Users\r\rizzi\powerlink\wb_crossbar\xwb_sdb_crossbar.vhd","FALSE","FALSE" +SUBBLOCK "xwb_register_link::work::wishbone_pkg","dependencies\wb_crossbar\xwb_register_link.vhd","FALSE","FALSE" +SUBBLOCK "xwb_sdb_crossbar::work::wishbone_pkg","dependencies\wb_crossbar\xwb_sdb_crossbar.vhd","FALSE","FALSE" SUBBLOCK "xwb_simple_pwm::work","","FALSE","FALSE" SUBBLOCK "xwb_simple_uart::work","","FALSE","FALSE" SUBBLOCK "xwb_spi::work","","FALSE","FALSE" @@ -1065,13 +1179,17 @@ SUBBLOCK "xwb_tics::work","","FALSE","FALSE" SUBBLOCK "xwb_vic::work","","FALSE","FALSE" SUBBLOCK "xwb_xil_multiboot::work","","FALSE","FALSE" ENDLIST +LIST "xurv_core::work","dependencies\urv-core\rtl\xurv_core.vhd","FALSE","FALSE" +SUBBLOCK "urv_cpu::work","dependencies\urv-core\rtl\urv_cpu.v","FALSE","FALSE" +SUBBLOCK "urv_iram::work","dependencies\urv-core\rtl\urv_iram.v","FALSE","FALSE" +ENDLIST LIST "xwb_async_bridge::work","","FALSE","FALSE" ENDLIST LIST "xwb_bus_fanout::work","","FALSE","FALSE" ENDLIST LIST "xwb_clock_crossing::work","","FALSE","FALSE" ENDLIST -LIST "xwb_crossbar::work::wishbone_pkg","G:\Users\r\rizzi\powerlink\wb_crossbar\xwb_crossbar.vhd","FALSE","FALSE" +LIST "xwb_crossbar::work::wishbone_pkg","dependencies\wb_crossbar\xwb_crossbar.vhd","FALSE","FALSE" ENDLIST LIST "xwb_dma::work","","FALSE","FALSE" ENDLIST @@ -1091,12 +1209,12 @@ LIST "xwb_ram_adapter::work","hdl\xwb_ram_adapter.vhdl","FALSE","FALSE" SUBBLOCK "secded_ecc::work","hdl\secded_ecc.vhd","FALSE","FALSE" SUBBLOCK "secded_ecc_daec::work","hdl\secded_ecc_daec.vhd","FALSE","FALSE" ENDLIST -LIST "xwb_register_link::work::wishbone_pkg","G:\Users\r\rizzi\powerlink\wb_crossbar\xwb_register_link.vhd","FALSE","FALSE" -SUBBLOCK "wb_skidpad::work::wishbone_pkg","G:\Users\r\rizzi\powerlink\wb_crossbar\wb_skidpad.vhd","FALSE","FALSE" +LIST "xwb_register_link::work::wishbone_pkg","dependencies\wb_crossbar\xwb_register_link.vhd","FALSE","FALSE" +SUBBLOCK "wb_skidpad::work::wishbone_pkg","dependencies\wb_crossbar\wb_skidpad.vhd","FALSE","FALSE" ENDLIST -LIST "xwb_sdb_crossbar::work::wishbone_pkg","G:\Users\r\rizzi\powerlink\wb_crossbar\xwb_sdb_crossbar.vhd","FALSE","FALSE" -SUBBLOCK "sdb_rom::work::wishbone_pkg","G:\Users\r\rizzi\powerlink\wb_crossbar\sdb_rom.vhd","FALSE","FALSE" -SUBBLOCK "xwb_crossbar::work::wishbone_pkg","G:\Users\r\rizzi\powerlink\wb_crossbar\xwb_crossbar.vhd","FALSE","FALSE" +LIST "xwb_sdb_crossbar::work::wishbone_pkg","dependencies\wb_crossbar\xwb_sdb_crossbar.vhd","FALSE","FALSE" +SUBBLOCK "sdb_rom::work::wishbone_pkg","dependencies\wb_crossbar\sdb_rom.vhd","FALSE","FALSE" +SUBBLOCK "xwb_crossbar::work::wishbone_pkg","dependencies\wb_crossbar\xwb_crossbar.vhd","FALSE","FALSE" ENDLIST LIST "xwb_seu_regs::work","hdl\xwb_seu_reg.vhd","FALSE","FALSE" SUBBLOCK "wb_seu_regs::work","hdl\wb_seu_reg.vhdl","FALSE","FALSE"