diff --git a/component/Actel/SmartFusion2MSS/MSS/1.1.500/MSS.cxf b/component/Actel/SmartFusion2MSS/MSS/1.1.500/MSS.cxf new file mode 100644 index 0000000000000000000000000000000000000000..3c189b99d95153730bd9d4bdf61a3a88ec9e32d4 --- /dev/null +++ b/component/Actel/SmartFusion2MSS/MSS/1.1.500/MSS.cxf @@ -0,0 +1 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>MSS</name><vendor>Actel</vendor><library>SmartFusion2MSS</library><version>1.1.500</version><fileSets><fileSet fileSetId="ANY_SIMULATION_FILESET"><file fileid="0"><name>peripheral_init.bfm</name><userFileType>BFM</userFileType></file></fileSet></fileSets><hwModel><views><view><fileSetRef>ANY_SIMULATION_FILESET</fileSetRef><name>SIMULATION</name></view><view><name>SYNTHESIS</name></view></views></hwModel></Component> \ No newline at end of file diff --git a/component/Actel/SmartFusion2MSS/MSS/1.1.500/peripheral_init.bfm b/component/Actel/SmartFusion2MSS/MSS/1.1.500/peripheral_init.bfm new file mode 100644 index 0000000000000000000000000000000000000000..156947a5bd2a34fb13209abdebbe943bd9223098 --- /dev/null +++ b/component/Actel/SmartFusion2MSS/MSS/1.1.500/peripheral_init.bfm @@ -0,0 +1,294 @@ +# ----------------------------------------------------------------------------- +# Top Level Initialization procedure +# +# Warning: Do not modify this file, it may lead to unexpected +# simulation failures in your Microcontroller Subsystem. +# +# ----------------------------------------------------------------------------- + +# ----------------------------------------------------------------------------- +# Registers Range +# ----------------------------------------------------------------------------- +# MDDR 0x40020000 - 0x40020FFF (starts at 0x40020800) +# FDDR 0x40021000 - 0x40021FFF +# Internal 0x40022000 - 0x40023FFF +# (Unused) 0x40024000 - 0x40027FFF +# SERDESIF_0 0x40028000 - 0x4002BFFF +# SERDESIF_1 0x4002C000 - 0x4002FFFF +# SERDESIF_2 0x40030000 - 0x40033FFF +# SERDESIF_3 0x40034000 - 0x40037FFF +# ----------------------------------------------------------------------------- + +# Initialization memory map +memmap MDDR 0x40020800; +memmap FDDR 0x40021000; +memmap SERDESIF_0 0x40028000; +memmap SERDESIF_1 0x4002C000; +memmap SERDESIF_2 0x40030000; +memmap SERDESIF_3 0x40034000; + +# CoreSF2Config memory map +memmap CORE_CONFIG_INTERNAL_REGISTERS 0x40022000; +constant STATUS_REG 0x4 + +# SERDES_IF_x memory map +constant LANE_0_PMA_STATUS 0x10C0 +constant LANE_1_PMA_STATUS 0x14C0 +constant LANE_2_PMA_STATUS 0x18C0 +constant LANE_3_PMA_STATUS 0x1CC0 +constant SYSTEM_SER_SOFT_RESET 0x2008 +constant SYSTEM_CONFIG_PHY_MODE_1 0x2028 + +#ifdef USE_MDDR +include "MDDR_init.bfm" +#endif +#ifdef USE_FDDR +include "FDDR_init.bfm" +#endif +#ifdef USE_SERDESIF_0 +include "SERDESIF_0_init.bfm" +#endif +#ifdef USE_SERDESIF_1 +include "SERDESIF_1_init.bfm" +#endif +#ifdef USE_SERDESIF_2 +include "SERDESIF_2_init.bfm" +#endif +#ifdef USE_SERDESIF_3 +include "SERDESIF_3_init.bfm" +#endif + +procedure init; + +int x_init_done; +int x_sdif_release; +int x_sdif0_pma; +int x_sdif0_pcie1_pma; +int x_sdif1_pma; +int x_sdif1_pcie1_pma; +int x_sdif2_pma; +int x_sdif2_pcie1_pma; +int x_sdif3_pma; +int x_sdif3_pcie1_pma; +int x_ser_soft_reset; +int x_ser_phy_mode_1; +int loop_sdif_release; +int loop_sdif0_pma; +int loop_sdif0_pcie1_pma; +int loop_sdif1_pma; +int loop_sdif1_pcie1_pma; +int loop_sdif2_pma; +int loop_sdif2_pcie1_pma; +int loop_sdif3_pma; +int loop_sdif3_pcie1_pma; +int loop_init_done; + +print "Start Initialization"; + +# --------------------------- +# Start Configuration phase 1 +# --------------------------- + +print "Start Register Configuration Phase 1"; + +#ifdef USE_MDDR +call MDDR_init; +#endif + +#ifdef USE_FDDR +call FDDR_init; +#endif + +#ifdef USE_SERDESIF_0 +call SERDESIF_0_init; +#endif + +#ifdef USE_SERDESIF_1 +call SERDESIF_1_init; +#endif + +#ifdef USE_SERDESIF_2 +call SERDESIF_2_init; +#endif + +#ifdef USE_SERDESIF_3 +call SERDESIF_3_init; +#endif + +# ------------------------------------------- +# End of configuration phase 1 (CONFIG1_DONE) +# ------------------------------------------- + +print "End Register Configuration Phase 1"; + +write w CORE_CONFIG_INTERNAL_REGISTERS 0x000 0x1; + +# ------------------------------------ +# If any SERDES, wait for SDIF_RELEASE +# ------------------------------------ + +print "Start Register Configuration Phase 2"; + +#ifdef USE_SERDESIF +set loop_sdif_release 1 +while loop_sdif_release + readstore b CORE_CONFIG_INTERNAL_REGISTERS STATUS_REG x_sdif_release + set x_sdif_release x_sdif_release & 0x02 + set loop_sdif_release x_sdif_release == 0 +endwhile +#endif + +# ----------------------------------------------------- +# Foreach SERDES with PCIE: +# - poll for PMA_READY (lane 0 for now) +# - write PCIE registers +# - issue a soft-reset to the PCIe controller +# PCIE_CTLR_SOFTRESET 0 (PCIe core for non-090, PCIE_0 for 090) +# PCIE2_CTLR_SOFTRESET 6 (PCIE_1 for 090) +# ----------------------------------------------------- + +#ifdef USE_SERDESIF_0_PCIE_0 + +readstore w SERDESIF_0 SYSTEM_CONFIG_PHY_MODE_1 x_ser_phy_mode_1 +set x_ser_phy_mode_1 x_ser_phy_mode_1 & 0xFFFFF0FF +set x_ser_phy_mode_1 x_ser_phy_mode_1 | SERDESIF_0_lane_x_cfg_phy_mode_1 +write w SERDESIF_0 SYSTEM_CONFIG_PHY_MODE_1 x_ser_phy_mode_1; + +set loop_sdif0_pma 1 +while loop_sdif0_pma + readstore b SERDESIF_0 SERDESIF_0_lane_x_pma_status x_sdif0_pma + set x_sdif0_pma x_sdif0_pma & 0x80 + set loop_sdif0_pma x_sdif0_pma == 0 +endwhile + +call SERDESIF_0_init_pcie; + +readstore w SERDESIF_0 SYSTEM_SER_SOFT_RESET x_ser_soft_reset +set x_ser_soft_reset x_ser_soft_reset & 0xFFFFFFFE +write w SERDESIF_0 SYSTEM_SER_SOFT_RESET x_ser_soft_reset; +set x_ser_soft_reset x_ser_soft_reset | 0x00000001 +write w SERDESIF_0 SYSTEM_SER_SOFT_RESET x_ser_soft_reset; + +#endif + +#ifdef USE_SERDESIF_0_PCIE_1 + +readstore w SERDESIF_0 SYSTEM_CONFIG_PHY_MODE_1 x_ser_phy_mode_1 +set x_ser_phy_mode_1 x_ser_phy_mode_1 & 0xFFFFF0FF +set x_ser_phy_mode_1 x_ser_phy_mode_1 | SERDESIF_0_pcie1_lane_x_cfg_phy_mode_1 +write w SERDESIF_0 SYSTEM_CONFIG_PHY_MODE_1 x_ser_phy_mode_1; + +set loop_sdif0_pcie1_pma 1 +while loop_sdif0_pcie1_pma + readstore b SERDESIF_0 SERDESIF_0_pcie1_lane_x_pma_status x_sdif0_pcie1_pma + set x_sdif0_pcie1_pma x_sdif0_pcie1_pma & 0x80 + set loop_sdif0_pcie1_pma x_sdif0_pcie1_pma == 0 +endwhile + +call SERDESIF_0_init_pcie1; + +readstore w SERDESIF_0 SYSTEM_SER_SOFT_RESET x_ser_soft_reset +set x_ser_soft_reset x_ser_soft_reset & 0xFFFFFFBF +write w SERDESIF_0 SYSTEM_SER_SOFT_RESET x_ser_soft_reset; +set x_ser_soft_reset x_ser_soft_reset | 0x00000040 +write w SERDESIF_0 SYSTEM_SER_SOFT_RESET x_ser_soft_reset; + +#endif + +#ifdef USE_SERDESIF_1_PCIE_0 + +readstore w SERDESIF_1 SYSTEM_CONFIG_PHY_MODE_1 x_ser_phy_mode_1 +set x_ser_phy_mode_1 x_ser_phy_mode_1 & 0xFFFFF0FF +set x_ser_phy_mode_1 x_ser_phy_mode_1 | SERDESIF_1_lane_x_cfg_phy_mode_1 +write w SERDESIF_1 SYSTEM_CONFIG_PHY_MODE_1 x_ser_phy_mode_1; + +set loop_sdif1_pma 1 +while loop_sdif1_pma + readstore b SERDESIF_1 SERDESIF_1_lane_x_pma_status x_sdif1_pma + set x_sdif1_pma x_sdif1_pma & 0x80 + set loop_sdif1_pma x_sdif1_pma == 0 +endwhile + +call SERDESIF_1_init_pcie; + +readstore w SERDESIF_1 SYSTEM_SER_SOFT_RESET x_ser_soft_reset +set x_ser_soft_reset x_ser_soft_reset & 0xFFFFFFFE +write w SERDESIF_1 SYSTEM_SER_SOFT_RESET x_ser_soft_reset; +set x_ser_soft_reset x_ser_soft_reset | 0x00000001 +write w SERDESIF_1 SYSTEM_SER_SOFT_RESET x_ser_soft_reset; + +#endif + +#ifdef USE_SERDESIF_2_PCIE_0 + +readstore w SERDESIF_2 SYSTEM_CONFIG_PHY_MODE_1 x_ser_phy_mode_1 +set x_ser_phy_mode_1 x_ser_phy_mode_1 & 0xFFFFF0FF +set x_ser_phy_mode_1 x_ser_phy_mode_1 | SERDESIF_2_lane_x_cfg_phy_mode_1 +write w SERDESIF_2 SYSTEM_CONFIG_PHY_MODE_1 x_ser_phy_mode_1; + +set loop_sdif2_pma 1 +while loop_sdif2_pma + readstore b SERDESIF_2 SERDESIF_2_lane_x_pma_status x_sdif2_pma + set x_sdif2_pma x_sdif2_pma & 0x80 + set loop_sdif2_pma x_sdif2_pma == 0 +endwhile + +call SERDESIF_2_init_pcie; + +readstore w SERDESIF_2 SYSTEM_SER_SOFT_RESET x_ser_soft_reset +set x_ser_soft_reset x_ser_soft_reset & 0xFFFFFFFE +write w SERDESIF_2 SYSTEM_SER_SOFT_RESET x_ser_soft_reset; +set x_ser_soft_reset x_ser_soft_reset | 0x00000001 +write w SERDESIF_2 SYSTEM_SER_SOFT_RESET x_ser_soft_reset; + +#endif + +#ifdef USE_SERDESIF_3_PCIE_0 + +readstore w SERDESIF_3 SYSTEM_CONFIG_PHY_MODE_1 x_ser_phy_mode_1 +set x_ser_phy_mode_1 x_ser_phy_mode_1 & 0xFFFFF0FF +set x_ser_phy_mode_1 x_ser_phy_mode_1 | SERDESIF_3_lane_x_cfg_phy_mode_1 +write w SERDESIF_3 SYSTEM_CONFIG_PHY_MODE_1 x_ser_phy_mode_1; + +set loop_sdif3_pma 1 +while loop_sdif3_pma + readstore b SERDESIF_3 SERDESIF_3_lane_x_pma_status x_sdif3_pma + set x_sdif3_pma x_sdif3_pma & 0x80 + set loop_sdif3_pma x_sdif3_pma == 0 +endwhile + +call SERDESIF_3_init_pcie; + +readstore w SERDESIF_3 SYSTEM_SER_SOFT_RESET x_ser_soft_reset +set x_ser_soft_reset x_ser_soft_reset & 0xFFFFFFFE +write w SERDESIF_3 SYSTEM_SER_SOFT_RESET x_ser_soft_reset; +set x_ser_soft_reset x_ser_soft_reset | 0x00000001 +write w SERDESIF_3 SYSTEM_SER_SOFT_RESET x_ser_soft_reset; + +#endif + +# ------------------------------------------- +# End of configuration phase 2 (CONFIG2_DONE) +# ------------------------------------------- + +print "End Register Configuration Phase 2"; + +write w CORE_CONFIG_INTERNAL_REGISTERS 0x000 0x3; + +# ----------------------------------------------------- +# Wait until INIT_DONE +# ----------------------------------------------------- + +print "Wait until INIT_DONE"; + +set loop_init_done 1 +while loop_init_done + readstore b CORE_CONFIG_INTERNAL_REGISTERS STATUS_REG x_init_done + set x_init_done x_init_done & 0x01 + set loop_init_done x_init_done == 0 +endwhile + +print "End Initialization"; + +return + diff --git a/component/Actel/SmartFusion2MSS/MSS_CC/1.0.100/MSS_CC.cxf b/component/Actel/SmartFusion2MSS/MSS_CC/1.0.100/MSS_CC.cxf new file mode 100644 index 0000000000000000000000000000000000000000..6bf0c4799f4e253b6e3702d8f69667653b724337 --- /dev/null +++ b/component/Actel/SmartFusion2MSS/MSS_CC/1.0.100/MSS_CC.cxf @@ -0,0 +1 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>MSS_CC</name><vendor>Actel</vendor><library>SmartFusion2MSS</library><version>1.0.100</version><fileSets/><hwModel><views/></hwModel></Component> \ No newline at end of file diff --git a/component/Actel/SmartFusion2MSS/MSS_CCC/1.0.100/MSS_CCC.cxf b/component/Actel/SmartFusion2MSS/MSS_CCC/1.0.100/MSS_CCC.cxf new file mode 100644 index 0000000000000000000000000000000000000000..5ea88d21fdea5f353a284de1ab6a539a77ca6281 --- /dev/null +++ b/component/Actel/SmartFusion2MSS/MSS_CCC/1.0.100/MSS_CCC.cxf @@ -0,0 +1 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>MSS_CCC</name><vendor>Actel</vendor><library>SmartFusion2MSS</library><version>1.0.100</version><fileSets/><hwModel><views/></hwModel></Component> \ No newline at end of file diff --git a/component/Actel/SmartFusion2MSS/MSS_CFGM/1.1.100/MSS_CFGM.cxf b/component/Actel/SmartFusion2MSS/MSS_CFGM/1.1.100/MSS_CFGM.cxf new file mode 100644 index 0000000000000000000000000000000000000000..acf1623340ea5dba1111757e5095017a25da20e2 --- /dev/null +++ b/component/Actel/SmartFusion2MSS/MSS_CFGM/1.1.100/MSS_CFGM.cxf @@ -0,0 +1 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>MSS_CFGM</name><vendor>Actel</vendor><library>SmartFusion2MSS</library><version>1.1.100</version><fileSets/><hwModel><views/></hwModel></Component> \ No newline at end of file diff --git a/component/Actel/SmartFusion2MSS/MSS_CM3/1.0.200/MSS_CM3.cxf b/component/Actel/SmartFusion2MSS/MSS_CM3/1.0.200/MSS_CM3.cxf new file mode 100644 index 0000000000000000000000000000000000000000..84ae0db3bb9362a2409499ae6c679867b879ca87 --- /dev/null +++ b/component/Actel/SmartFusion2MSS/MSS_CM3/1.0.200/MSS_CM3.cxf @@ -0,0 +1 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>MSS_CM3</name><vendor>Actel</vendor><library>SmartFusion2MSS</library><version>1.0.200</version><fileSets/><hwModel><views/></hwModel></Component> \ No newline at end of file diff --git a/component/Actel/SmartFusion2MSS/MSS_DDRB/1.0.200/MSS_DDRB.cxf b/component/Actel/SmartFusion2MSS/MSS_DDRB/1.0.200/MSS_DDRB.cxf new file mode 100644 index 0000000000000000000000000000000000000000..647b6229792e1b3345d32faaec6bfa2529152394 --- /dev/null +++ b/component/Actel/SmartFusion2MSS/MSS_DDRB/1.0.200/MSS_DDRB.cxf @@ -0,0 +1 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>MSS_DDRB</name><vendor>Actel</vendor><library>SmartFusion2MSS</library><version>1.0.200</version><fileSets/><hwModel><views/></hwModel></Component> \ No newline at end of file diff --git a/component/Actel/SmartFusion2MSS/MSS_EDAC/1.0.101/MSS_EDAC.cxf b/component/Actel/SmartFusion2MSS/MSS_EDAC/1.0.101/MSS_EDAC.cxf new file mode 100644 index 0000000000000000000000000000000000000000..60c85145d95ea79a60b0ddbaffc45804f2519781 --- /dev/null +++ b/component/Actel/SmartFusion2MSS/MSS_EDAC/1.0.101/MSS_EDAC.cxf @@ -0,0 +1 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>MSS_EDAC</name><vendor>Actel</vendor><library>SmartFusion2MSS</library><version>1.0.101</version><fileSets/><hwModel><views/></hwModel></Component> \ No newline at end of file diff --git a/component/Actel/SmartFusion2MSS/MSS_ENVM/1.0.101/MSS_ENVM.cxf b/component/Actel/SmartFusion2MSS/MSS_ENVM/1.0.101/MSS_ENVM.cxf new file mode 100644 index 0000000000000000000000000000000000000000..eb3ee45ad0289107262230eacdca7f92e551d543 --- /dev/null +++ b/component/Actel/SmartFusion2MSS/MSS_ENVM/1.0.101/MSS_ENVM.cxf @@ -0,0 +1 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>MSS_ENVM</name><vendor>Actel</vendor><library>SmartFusion2MSS</library><version>1.0.101</version><fileSets/><hwModel><views/></hwModel></Component> \ No newline at end of file diff --git a/component/Actel/SmartFusion2MSS/MSS_FIC32/1.0.100/MSS_FIC32.cxf b/component/Actel/SmartFusion2MSS/MSS_FIC32/1.0.100/MSS_FIC32.cxf new file mode 100644 index 0000000000000000000000000000000000000000..0014de3ff2da1186fcf8b179a2782d79b829c0e6 --- /dev/null +++ b/component/Actel/SmartFusion2MSS/MSS_FIC32/1.0.100/MSS_FIC32.cxf @@ -0,0 +1 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>MSS_FIC32</name><vendor>Actel</vendor><library>SmartFusion2MSS</library><version>1.0.100</version><fileSets/><hwModel><views/></hwModel></Component> \ No newline at end of file diff --git a/component/Actel/SmartFusion2MSS/MSS_INTR/1.0.200/MSS_INTR.cxf b/component/Actel/SmartFusion2MSS/MSS_INTR/1.0.200/MSS_INTR.cxf new file mode 100644 index 0000000000000000000000000000000000000000..1cdec6e17f62820de0ba315ab04d9997b2686498 --- /dev/null +++ b/component/Actel/SmartFusion2MSS/MSS_INTR/1.0.200/MSS_INTR.cxf @@ -0,0 +1 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>MSS_INTR</name><vendor>Actel</vendor><library>SmartFusion2MSS</library><version>1.0.200</version><fileSets/><hwModel><views/></hwModel></Component> \ No newline at end of file diff --git a/component/Actel/SmartFusion2MSS/MSS_RESET/1.0.100/MSS_RESET.cxf b/component/Actel/SmartFusion2MSS/MSS_RESET/1.0.100/MSS_RESET.cxf new file mode 100644 index 0000000000000000000000000000000000000000..9e3a462bffc4bd0ec7d5da747c04cfe946ef48b6 --- /dev/null +++ b/component/Actel/SmartFusion2MSS/MSS_RESET/1.0.100/MSS_RESET.cxf @@ -0,0 +1 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>MSS_RESET</name><vendor>Actel</vendor><library>SmartFusion2MSS</library><version>1.0.100</version><fileSets/><hwModel><views/></hwModel></Component> \ No newline at end of file diff --git a/component/Actel/SmartFusion2MSS/MSS_RTC/1.0.201/MSS_RTC.cxf b/component/Actel/SmartFusion2MSS/MSS_RTC/1.0.201/MSS_RTC.cxf new file mode 100644 index 0000000000000000000000000000000000000000..bf5634103a9675fea23ba0f1cc4f71bb41cfaba7 --- /dev/null +++ b/component/Actel/SmartFusion2MSS/MSS_RTC/1.0.201/MSS_RTC.cxf @@ -0,0 +1 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>MSS_RTC</name><vendor>Actel</vendor><library>SmartFusion2MSS</library><version>1.0.201</version><fileSets/><hwModel><views/></hwModel></Component> \ No newline at end of file diff --git a/component/Actel/SmartFusion2MSS/MSS_SECURITY/1.0.100/MSS_SECURITY.cxf b/component/Actel/SmartFusion2MSS/MSS_SECURITY/1.0.100/MSS_SECURITY.cxf new file mode 100644 index 0000000000000000000000000000000000000000..3d11115adecaad4c91aa162211a33f5ddb9ef21d --- /dev/null +++ b/component/Actel/SmartFusion2MSS/MSS_SECURITY/1.0.100/MSS_SECURITY.cxf @@ -0,0 +1 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>MSS_SECURITY</name><vendor>Actel</vendor><library>SmartFusion2MSS</library><version>1.0.100</version><fileSets/><hwModel><views/></hwModel></Component> \ No newline at end of file diff --git a/component/Actel/SmartFusion2MSS/MSS_SWITCH/1.0.101/MSS_SWITCH.cxf b/component/Actel/SmartFusion2MSS/MSS_SWITCH/1.0.101/MSS_SWITCH.cxf new file mode 100644 index 0000000000000000000000000000000000000000..b53940ba303c74c4c13f0895eaf8d9c335051ac2 --- /dev/null +++ b/component/Actel/SmartFusion2MSS/MSS_SWITCH/1.0.101/MSS_SWITCH.cxf @@ -0,0 +1 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>MSS_SWITCH</name><vendor>Actel</vendor><library>SmartFusion2MSS</library><version>1.0.101</version><fileSets/><hwModel><views/></hwModel></Component> \ No newline at end of file diff --git a/component/User/Private/urv_soc/1.0/urv_soc.xml b/component/User/Private/urv_soc/1.0/urv_soc.xml new file mode 100644 index 0000000000000000000000000000000000000000..9c2a5ca26cf4322bc944a6c24289f8ea2a65640a --- /dev/null +++ b/component/User/Private/urv_soc/1.0/urv_soc.xml @@ -0,0 +1,180 @@ +<spirit:component xmlns:actel-cc="http://www.actel.com/XMLSchema/CoreConsole" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.1 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.1/component.xsd"> + <spirit:vendor>User</spirit:vendor> + <spirit:library>Private</spirit:library> + <spirit:name>urv_soc</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>BIF_1</spirit:name> + <spirit:busType spirit:vendor="AMBA" spirit:library="AMBA2" spirit:name="APB" spirit:version="r0p0"/> + <spirit:master></spirit:master> + <spirit:signalMap> + <spirit:signalName> + <spirit:componentSignalName>apb_paddr_o</spirit:componentSignalName><spirit:busSignalName>PADDR</spirit:busSignalName></spirit:signalName> + <spirit:signalName> + <spirit:componentSignalName>apb_psel_o</spirit:componentSignalName><spirit:busSignalName>PSELx</spirit:busSignalName></spirit:signalName> + <spirit:signalName> + <spirit:componentSignalName>apb_pen_o</spirit:componentSignalName><spirit:busSignalName>PENABLE</spirit:busSignalName></spirit:signalName> + <spirit:signalName> + <spirit:componentSignalName>apb_pwr_o</spirit:componentSignalName><spirit:busSignalName>PWRITE</spirit:busSignalName></spirit:signalName> + <spirit:signalName> + <spirit:componentSignalName>apb_pready_i</spirit:componentSignalName><spirit:busSignalName>PRDATA</spirit:busSignalName></spirit:signalName> + <spirit:signalName> + <spirit:componentSignalName>apb_pwdat_o</spirit:componentSignalName><spirit:busSignalName>PWDATA</spirit:busSignalName></spirit:signalName> + <spirit:signalName> + <spirit:componentSignalName>apb_prdat_i</spirit:componentSignalName><spirit:busSignalName>PREADY</spirit:busSignalName></spirit:signalName></spirit:signalMap> + <spirit:vendorExtensions></spirit:vendorExtensions> + </spirit:busInterface> + </spirit:busInterfaces> + <spirit:memoryMaps> + </spirit:memoryMaps> + <spirit:hwModel> + <spirit:views> + </spirit:views> + <spirit:signals> + <spirit:signal> + <spirit:name>clk_i</spirit:name> + <spirit:direction>in</spirit:direction> + </spirit:signal> + <spirit:signal> + <spirit:name>clk_ram_i</spirit:name> + <spirit:direction>in</spirit:direction> + <spirit:left>39</spirit:left> + <spirit:right>0</spirit:right> + </spirit:signal> + <spirit:signal> + <spirit:name>rst_i</spirit:name> + <spirit:direction>in</spirit:direction> + </spirit:signal> + <spirit:signal> + <spirit:name>DEVRST_I</spirit:name> + <spirit:direction>in</spirit:direction> + </spirit:signal> + <spirit:signal> + <spirit:name>apb_psel_o</spirit:name> + <spirit:direction>out</spirit:direction> + </spirit:signal> + <spirit:signal> + <spirit:name>apb_pwr_o</spirit:name> + <spirit:direction>out</spirit:direction> + </spirit:signal> + <spirit:signal> + <spirit:name>apb_pen_o</spirit:name> + <spirit:direction>out</spirit:direction> + </spirit:signal> + <spirit:signal> + <spirit:name>apb_paddr_o</spirit:name> + <spirit:direction>out</spirit:direction> + <spirit:left>31</spirit:left> + <spirit:right>0</spirit:right> + </spirit:signal> + <spirit:signal> + <spirit:name>apb_pwdat_o</spirit:name> + <spirit:direction>out</spirit:direction> + <spirit:left>31</spirit:left> + <spirit:right>0</spirit:right> + </spirit:signal> + <spirit:signal> + <spirit:name>apb_prdat_i</spirit:name> + <spirit:direction>in</spirit:direction> + <spirit:left>31</spirit:left> + <spirit:right>0</spirit:right> + </spirit:signal> + <spirit:signal> + <spirit:name>apb_pready_i</spirit:name> + <spirit:direction>in</spirit:direction> + </spirit:signal> + <spirit:signal> + <spirit:name>apb_pslverr_i</spirit:name> + <spirit:direction>in</spirit:direction> + </spirit:signal> + <spirit:signal> + <spirit:name>uart_tx_o</spirit:name> + <spirit:direction>out</spirit:direction> + </spirit:signal> + <spirit:signal> + <spirit:name>eth_tx_clk_i</spirit:name> + <spirit:direction>in</spirit:direction> + </spirit:signal> + <spirit:signal> + <spirit:name>eth_txd_o</spirit:name> + <spirit:direction>out</spirit:direction> + <spirit:left>3</spirit:left> + <spirit:right>0</spirit:right> + </spirit:signal> + <spirit:signal> + <spirit:name>eth_txen_o</spirit:name> + <spirit:direction>out</spirit:direction> + </spirit:signal> + <spirit:signal> + <spirit:name>eth_txerr_o</spirit:name> + <spirit:direction>out</spirit:direction> + </spirit:signal> + <spirit:signal> + <spirit:name>eth_rx_clk_i</spirit:name> + <spirit:direction>in</spirit:direction> + </spirit:signal> + <spirit:signal> + <spirit:name>eth_rxd_i</spirit:name> + <spirit:direction>in</spirit:direction> + <spirit:left>3</spirit:left> + <spirit:right>0</spirit:right> + </spirit:signal> + <spirit:signal> + <spirit:name>eth_rxdv_i</spirit:name> + <spirit:direction>in</spirit:direction> + </spirit:signal> + <spirit:signal> + <spirit:name>eth_rxerr_i</spirit:name> + <spirit:direction>in</spirit:direction> + </spirit:signal> + <spirit:signal> + <spirit:name>eth_mdc_o</spirit:name> + <spirit:direction>out</spirit:direction> + </spirit:signal> + <spirit:signal> + <spirit:name>eth_md_i</spirit:name> + <spirit:direction>in</spirit:direction> + </spirit:signal> + <spirit:signal> + <spirit:name>eth_md_o</spirit:name> + <spirit:direction>out</spirit:direction> + </spirit:signal> + <spirit:signal> + <spirit:name>eth_oe_o</spirit:name> + <spirit:direction>out</spirit:direction> + </spirit:signal> + <spirit:signal> + <spirit:name>eth_rst_o</spirit:name> + <spirit:direction>out</spirit:direction> + </spirit:signal> + <spirit:signal> + <spirit:name>reboot_o</spirit:name> + <spirit:direction>out</spirit:direction> + </spirit:signal> + </spirit:signals> + <spirit:hwParameters> + </spirit:hwParameters> + </spirit:hwModel> + <spirit:choices> + </spirit:choices> + <spirit:fileSets> + <spirit:fileSet spirit:fileSetId="HDL_FILESET"> + <spirit:file> + <spirit:name>hdl/urv_soc.vhd</spirit:name> + <spirit:fileType>verilogSource</spirit:fileType> + <spirit:vendorExtensions></spirit:vendorExtensions> + </spirit:file> + <spirit:vendorExtensions></spirit:vendorExtensions> + </spirit:fileSet> + </spirit:fileSets> + <spirit:vendorExtensions> + <actel-cc:type typeName="IP"/> + <actel-cc:instantiateOnCreation value="false"/> + <actel-cc:diveInPermission value="READ_WRITE"/> + <actel-cc:categories categoryName="OS" style="hidden"> + <actel-cc:category name="PC"> + </actel-cc:category> + </actel-cc:categories> + </spirit:vendorExtensions> +</spirit:component>