From 8c18f977cb58a2944d1e4c8ae88e330f9c365890 Mon Sep 17 00:00:00 2001 From: Mattia Rizzi <mattia.rizzi@cern.ch> Date: Mon, 14 Dec 2020 14:52:40 +0100 Subject: [PATCH] Fixed missing module --- hydra.prjx | 272 ++++++++++++++++++++++++++++------------------------- 1 file changed, 145 insertions(+), 127 deletions(-) diff --git a/hydra.prjx b/hydra.prjx index 4aff430..8fb2a43 100644 --- a/hydra.prjx +++ b/hydra.prjx @@ -31,7 +31,7 @@ KEY VendorTechnology_VCCI_1.8_VOLTR "COM" KEY VendorTechnology_VCCI_2.5_VOLTR "COM" KEY VendorTechnology_VCCI_3.3_VOLTR "COM" KEY VendorTechnology_VOLTR "IND" -KEY ProjectLocation "C:\Users\mattia\Desktop\urv-core-rad\final-design\hydra" +KEY ProjectLocation "C:\Users\mattia\Downloads\hydra-master (4)\hydra-master" KEY ProjectDescription "" KEY Pa4PeripheralNewSeq "GOOD" KEY SimulationType "VERILOG" @@ -40,120 +40,121 @@ KEY ActiveRoot "hydra::work" LIST REVISIONS VALUE="Impl1",NUM=1 VALUE="Impl2",NUM=2 -CURREV=2 +VALUE="Impl3",NUM=3 +CURREV=3 ENDLIST LIST FileManager VALUE "<project>\component\Actel\SmartFusion2MSS\MSS\1.1.500\MSS.cxf,actgen_cxf" STATE="utd" -TIME="1607422610" +TIME="1607943296" SIZE="526" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" ENDFILE VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_CCC\1.0.100\MSS_CCC.cxf,actgen_cxf" STATE="utd" -TIME="1607422603" +TIME="1607943296" SIZE="253" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" ENDFILE VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_CC\1.0.100\MSS_CC.cxf,actgen_cxf" STATE="utd" -TIME="1607422603" +TIME="1607943296" SIZE="252" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" ENDFILE VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_CFGM\1.1.100\MSS_CFGM.cxf,actgen_cxf" STATE="utd" -TIME="1607422603" +TIME="1607943297" SIZE="254" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" ENDFILE VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_CM3\1.0.200\MSS_CM3.cxf,actgen_cxf" STATE="utd" -TIME="1607422603" +TIME="1607943297" SIZE="253" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" ENDFILE VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_DDRB\1.0.200\MSS_DDRB.cxf,actgen_cxf" STATE="utd" -TIME="1607422603" +TIME="1607943297" SIZE="254" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" ENDFILE VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_EDAC\1.0.101\MSS_EDAC.cxf,actgen_cxf" STATE="utd" -TIME="1607422603" +TIME="1607943297" SIZE="254" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" ENDFILE VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_ENVM\1.0.101\MSS_ENVM.cxf,actgen_cxf" STATE="utd" -TIME="1607422603" +TIME="1607943297" SIZE="254" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" ENDFILE VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_FIC32\1.0.100\MSS_FIC32.cxf,actgen_cxf" STATE="utd" -TIME="1607422603" +TIME="1607943297" SIZE="255" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" ENDFILE VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_INTR\1.0.200\MSS_INTR.cxf,actgen_cxf" STATE="utd" -TIME="1607422603" +TIME="1607943297" SIZE="254" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" ENDFILE VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_RESET\1.0.100\MSS_RESET.cxf,actgen_cxf" STATE="utd" -TIME="1607422603" +TIME="1607943297" SIZE="255" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" ENDFILE VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_RTC\1.0.201\MSS_RTC.cxf,actgen_cxf" STATE="utd" -TIME="1607422603" +TIME="1607943297" SIZE="253" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" ENDFILE VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_SECURITY\1.0.100\MSS_SECURITY.cxf,actgen_cxf" STATE="utd" -TIME="1607422603" +TIME="1607943297" SIZE="258" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" ENDFILE VALUE "<project>\component\Actel\SmartFusion2MSS\MSS_SWITCH\1.0.101\MSS_SWITCH.cxf,actgen_cxf" STATE="utd" -TIME="1607422603" +TIME="1607943297" SIZE="256" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" ENDFILE VALUE "<project>\component\work\hydra\hydra.cxf,actgen_cxf" STATE="utd" -TIME="1607435680" +TIME="1607943297" SIZE="4639" ENDFILE VALUE "<project>\component\work\hydra\hydra.v,hdl" STATE="utd" -TIME="1607435679" +TIME="1607943297" SIZE="8204" PARENT="<project>\component\work\hydra\hydra.cxf" IS_READONLY="TRUE" ENDFILE VALUE "<project>\component\work\hydra_MSS\hydra_MSS.cxf,actgen_cxf" STATE="utd" -TIME="1607422611" +TIME="1607943298" SIZE="11844" ENDFILE VALUE "<project>\component\work\hydra_MSS\hydra_MSS.v,hdl" STATE="utd" -TIME="1607422610" +TIME="1607943298" SIZE="48497" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" IS_READONLY="TRUE" ENDFILE VALUE "<project>\component\work\hydra_MSS\hydra_MSS_pre.v,hdl" STATE="utd" -TIME="1607422609" +TIME="1607943298" SIZE="64284" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" BEGIN_USE_CONSTRAINT @@ -165,7 +166,7 @@ IS_READONLY="TRUE" ENDFILE VALUE "<project>\component\work\hydra_MSS\hydra_MSS_pre.vhd,hdl" STATE="utd" -TIME="1606772857" +TIME="1607943298" SIZE="80667" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" BEGIN_USE_CONSTRAINT @@ -177,7 +178,7 @@ IS_READONLY="TRUE" ENDFILE VALUE "<project>\component\work\hydra_MSS\hydra_MSS_syn.v,hdl" STATE="utd" -TIME="1607422609" +TIME="1607943298" SIZE="56527" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" BEGIN_USE_CONSTRAINT @@ -189,265 +190,255 @@ IS_READONLY="TRUE" ENDFILE VALUE "<project>\constraint\fp\user.pdc,fp_pdc" STATE="utd" -TIME="1606837432" +TIME="1607943298" SIZE="891" IS_TARGET="TRUE" ENDFILE VALUE "<project>\constraint\io\m2s050_som.io.pdc,io_pdc" STATE="utd" -TIME="1606818694" +TIME="1607943298" SIZE="3087" ENDFILE VALUE "<project>\constraint\timing.sdc,sdc" STATE="utd" -TIME="1606769924" +TIME="1607943298" SIZE="2151" ENDFILE -VALUE "<project>\designer\impl2\hydra.ide_des,ide_des" +VALUE "<project>\designer\impl3\hydra.ide_des,ide_des" STATE="utd" -TIME="1607015706" -SIZE="404" +TIME="1607943329" +SIZE="212" ENDFILE VALUE "<project>\hdl\axis_assert.vhd,hdl" STATE="utd" -TIME="1583233333" +TIME="1607943299" SIZE="5469" ENDFILE VALUE "<project>\hdl\axis_fifo_cdc.vhd,hdl" STATE="utd" -TIME="1569832340" +TIME="1607943299" SIZE="12441" ENDFILE VALUE "<project>\hdl\clock_buffer.vhd,hdl" STATE="utd" -TIME="1607430744" +TIME="1607943299" SIZE="1021" ENDFILE VALUE "<project>\hdl\dpram_generic.vhd,hdl" STATE="utd" -TIME="1607442917" -SIZE="12876" +TIME="1607943299" +SIZE="12853" ENDFILE VALUE "<project>\hdl\ram_voter.vhd,hdl" STATE="utd" -TIME="1563289215" +TIME="1607943299" SIZE="2129" ENDFILE VALUE "<project>\hdl\reset_gen.vhd,hdl" STATE="utd" -TIME="1607425407" +TIME="1607943299" SIZE="1664" ENDFILE VALUE "<project>\hdl\rst_filter.vhd,hdl" STATE="utd" -TIME="1570774742" +TIME="1607943299" SIZE="866" ENDFILE VALUE "<project>\hdl\sdram_cdc_r.vhd,hdl" STATE="utd" -TIME="1563881401" +TIME="1607943299" SIZE="1664" ENDFILE VALUE "<project>\hdl\secded_ecc.vhd,hdl" STATE="utd" -TIME="1607432749" +TIME="1607943299" SIZE="12912" ENDFILE VALUE "<project>\hdl\secded_ecc_daec.vhd,hdl" STATE="utd" -TIME="1570772004" +TIME="1607943299" SIZE="17193" ENDFILE VALUE "<project>\hdl\seu_counters.vhd,hdl" STATE="utd" -TIME="1561992949" +TIME="1607943299" SIZE="2092" ENDFILE VALUE "<project>\hdl\uart.v,hdl" STATE="utd" -TIME="1593365548" +TIME="1607943299" SIZE="2316" ENDFILE VALUE "<project>\hdl\ueth.vhd,hdl" STATE="utd" -TIME="1588249797" +TIME="1607943299" SIZE="4891" ENDFILE VALUE "<project>\hdl\ueth_crc.vhd,hdl" STATE="utd" -TIME="1593367576" +TIME="1607943299" SIZE="3177" ENDFILE VALUE "<project>\hdl\ueth_dma.vhd,hdl" STATE="utd" -TIME="1605105818" +TIME="1607943299" SIZE="19463" ENDFILE VALUE "<project>\hdl\ueth_hub.vhd,hdl" STATE="utd" -TIME="1593367593" +TIME="1607943300" SIZE="7485" ENDFILE VALUE "<project>\hdl\ueth_mac.vhd,hdl" STATE="utd" -TIME="1593367918" +TIME="1607943300" SIZE="15827" ENDFILE VALUE "<project>\hdl\ueth_miim.vhd,hdl" STATE="utd" -TIME="1607451522" +TIME="1607943300" SIZE="5655" ENDFILE VALUE "<project>\hdl\ueth_uphy.vhd,hdl" STATE="utd" -TIME="1593367542" +TIME="1607943300" SIZE="4713" ENDFILE VALUE "<project>\hdl\urv_core_DTMR.vhd,hdl" STATE="utd" -TIME="1593348949" +TIME="1607943300" SIZE="13440" ENDFILE VALUE "<project>\hdl\urv_soc.vhd,hdl" STATE="utd" -TIME="1607435517" +TIME="1607943300" SIZE="30808" ENDFILE VALUE "<project>\hdl\urv_supervisor.vhd,hdl" STATE="utd" -TIME="1604492687" +TIME="1607943300" SIZE="4646" ENDFILE VALUE "<project>\hdl\wb_envm.vhd,hdl" STATE="utd" -TIME="1604860502" +TIME="1607943300" SIZE="7675" ENDFILE VALUE "<project>\hdl\wb_master_voter.vhd,hdl" STATE="utd" -TIME="1592922124" +TIME="1607943300" SIZE="1685" ENDFILE VALUE "<project>\hdl\wb_seu_reg.vhdl,hdl" STATE="utd" -TIME="1561622710" +TIME="1607943300" SIZE="4684" ENDFILE VALUE "<project>\hdl\wb_slave_voter.vhd,hdl" STATE="utd" -TIME="1592922113" +TIME="1607943300" SIZE="1154" ENDFILE VALUE "<project>\hdl\wb_uart.vhdl,hdl" STATE="utd" -TIME="1592921902" +TIME="1607943300" SIZE="7444" ENDFILE VALUE "<project>\hdl\wb_wd_reg.vhdl,hdl" STATE="utd" -TIME="1564131777" +TIME="1607943300" SIZE="5376" ENDFILE VALUE "<project>\hdl\xwb_ram_adapter.vhdl,hdl" STATE="utd" -TIME="1605105986" +TIME="1607943300" SIZE="8791" ENDFILE VALUE "<project>\hdl\xwb_seu_reg.vhd,hdl" STATE="utd" -TIME="1593367659" +TIME="1607943300" SIZE="3180" ENDFILE VALUE "<project>\hdl\xwb_supervisor_reg.vhd,hdl" STATE="utd" -TIME="1604492831" +TIME="1607943300" SIZE="2854" ENDFILE VALUE "<project>\hdl\xwb_uart.vhd,hdl" STATE="utd" -TIME="1593367672" +TIME="1607943301" SIZE="2888" ENDFILE VALUE "<project>\hdl\xwb_wd_reg.vhd,hdl" STATE="utd" -TIME="1593367680" +TIME="1607943301" SIZE="2215" ENDFILE VALUE "<project>\simulation\CM3_compile_bfm.tcl,sim" STATE="utd" -TIME="1607422609" +TIME="1607943298" SIZE="500" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" ENDFILE VALUE "<project>\simulation\peripheral_init.bfm,sim" STATE="utd" -TIME="1566480149" +TIME="1607943296" SIZE="8450" PARENT="<project>\component\Actel\SmartFusion2MSS\MSS\1.1.500\MSS.cxf" ENDFILE VALUE "<project>\simulation\subsystem.bfm,sim" STATE="utd" -TIME="1607435679" +TIME="1607943298" SIZE="602" PARENT="<project>\component\work\hydra\hydra.cxf" ENDFILE VALUE "<project>\simulation\test.bfm,sim" STATE="utd" -TIME="1607422609" +TIME="1607943298" SIZE="734" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" ENDFILE VALUE "<project>\simulation\user.bfm,sim" STATE="utd" -TIME="1606762191" +TIME="1607943298" SIZE="555" PARENT="<project>\component\work\hydra_MSS\hydra_MSS.cxf" ENDFILE VALUE "<project>\synthesis\hydra_syn.prj,prj" STATE="utd" -TIME="1607425586" -SIZE="8370" +TIME="1607943628" +SIZE="6757" ENDFILE VALUE "<project>\synthesis\rev_1\hydra.edn,syn_edn" -STATE="ood" -TIME="1607009112" -SIZE="24838895" +STATE="utd" +TIME="1607943440" +SIZE="24833985" ENDFILE VALUE "<project>\synthesis\rev_1\hydra.so,so" STATE="utd" -TIME="1607425585" +TIME="1607943627" SIZE="246" ENDFILE VALUE "<project>\synthesis\rev_1\hydra.v,syn_hdl" -STATE="ood" -TIME="1607425599" -SIZE="7327805" +STATE="utd" +TIME="1607943641" +SIZE="7337797" +ENDFILE +VALUE "<project>\synthesis\rev_1\hydra.vm,syn_vm" +STATE="utd" +TIME="1607943624" +SIZE="7783225" ENDFILE VALUE "<project>\synthesis\rev_1\hydra_sdc.sdc,syn_sdc" -STATE="ood" -TIME="1607009111" +STATE="utd" +TIME="1607943439" SIZE="2066" ENDFILE VALUE "<project>\synthesis\rev_1\hydra_vm.sdc,syn_sdc" STATE="utd" -TIME="1607425582" +TIME="1607943625" SIZE="2066" ENDFILE -VALUE "<project>\synthesis\rev_2\hydra_pro.so,so" -STATE="utd" -TIME="1607441572" -SIZE="250" -ENDFILE -VALUE "<project>\synthesis\rev_2\hydra_pro.vm,syn_vm" -STATE="ood" -TIME="1607441874" -SIZE="8019400" -ENDFILE -VALUE "<project>\synthesis\rev_2\hydra_pro_vm.sdc,syn_sdc" -STATE="utd" -TIME="1607441572" -SIZE="3103" -ENDFILE VALUE "G:\Users\r\rizzi\powerlink\urv-core-irq-patched\rtl\urv_config.v,hdl" LINKFILEROOT "G:/Users/r/rizzi/powerlink/urv-core-irq-patched/rtl" STATE="utd" @@ -599,6 +590,7 @@ VALUE "<project>\constraint\timing.sdc,sdc" ENDLIST LIST ProjectState5.1 LIST Impl1 +ideSYNTHESIS(<project>\synthesis\rev_1\hydra.vm,syn_vm)=StateSuccess LIST FlowOptions UsePhySynth=FALSE UseSynth=FALSE @@ -612,16 +604,29 @@ VALUE "<project>\phy_synthesis\hydra_palace.gcf,palace_gcf" VALUE "<project>\phy_synthesis\hydra_palace.pdc,palace_pdc" VALUE "<project>\phy_synthesis\hydra_palace.sdc,palace_sdc" VALUE "<project>\phy_synthesis\hydra_palace.v,palace_hdl" -VALUE "<project>\designer\impl1\hydra.adb,adb" -VALUE "<project>\designer\impl1\hydra.fdb,fdb" -VALUE "<project>\designer\impl1\hydra.pdb,pdb" -VALUE "<project>\designer\impl1\hydra.stp,stp" -VALUE "<project>\designer\impl1\hydra_fp\hydra.pro,pro" VALUE "<project>\synthesis\hydra.vm,syn_vm" VALUE "<project>\synthesis\hydra_sdc.sdc,syn_sdc" ENDUsed_File_List ENDLIST LIST Impl2 +ideSYNTHESIS(<project>\synthesis\rev_1\hydra.vm,syn_vm)=StateSuccess +LIST FlowOptions +UsePhySynth=FALSE +UseSynth=TRUE +UseFhbAutoInst=FALSE +ENDLIST +Used_File_List +VALUE "<project>\synthesis\hydra.edn,syn_edn" +VALUE "<project>\synthesis\hydra.v,syn_hdl" +VALUE "<project>\phy_synthesis\hydra_palace.edn,palace_edn" +VALUE "<project>\phy_synthesis\hydra_palace.gcf,palace_gcf" +VALUE "<project>\phy_synthesis\hydra_palace.pdc,palace_pdc" +VALUE "<project>\phy_synthesis\hydra_palace.sdc,palace_sdc" +VALUE "<project>\phy_synthesis\hydra_palace.v,palace_hdl" +ENDUsed_File_List +ENDLIST +LIST Impl3 +ideSYNTHESIS(<project>\synthesis\rev_1\hydra.vm,syn_vm)=StateSuccess LIST FlowOptions UsePhySynth=FALSE UseSynth=TRUE @@ -635,8 +640,8 @@ VALUE "<project>\phy_synthesis\hydra_palace.gcf,palace_gcf" VALUE "<project>\phy_synthesis\hydra_palace.pdc,palace_pdc" VALUE "<project>\phy_synthesis\hydra_palace.sdc,palace_sdc" VALUE "<project>\phy_synthesis\hydra_palace.v,palace_hdl" -VALUE "<project>\synthesis\rev_2\hydra_pro.vm,syn_vm" -VALUE "<project>\synthesis\rev_2\hydra_pro_sdc.sdc,syn_sdc" +VALUE "<project>\synthesis\rev_1\hydra.vm,syn_vm" +VALUE "<project>\synthesis\rev_1\hydra_sdc.sdc,syn_sdc" ENDUsed_File_List ENDLIST ENDLIST @@ -729,8 +734,8 @@ NAME="Synplify Pro ME" FUNCTION="Synthesis" TOOL="Synplify Pro ME" LOCATION="C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\bin\synplify_pro.exe" -PARAM="-licensetype synplifypro_actel -batch -log synplify.log" -BATCH=1 +PARAM="" +BATCH=0 LICENSE="" IS32BIT="1" EndProfile @@ -765,6 +770,7 @@ ENDLIST LIST ProjectState5.1 LIST "hydra::work" LIST Impl1 +ideSYNTHESIS(<project>\synthesis\rev_1\hydra.vm,syn_vm)=StateSuccess LIST FlowOptions UsePhySynth=FALSE UseSynth=FALSE @@ -778,16 +784,12 @@ VALUE "<project>\phy_synthesis\hydra_palace.gcf,palace_gcf" VALUE "<project>\phy_synthesis\hydra_palace.pdc,palace_pdc" VALUE "<project>\phy_synthesis\hydra_palace.sdc,palace_sdc" VALUE "<project>\phy_synthesis\hydra_palace.v,palace_hdl" -VALUE "<project>\designer\impl1\hydra.adb,adb" -VALUE "<project>\designer\impl1\hydra.fdb,fdb" -VALUE "<project>\designer\impl1\hydra.pdb,pdb" -VALUE "<project>\designer\impl1\hydra.stp,stp" -VALUE "<project>\designer\impl1\hydra_fp\hydra.pro,pro" VALUE "<project>\synthesis\hydra.vm,syn_vm" VALUE "<project>\synthesis\hydra_sdc.sdc,syn_sdc" ENDUsed_File_List ENDLIST LIST Impl2 +ideSYNTHESIS(<project>\synthesis\rev_1\hydra.vm,syn_vm)=StateSuccess LIST FlowOptions UsePhySynth=FALSE UseSynth=TRUE @@ -801,8 +803,25 @@ VALUE "<project>\phy_synthesis\hydra_palace.gcf,palace_gcf" VALUE "<project>\phy_synthesis\hydra_palace.pdc,palace_pdc" VALUE "<project>\phy_synthesis\hydra_palace.sdc,palace_sdc" VALUE "<project>\phy_synthesis\hydra_palace.v,palace_hdl" -VALUE "<project>\synthesis\rev_2\hydra_pro.vm,syn_vm" -VALUE "<project>\synthesis\rev_2\hydra_pro_sdc.sdc,syn_sdc" +ENDUsed_File_List +ENDLIST +LIST Impl3 +ideSYNTHESIS(<project>\synthesis\rev_1\hydra.vm,syn_vm)=StateSuccess +LIST FlowOptions +UsePhySynth=FALSE +UseSynth=TRUE +UseFhbAutoInst=FALSE +ENDLIST +Used_File_List +VALUE "<project>\synthesis\hydra.edn,syn_edn" +VALUE "<project>\synthesis\hydra.v,syn_hdl" +VALUE "<project>\phy_synthesis\hydra_palace.edn,palace_edn" +VALUE "<project>\phy_synthesis\hydra_palace.gcf,palace_gcf" +VALUE "<project>\phy_synthesis\hydra_palace.pdc,palace_pdc" +VALUE "<project>\phy_synthesis\hydra_palace.sdc,palace_sdc" +VALUE "<project>\phy_synthesis\hydra_palace.v,palace_hdl" +VALUE "<project>\synthesis\rev_1\hydra.vm,syn_vm" +VALUE "<project>\synthesis\rev_1\hydra_sdc.sdc,syn_sdc" ENDUsed_File_List ENDLIST ENDLIST @@ -827,23 +846,22 @@ ENDLIST ENDLIST LIST OpenedFileList ORIENTATION;HORIZONTAL -Reports;Reports;0 -ReportsCurrentItem;Run PROGRAM Action:hydra_PROGRAM.log -HDL;hdl\dpram_generic.vhd;0 -HDL;hdl\urv_soc.vhd;0 -HDL;constraint\fp\user.pdc;0 -HDL;hdl\axis_fifo_cdc.vhd;0 -StartPage;StartPage;0 -HDL;constraint\io\m2s050_som.io.pdc;0 -HDL;synthesis\hydra.srr;0 -HDL;hdl\reset_gen.vhd;0 -SmartDesign;hydra;0 -HDL;hdl\ueth_dma.vhd;0 Constraint Manager;Constraint Manager;0 -SmartDesign;hydra_MSS;0 HDL;constraint\timing.sdc;0 HDL;hdl\axis_assert.vhd;0 -ACTIVEVIEW;hdl\dpram_generic.vhd +StartPage;StartPage;0 +HDL;constraint\io\m2s050_som.io.pdc;0 +Reports;Reports;0 +ReportsCurrentItem;Synthesize:hydra_compile_netlist_resources.xml +HDL;hdl\axis_fifo_cdc.vhd;0 +HDL;constraint\fp\user.pdc;0 +HDL;hdl\urv_soc.vhd;0 +HDL;hdl\dpram_generic.vhd;0 +HDL;hdl\ueth_dma.vhd;0 +HDL;component\work\hydra\hydra.v;0 +HDL;hdl\reset_gen.vhd;0 +HDL;synthesis\hydra.srr;0 +ACTIVEVIEW;Constraint Manager ENDLIST LIST ModuleSubBlockList LIST "axis_assert::work","hdl\axis_assert.vhd","FALSE","FALSE" @@ -941,6 +959,7 @@ ENDLIST LIST "urv_shifter::work","G:\Users\r\rizzi\powerlink\urv-core-irq-patched\rtl\urv_shifter.v","FALSE","FALSE" ENDLIST LIST "urv_soc::work","hdl\urv_soc.vhd","FALSE","FALSE" +SUBBLOCK "dpram_generic::work","hdl\dpram_generic.vhd","FALSE","FALSE" SUBBLOCK "ram_voter::work","hdl\ram_voter.vhd","FALSE","FALSE" SUBBLOCK "seu_counters::work","hdl\seu_counters.vhd","FALSE","FALSE" SUBBLOCK "uart::work","hdl\uart.v","FALSE","FALSE" @@ -950,12 +969,11 @@ SUBBLOCK "urv_supervisor::work","hdl\urv_supervisor.vhd","FALSE","FALSE" SUBBLOCK "wb_envm::work","hdl\wb_envm.vhd","FALSE","FALSE" SUBBLOCK "wb_master_voter::work","hdl\wb_master_voter.vhd","FALSE","FALSE" SUBBLOCK "wb_slave_voter::work","hdl\wb_slave_voter.vhd","FALSE","FALSE" +SUBBLOCK "xwb_crossbar::work::wishbone_pkg","G:\Users\r\rizzi\powerlink\wb_crossbar\xwb_crossbar.vhd","FALSE","FALSE" SUBBLOCK "xwb_ram_adapter::work","hdl\xwb_ram_adapter.vhdl","FALSE","FALSE" SUBBLOCK "xwb_seu_regs::work","hdl\xwb_seu_reg.vhd","FALSE","FALSE" SUBBLOCK "xwb_uart::work","hdl\xwb_uart.vhd","FALSE","FALSE" SUBBLOCK "xwb_wd_reg::work","hdl\xwb_wd_reg.vhd","FALSE","FALSE" -SUBBLOCK "dpram_generic::work","hdl\dpram_generic.vhd","FALSE","FALSE" -SUBBLOCK "xwb_crossbar::work::wishbone_pkg","G:\Users\r\rizzi\powerlink\wb_crossbar\xwb_crossbar.vhd","FALSE","FALSE" ENDLIST LIST "urv_supervisor::work","hdl\urv_supervisor.vhd","FALSE","FALSE" SUBBLOCK "xwb_supervisor_reg::work","hdl\xwb_supervisor_reg.vhd","FALSE","FALSE" -- GitLab