From 608d3c6441d39b706930c7fcebdb6bdb2b156a78 Mon Sep 17 00:00:00 2001 From: Mattia Rizzi <mattia.rizzi@cern.ch> Date: Mon, 14 Dec 2020 11:01:36 +0100 Subject: [PATCH] Added top file --- component/work/hydra/hydra.v | 231 +++++++++++++++++++++++++++++++++++ 1 file changed, 231 insertions(+) create mode 100644 component/work/hydra/hydra.v diff --git a/component/work/hydra/hydra.v b/component/work/hydra/hydra.v new file mode 100644 index 0000000..1986b05 --- /dev/null +++ b/component/work/hydra/hydra.v @@ -0,0 +1,231 @@ +////////////////////////////////////////////////////////////////////// +// Created by SmartDesign Tue Dec 08 14:54:39 2020 +// Version: v11.8 11.8.0.26 +////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 100ps + +// hydra +module hydra( + // Inputs + CLK_I, + DEVRST_N, + ETH_RXD_I, + ETH_RXERR_I, + ETH_RX_CLK_I, + ETH_RX_DV_I, + ETH_TX_CLK_I, + RST_I, + // Outputs + ETH_MDC_O, + ETH_TXD_O, + ETH_TXERR_O, + ETH_TX_EN_O, + GPIO_LED1, + GPIO_LED2, + uart_tx_o, + // Inouts + ETH_MDIO +); + +//-------------------------------------------------------------------- +// Input +//-------------------------------------------------------------------- +input CLK_I; +input DEVRST_N; +input [3:0] ETH_RXD_I; +input ETH_RXERR_I; +input ETH_RX_CLK_I; +input ETH_RX_DV_I; +input ETH_TX_CLK_I; +input RST_I; +//-------------------------------------------------------------------- +// Output +//-------------------------------------------------------------------- +output ETH_MDC_O; +output [3:0] ETH_TXD_O; +output ETH_TXERR_O; +output ETH_TX_EN_O; +output GPIO_LED1; +output GPIO_LED2; +output uart_tx_o; +//-------------------------------------------------------------------- +// Inout +//-------------------------------------------------------------------- +inout ETH_MDIO; +//-------------------------------------------------------------------- +// Nets +//-------------------------------------------------------------------- +wire BIBUF_0_Y; +wire CLK_I; +wire [39:0] clock_buffer_0_clk_ram_o; +wire clock_buffer_0_clk_sys_o; +wire DEVRST_N; +wire eth_mdc_o_net_0; +wire ETH_MDIO; +wire ETH_RX_CLK_I; +wire ETH_RX_DV_I; +wire [3:0] ETH_RXD_I; +wire ETH_RXERR_I; +wire ETH_TX_CLK_I; +wire ETH_TX_EN_O_net_0; +wire [3:0] eth_txd_o_net_0; +wire eth_txerr_o_net_0; +wire GPIO_LED1_net_0; +wire GPIO_LED2_net_0; +wire [31:0] hydra_MSS_0_FIC_0_APB_S_PRDATA; +wire hydra_MSS_0_FIC_0_APB_S_PREADY; +wire hydra_MSS_0_FIC_0_APB_S_PSLVERR; +wire RST_I; +wire SYSRESET_0_POWER_ON_RESET_N; +wire uart_tx_o_net_0; +wire [31:0] urv_soc_0_apb_paddr_o; +wire urv_soc_0_apb_pen_o; +wire urv_soc_0_apb_psel_o; +wire [31:0] urv_soc_0_apb_pwdat_o; +wire urv_soc_0_apb_pwr_o; +wire urv_soc_0_eth_md_o; +wire urv_soc_0_eth_oe_o; +wire urv_soc_0_reboot_o; +wire eth_txerr_o_net_1; +wire ETH_TX_EN_O_net_1; +wire eth_mdc_o_net_1; +wire uart_tx_o_net_1; +wire GPIO_LED1_net_1; +wire GPIO_LED2_net_1; +wire [3:0] eth_txd_o_net_1; +//-------------------------------------------------------------------- +// TiedOff Nets +//-------------------------------------------------------------------- +wire GND_net; +//-------------------------------------------------------------------- +// Inverted Nets +//-------------------------------------------------------------------- +wire MSS_RESET_N_F2M_IN_POST_INV0_0; +wire rst_por_i_IN_POST_INV1_0; +wire rst_btn_i_IN_POST_INV2_0; +wire DEVRST_I_IN_POST_INV3_0; +//-------------------------------------------------------------------- +// Constant assignments +//-------------------------------------------------------------------- +assign GND_net = 1'b0; +//-------------------------------------------------------------------- +// Inversions +//-------------------------------------------------------------------- +assign MSS_RESET_N_F2M_IN_POST_INV0_0 = ~ GPIO_LED2_net_0; +assign rst_por_i_IN_POST_INV1_0 = ~ SYSRESET_0_POWER_ON_RESET_N; +assign rst_btn_i_IN_POST_INV2_0 = ~ RST_I; +assign DEVRST_I_IN_POST_INV3_0 = ~ SYSRESET_0_POWER_ON_RESET_N; +//-------------------------------------------------------------------- +// Top level output port assignments +//-------------------------------------------------------------------- +assign eth_txerr_o_net_1 = eth_txerr_o_net_0; +assign ETH_TXERR_O = eth_txerr_o_net_1; +assign ETH_TX_EN_O_net_1 = ETH_TX_EN_O_net_0; +assign ETH_TX_EN_O = ETH_TX_EN_O_net_1; +assign eth_mdc_o_net_1 = eth_mdc_o_net_0; +assign ETH_MDC_O = eth_mdc_o_net_1; +assign uart_tx_o_net_1 = uart_tx_o_net_0; +assign uart_tx_o = uart_tx_o_net_1; +assign GPIO_LED1_net_1 = GPIO_LED1_net_0; +assign GPIO_LED1 = GPIO_LED1_net_1; +assign GPIO_LED2_net_1 = GPIO_LED2_net_0; +assign GPIO_LED2 = GPIO_LED2_net_1; +assign eth_txd_o_net_1 = eth_txd_o_net_0; +assign ETH_TXD_O[3:0] = eth_txd_o_net_1; +//-------------------------------------------------------------------- +// Component instances +//-------------------------------------------------------------------- +//--------BIBUF +BIBUF BIBUF_0( + // Inputs + .D ( urv_soc_0_eth_md_o ), + .E ( urv_soc_0_eth_oe_o ), + // Outputs + .Y ( BIBUF_0_Y ), + // Inouts + .PAD ( ETH_MDIO ) + ); + +//--------clock_buffer +clock_buffer clock_buffer_0( + // Inputs + .clk_i ( CLK_I ), + // Outputs + .clk_sys_o ( clock_buffer_0_clk_sys_o ), + .clk_ram_o ( clock_buffer_0_clk_ram_o ) + ); + +//--------hydra_MSS +hydra_MSS hydra_MSS_0( + // Inputs + .MCCC_CLK_BASE ( clock_buffer_0_clk_sys_o ), + .FIC_0_APB_S_PSEL ( urv_soc_0_apb_psel_o ), + .FIC_0_APB_S_PWRITE ( urv_soc_0_apb_pwr_o ), + .FIC_0_APB_S_PENABLE ( urv_soc_0_apb_pen_o ), + .MSS_RESET_N_F2M ( MSS_RESET_N_F2M_IN_POST_INV0_0 ), + .M3_RESET_N ( GND_net ), + .FIC_0_APB_S_PADDR ( urv_soc_0_apb_paddr_o ), + .FIC_0_APB_S_PWDATA ( urv_soc_0_apb_pwdat_o ), + // Outputs + .FIC_0_APB_S_PREADY ( hydra_MSS_0_FIC_0_APB_S_PREADY ), + .FIC_0_APB_S_PSLVERR ( hydra_MSS_0_FIC_0_APB_S_PSLVERR ), + .MSS_RESET_N_M2F ( ), + .FIC_0_APB_S_PRDATA ( hydra_MSS_0_FIC_0_APB_S_PRDATA ) + ); + +//--------reset_gen +reset_gen reset_gen_0( + // Inputs + .clk_i ( clock_buffer_0_clk_sys_o ), + .rst_por_i ( rst_por_i_IN_POST_INV1_0 ), + .rst_btn_i ( rst_btn_i_IN_POST_INV2_0 ), + .wd_i ( urv_soc_0_reboot_o ), + // Outputs + .rst_soc_o ( GPIO_LED1_net_0 ), + .rst_mss_o ( GPIO_LED2_net_0 ) + ); + +//--------urv_soc +urv_soc soc( + // Inputs + .clk_i ( clock_buffer_0_clk_sys_o ), + .clk_ram_i ( clock_buffer_0_clk_ram_o ), + .rst_i ( GPIO_LED1_net_0 ), + .DEVRST_I ( DEVRST_I_IN_POST_INV3_0 ), + .apb_prdat_i ( hydra_MSS_0_FIC_0_APB_S_PRDATA ), + .apb_pready_i ( hydra_MSS_0_FIC_0_APB_S_PREADY ), + .apb_pslverr_i ( hydra_MSS_0_FIC_0_APB_S_PSLVERR ), + .eth_tx_clk_i ( ETH_TX_CLK_I ), + .eth_rx_clk_i ( ETH_RX_CLK_I ), + .eth_rxd_i ( ETH_RXD_I ), + .eth_rxdv_i ( ETH_RX_DV_I ), + .eth_rxerr_i ( ETH_RXERR_I ), + .eth_md_i ( BIBUF_0_Y ), + // Outputs + .apb_psel_o ( urv_soc_0_apb_psel_o ), + .apb_pwr_o ( urv_soc_0_apb_pwr_o ), + .apb_pen_o ( urv_soc_0_apb_pen_o ), + .apb_paddr_o ( urv_soc_0_apb_paddr_o ), + .apb_pwdat_o ( urv_soc_0_apb_pwdat_o ), + .uart_tx_o ( uart_tx_o_net_0 ), + .eth_txd_o ( eth_txd_o_net_0 ), + .eth_txen_o ( ETH_TX_EN_O_net_0 ), + .eth_txerr_o ( eth_txerr_o_net_0 ), + .eth_mdc_o ( eth_mdc_o_net_0 ), + .eth_md_o ( urv_soc_0_eth_md_o ), + .eth_oe_o ( urv_soc_0_eth_oe_o ), + .eth_rst_o ( ), + .reboot_o ( urv_soc_0_reboot_o ) + ); + +//--------SYSRESET +SYSRESET SYSRESET_0( + // Inputs + .DEVRST_N ( DEVRST_N ), + // Outputs + .POWER_ON_RESET_N ( SYSRESET_0_POWER_ON_RESET_N ) + ); + + +endmodule -- GitLab